refactor(core): extract pin configuration from NRF driver to board definition

diff --git a/core/embed/io/nrf/stm32u5/nrf.c b/core/embed/io/nrf/stm32u5/nrf.c
index 038704a2..a90fad52 100644
--- a/core/embed/io/nrf/stm32u5/nrf.c
+++ b/core/embed/io/nrf/stm32u5/nrf.c
@@ -190,7 +190,7 @@ void nrf_init(void) {
   EXTI_Config.Mode = EXTI_MODE_INTERRUPT;
   EXTI_Config.Trigger = EXTI_TRIGGER_RISING;
   HAL_EXTI_SetConfigLine(&drv->exti, &EXTI_Config);
-  __HAL_GPIO_EXTI_CLEAR_FLAG(NRF_EXTI_INTERRUPT_PIN);
+  __HAL_GPIO_EXTI_CLEAR_IT(NRF_EXTI_INTERRUPT_PIN);
 
 #ifdef USE_SMP
   nrf_uart_init(drv);
@@ -208,15 +208,15 @@ void nrf_init(void) {
   nrf_start();
 
 #ifdef USE_SMP
-  NVIC_SetPriority(USART3_IRQn, IRQ_PRI_NORMAL);
-  NVIC_EnableIRQ(USART3_IRQn);
+  NVIC_SetPriority(NRF_UART_IRQN, IRQ_PRI_NORMAL);
+  NVIC_EnableIRQ(NRF_UART_IRQN);
 #endif
   NVIC_SetPriority(GPDMA1_Channel1_IRQn, IRQ_PRI_NORMAL);
   NVIC_EnableIRQ(GPDMA1_Channel1_IRQn);
   NVIC_SetPriority(GPDMA1_Channel2_IRQn, IRQ_PRI_NORMAL);
   NVIC_EnableIRQ(GPDMA1_Channel2_IRQn);
-  NVIC_SetPriority(SPI1_IRQn, IRQ_PRI_NORMAL);
-  NVIC_EnableIRQ(SPI1_IRQn);
+  NVIC_SetPriority(NRF_SPI_IRQN, IRQ_PRI_NORMAL);
+  NVIC_EnableIRQ(NRF_SPI_IRQN);
   NVIC_SetPriority(NRF_EXTI_INTERRUPT_NUM, IRQ_PRI_NORMAL);
   NVIC_EnableIRQ(NRF_EXTI_INTERRUPT_NUM);
 
@@ -232,11 +232,11 @@ static void nrf_deinit_common(nrf_driver_t *drv) {
   systimer_delete(drv->timer);
 
 #ifdef USE_SMP
-  NVIC_DisableIRQ(USART3_IRQn);
+  NVIC_DisableIRQ(NRF_UART_IRQN);
 #endif
   NVIC_DisableIRQ(GPDMA1_Channel1_IRQn);
   NVIC_DisableIRQ(GPDMA1_Channel2_IRQn);
-  NVIC_DisableIRQ(SPI1_IRQn);
+  NVIC_DisableIRQ(NRF_SPI_IRQN);
 
   HAL_GPIO_DeInit(NRF_OUT_RESET_PORT, NRF_OUT_RESET_PIN);
   HAL_GPIO_DeInit(NRF_OUT_SPI_READY_PORT, NRF_OUT_SPI_READY_PIN);
@@ -309,11 +309,11 @@ void nrf_resume(void) {
   nrf_spi_init(drv);
 
 #ifdef USE_SMP
-  NVIC_EnableIRQ(USART3_IRQn);
+  NVIC_EnableIRQ(NRF_UART_IRQN);
 #endif
   NVIC_EnableIRQ(GPDMA1_Channel1_IRQn);
   NVIC_EnableIRQ(GPDMA1_Channel2_IRQn);
-  NVIC_EnableIRQ(SPI1_IRQn);
+  NVIC_EnableIRQ(NRF_SPI_IRQN);
 
   nrf_start();
 
@@ -392,7 +392,7 @@ void NRF_EXTI_INTERRUPT_HANDLER(void) {
     }
   }
   // Clear the EXTI line pending bit
-  __HAL_GPIO_EXTI_CLEAR_FLAG(NRF_EXTI_INTERRUPT_PIN);
+  __HAL_GPIO_EXTI_CLEAR_IT(NRF_EXTI_INTERRUPT_PIN);
 
   mpu_restore(mpu_mode);
   IRQ_LOG_EXIT();
diff --git a/core/embed/io/nrf/stm32u5/nrf_spi.c b/core/embed/io/nrf/stm32u5/nrf_spi.c
index d611ee21..75e9c4cf 100644
--- a/core/embed/io/nrf/stm32u5/nrf_spi.c
+++ b/core/embed/io/nrf/stm32u5/nrf_spi.c
@@ -41,20 +41,34 @@ void nrf_spi_init(nrf_driver_t *drv) {
   GPIO_InitTypeDef GPIO_InitStructure = {0};
 
   __HAL_RCC_GPDMA1_CLK_ENABLE();
-  __HAL_RCC_SPI1_CLK_ENABLE();
+  NRF_SPI_CLK_EN();
+  NRF_SPI_SCK_CLK_EN();
+  NRF_SPI_NSS_CLK_EN();
+  NRF_SPI_MISO_CLK_EN();
+  NRF_SPI_MOSI_CLK_EN();
 
   // SPI pins
   GPIO_InitStructure.Mode = GPIO_MODE_AF_PP;
   GPIO_InitStructure.Pull = GPIO_NOPULL;
-  GPIO_InitStructure.Alternate = GPIO_AF5_SPI1;
+  GPIO_InitStructure.Alternate = NRF_SPI_PIN_AF;
   GPIO_InitStructure.Speed = GPIO_SPEED_FREQ_MEDIUM;
-  GPIO_InitStructure.Pin = GPIO_PIN_1 | GPIO_PIN_4 | GPIO_PIN_6 | GPIO_PIN_7;
-  HAL_GPIO_Init(GPIOA, &GPIO_InitStructure);
+
+  GPIO_InitStructure.Pin = NRF_SPI_SCK_PIN;
+  HAL_GPIO_Init(NRF_SPI_SCK_PORT, &GPIO_InitStructure);
+
+  GPIO_InitStructure.Pin = NRF_SPI_NSS_PIN;
+  HAL_GPIO_Init(NRF_SPI_NSS_PORT, &GPIO_InitStructure);
+
+  GPIO_InitStructure.Pin = NRF_SPI_MISO_PIN;
+  HAL_GPIO_Init(NRF_SPI_MISO_PORT, &GPIO_InitStructure);
+
+  GPIO_InitStructure.Pin = NRF_SPI_MOSI_PIN;
+  HAL_GPIO_Init(NRF_SPI_MOSI_PORT, &GPIO_InitStructure);
 
   drv->spi_rx_dma.Instance = GPDMA1_Channel2;
   drv->spi_rx_dma.Init.Direction = DMA_PERIPH_TO_MEMORY;
   drv->spi_rx_dma.Init.Mode = DMA_NORMAL;
-  drv->spi_rx_dma.Init.Request = GPDMA1_REQUEST_SPI1_RX;
+  drv->spi_rx_dma.Init.Request = NRF_SPI_DMA_RX_REQUEST;
   drv->spi_rx_dma.Init.BlkHWRequest = DMA_BREQ_SINGLE_BURST;
   drv->spi_rx_dma.Init.SrcInc = DMA_SINC_FIXED;
   drv->spi_rx_dma.Init.DestInc = DMA_DINC_INCREMENTED;
@@ -76,7 +90,7 @@ void nrf_spi_init(nrf_driver_t *drv) {
   drv->spi_tx_dma.Init.Direction = DMA_MEMORY_TO_PERIPH;
   drv->spi_tx_dma.Init.Mode = DMA_NORMAL;
   drv->spi_tx_dma.Instance = GPDMA1_Channel1;
-  drv->spi_tx_dma.Init.Request = GPDMA1_REQUEST_SPI1_TX;
+  drv->spi_tx_dma.Init.Request = NRF_SPI_DMA_TX_REQUEST;
   drv->spi_tx_dma.Init.BlkHWRequest = DMA_BREQ_SINGLE_BURST;
   drv->spi_tx_dma.Init.SrcInc = DMA_SINC_INCREMENTED;
   drv->spi_tx_dma.Init.DestInc = DMA_DINC_FIXED;
@@ -94,7 +108,7 @@ void nrf_spi_init(nrf_driver_t *drv) {
       &drv->spi_tx_dma, DMA_CHANNEL_PRIV | DMA_CHANNEL_SEC |
                             DMA_CHANNEL_SRC_SEC | DMA_CHANNEL_DEST_SEC);
 
-  drv->spi.Instance = SPI1;
+  drv->spi.Instance = NRF_SPI_INSTANCE;
   drv->spi.Init.Mode = SPI_MODE_SLAVE;
   drv->spi.Init.Direction = SPI_DIRECTION_2LINES;
   drv->spi.Init.DataSize = SPI_DATASIZE_8BIT;
@@ -113,13 +127,20 @@ void nrf_spi_init(nrf_driver_t *drv) {
 }
 
 void nrf_spi_deinit(void) {
-  __HAL_RCC_SPI1_FORCE_RESET();
-  __HAL_RCC_SPI1_RELEASE_RESET();
+  nrf_driver_t *drv = &g_nrf_driver;
+
+  HAL_DMA_DeInit(&drv->spi_rx_dma);
+  HAL_DMA_DeInit(&drv->spi_tx_dma);
+
+  NRF_SPI_FORCE_RESET();
+  NRF_SPI_RELEASE_RESET();
+
+  HAL_GPIO_DeInit(NRF_SPI_SCK_PORT, NRF_SPI_SCK_PIN);
+  HAL_GPIO_DeInit(NRF_SPI_NSS_PORT, NRF_SPI_NSS_PIN);
+  HAL_GPIO_DeInit(NRF_SPI_MISO_PORT, NRF_SPI_MISO_PIN);
+  HAL_GPIO_DeInit(NRF_SPI_MOSI_PORT, NRF_SPI_MOSI_PIN);
 
-  HAL_GPIO_DeInit(GPIOA, GPIO_PIN_1);
-  HAL_GPIO_DeInit(GPIOA, GPIO_PIN_4);
-  HAL_GPIO_DeInit(GPIOA, GPIO_PIN_6);
-  HAL_GPIO_DeInit(GPIOA, GPIO_PIN_7);
+  NRF_SPI_CLK_DIS();
 }
 
 int32_t nrf_send_msg(nrf_service_id_t service, const uint8_t *data,
@@ -236,7 +257,7 @@ void GPDMA1_Channel2_IRQHandler(void) {
   IRQ_LOG_EXIT();
 }
 
-void SPI1_IRQHandler(void) {
+void NRF_SPI_INTERRUPT_HANDLER(void) {
   IRQ_LOG_ENTER();
 
   mpu_mode_t mpu_mode = mpu_reconfig(MPU_MODE_DEFAULT);
diff --git a/core/embed/io/nrf/stm32u5/nrf_uart.c b/core/embed/io/nrf/stm32u5/nrf_uart.c
index 9a6eccb8..8f96dca6 100644
--- a/core/embed/io/nrf/stm32u5/nrf_uart.c
+++ b/core/embed/io/nrf/stm32u5/nrf_uart.c
@@ -32,25 +32,32 @@
 extern nrf_driver_t g_nrf_driver;
 
 static void nrf_uart_init_peripherals(nrf_driver_t *drv, uint32_t baudrate) {
-  __HAL_RCC_USART3_FORCE_RESET();
-  __HAL_RCC_USART3_RELEASE_RESET();
-  __HAL_RCC_USART3_CLK_ENABLE();
+  NRF_UART_FORCE_RESET();
+  NRF_UART_RELEASE_RESET();
+  NRF_UART_CLK_EN();
+
+  NRF_UART_TX_CLK_EN();
+  NRF_UART_RX_CLK_EN();
+  NRF_UART_RTS_CLK_EN();
+  NRF_UART_CTS_CLK_EN();
 
   GPIO_InitTypeDef GPIO_InitStructure = {0};
   // UART PINS
   GPIO_InitStructure.Mode = GPIO_MODE_AF_PP;
   GPIO_InitStructure.Pull = GPIO_NOPULL;
-  GPIO_InitStructure.Alternate = GPIO_AF7_USART3;
+  GPIO_InitStructure.Alternate = NRF_UART_PIN_AF;
   GPIO_InitStructure.Speed = GPIO_SPEED_FREQ_LOW;
 
-  GPIO_InitStructure.Pin = GPIO_PIN_10 | GPIO_PIN_1;
-  HAL_GPIO_Init(GPIOB, &GPIO_InitStructure);
+  GPIO_InitStructure.Pin = NRF_UART_TX_PIN;
+  HAL_GPIO_Init(NRF_UART_TX_PORT, &GPIO_InitStructure);
+  GPIO_InitStructure.Pin = NRF_UART_RTS_PIN;
+  HAL_GPIO_Init(NRF_UART_RTS_PORT, &GPIO_InitStructure);
 
   GPIO_InitStructure.Pull = GPIO_PULLUP;
-  GPIO_InitStructure.Pin = GPIO_PIN_11;
-  HAL_GPIO_Init(GPIOD, &GPIO_InitStructure);
-  GPIO_InitStructure.Pin = GPIO_PIN_5;
-  HAL_GPIO_Init(GPIOA, &GPIO_InitStructure);
+  GPIO_InitStructure.Pin = NRF_UART_CTS_PIN;
+  HAL_GPIO_Init(NRF_UART_CTS_PORT, &GPIO_InitStructure);
+  GPIO_InitStructure.Pin = NRF_UART_RX_PIN;
+  HAL_GPIO_Init(NRF_UART_RX_PORT, &GPIO_InitStructure);
 
   drv->urt.Init.Mode = UART_MODE_TX_RX;
   drv->urt.Init.BaudRate = baudrate;
@@ -59,7 +66,7 @@ static void nrf_uart_init_peripherals(nrf_driver_t *drv, uint32_t baudrate) {
   drv->urt.Init.Parity = UART_PARITY_NONE;
   drv->urt.Init.StopBits = UART_STOPBITS_1;
   drv->urt.Init.WordLength = UART_WORDLENGTH_8B;
-  drv->urt.Instance = USART3;
+  drv->urt.Instance = NRF_UART_INSTANCE;
   HAL_UART_Init(&drv->urt);
 }
 
@@ -68,12 +75,13 @@ void nrf_uart_init(nrf_driver_t *drv) {
 }
 
 void nrf_uart_deinit(void) {
-  __HAL_RCC_USART3_FORCE_RESET();
-  __HAL_RCC_USART3_RELEASE_RESET();
-  HAL_GPIO_DeInit(GPIOB, GPIO_PIN_10);
-  HAL_GPIO_DeInit(GPIOB, GPIO_PIN_1);
-  HAL_GPIO_DeInit(GPIOD, GPIO_PIN_11);
-  HAL_GPIO_DeInit(GPIOA, GPIO_PIN_5);
+  NRF_UART_FORCE_RESET();
+  NRF_UART_RELEASE_RESET();
+  HAL_GPIO_DeInit(NRF_UART_TX_PORT, NRF_UART_TX_PIN);
+  HAL_GPIO_DeInit(NRF_UART_RX_PORT, NRF_UART_RX_PIN);
+  HAL_GPIO_DeInit(NRF_UART_RTS_PORT, NRF_UART_RTS_PIN);
+  HAL_GPIO_DeInit(NRF_UART_CTS_PORT, NRF_UART_CTS_PIN);
+  NRF_UART_CLK_DIS();
 }
 
 void nrf_uart_send(uint8_t data) {
@@ -144,7 +152,7 @@ void HAL_UART_TxCpltCallback(UART_HandleTypeDef *urt) {
   }
 }
 
-void USART3_IRQHandler(void) {
+void NRF_UART_INTERRUPT_HANDLER(void) {
   IRQ_LOG_ENTER();
 
   mpu_mode_t mpu_mode = mpu_reconfig(MPU_MODE_DEFAULT);
diff --git a/core/embed/models/T3W1/boards/trezor_t3w1_revA.h b/core/embed/models/T3W1/boards/trezor_t3w1_revA.h
index bdd4501e..f8fee412 100644
--- a/core/embed/models/T3W1/boards/trezor_t3w1_revA.h
+++ b/core/embed/models/T3W1/boards/trezor_t3w1_revA.h
@@ -194,15 +194,28 @@
 #define SBU_2_PORT GPIOC
 #define SBU_2_CLK_ENA __HAL_RCC_GPIOC_CLK_ENABLE
 
-#define NRF_IN_RESERVED_PIN GPIO_PIN_7
-#define NRF_IN_RESERVED_PORT GPIOE
-#define NRF_IN_RESERVED_CLK_ENA __HAL_RCC_GPIOE_CLK_ENABLE
-#define NRF_OUT_RESET_PIN GPIO_PIN_0
-#define NRF_OUT_RESET_PORT GPIOG
-#define NRF_OUT_RESET_CLK_ENA __HAL_RCC_GPIOG_CLK_ENABLE
-#define NRF_OUT_STAY_IN_BLD_PIN GPIO_PIN_15
-#define NRF_OUT_STAY_IN_BLD_PORT GPIOE
-#define NRF_OUT_STAY_IN_BLD_CLK_ENA __HAL_RCC_GPIOE_CLK_ENABLE
+#define NRF_SPI_INSTANCE SPI1
+#define NRF_SPI_CLK_EN __HAL_RCC_SPI1_CLK_ENABLE
+#define NRF_SPI_CLK_DIS __HAL_RCC_SPI1_CLK_DISABLE
+#define NRF_SPI_FORCE_RESET __HAL_RCC_SPI1_FORCE_RESET
+#define NRF_SPI_RELEASE_RESET __HAL_RCC_SPI1_RELEASE_RESET
+#define NRF_SPI_PIN_AF GPIO_AF5_SPI1
+#define NRF_SPI_DMA_RX_REQUEST GPDMA1_REQUEST_SPI1_RX
+#define NRF_SPI_DMA_TX_REQUEST GPDMA1_REQUEST_SPI1_TX
+#define NRF_SPI_INTERRUPT_HANDLER SPI1_IRQHandler
+#define NRF_SPI_IRQN SPI1_IRQn
+#define NRF_SPI_SCK_PORT GPIOA
+#define NRF_SPI_SCK_PIN GPIO_PIN_1
+#define NRF_SPI_SCK_CLK_EN __HAL_RCC_GPIOA_CLK_ENABLE
+#define NRF_SPI_NSS_PORT GPIOA
+#define NRF_SPI_NSS_PIN GPIO_PIN_4
+#define NRF_SPI_NSS_CLK_EN __HAL_RCC_GPIOA_CLK_ENABLE
+#define NRF_SPI_MISO_PORT GPIOA
+#define NRF_SPI_MISO_PIN GPIO_PIN_6
+#define NRF_SPI_MISO_CLK_EN __HAL_RCC_GPIOA_CLK_ENABLE
+#define NRF_SPI_MOSI_PORT GPIOA
+#define NRF_SPI_MOSI_PIN GPIO_PIN_7
+#define NRF_SPI_MOSI_CLK_EN __HAL_RCC_GPIOA_CLK_ENABLE
 #define NRF_OUT_SPI_READY_PIN GPIO_PIN_13
 #define NRF_OUT_SPI_READY_PORT GPIOE
 #define NRF_OUT_SPI_READY_CLK_ENA __HAL_RCC_GPIOE_CLK_ENABLE
@@ -215,6 +228,37 @@
 #define NRF_EXTI_INTERRUPT_NUM EXTI11_IRQn
 #define NRF_EXTI_INTERRUPT_HANDLER EXTI11_IRQHandler
 
+#define NRF_IN_RESERVED_PIN GPIO_PIN_7
+#define NRF_IN_RESERVED_PORT GPIOE
+#define NRF_IN_RESERVED_CLK_ENA __HAL_RCC_GPIOE_CLK_ENABLE
+#define NRF_OUT_RESET_PIN GPIO_PIN_0
+#define NRF_OUT_RESET_PORT GPIOG
+#define NRF_OUT_RESET_CLK_ENA __HAL_RCC_GPIOG_CLK_ENABLE
+#define NRF_OUT_STAY_IN_BLD_PIN GPIO_PIN_15
+#define NRF_OUT_STAY_IN_BLD_PORT GPIOE
+#define NRF_OUT_STAY_IN_BLD_CLK_ENA __HAL_RCC_GPIOE_CLK_ENABLE
+
+#define NRF_UART_INSTANCE USART3
+#define NRF_UART_CLK_EN __HAL_RCC_USART3_CLK_ENABLE
+#define NRF_UART_CLK_DIS __HAL_RCC_USART3_CLK_DISABLE
+#define NRF_UART_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET
+#define NRF_UART_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET
+#define NRF_UART_INTERRUPT_HANDLER USART3_IRQHandler
+#define NRF_UART_IRQN USART3_IRQn
+#define NRF_UART_PIN_AF GPIO_AF7_USART3
+#define NRF_UART_TX_PORT GPIOB
+#define NRF_UART_TX_PIN GPIO_PIN_10
+#define NRF_UART_TX_CLK_EN __HAL_RCC_GPIOB_CLK_ENABLE
+#define NRF_UART_RX_PORT GPIOB
+#define NRF_UART_RX_PIN GPIO_PIN_1
+#define NRF_UART_RX_CLK_EN __HAL_RCC_GPIOB_CLK_ENABLE
+#define NRF_UART_RTS_PORT GPIOD
+#define NRF_UART_RTS_PIN GPIO_PIN_11
+#define NRF_UART_RTS_CLK_EN __HAL_RCC_GPIOD_CLK_ENABLE
+#define NRF_UART_CTS_PORT GPIOA
+#define NRF_UART_CTS_PIN GPIO_PIN_5
+#define NRF_UART_CTS_CLK_EN __HAL_RCC_GPIOA_CLK_ENABLE
+
 #define ST25R3916B
 #define NFC_SPI_INSTANCE SPI3
 #define NFC_SPI_PIN_AF GPIO_AF6_SPI3
diff --git a/core/embed/models/T3W1/boards/trezor_t3w1_revB.h b/core/embed/models/T3W1/boards/trezor_t3w1_revB.h
index 5d02ea2d..b375e86b 100644
--- a/core/embed/models/T3W1/boards/trezor_t3w1_revB.h
+++ b/core/embed/models/T3W1/boards/trezor_t3w1_revB.h
@@ -194,15 +194,28 @@
 #define SBU_2_PORT GPIOC
 #define SBU_2_CLK_ENA __HAL_RCC_GPIOC_CLK_ENABLE
 
-#define NRF_IN_RESERVED_PIN GPIO_PIN_7
-#define NRF_IN_RESERVED_PORT GPIOE
-#define NRF_IN_RESERVED_CLK_ENA __HAL_RCC_GPIOE_CLK_ENABLE
-#define NRF_OUT_RESET_PIN GPIO_PIN_0
-#define NRF_OUT_RESET_PORT GPIOG
-#define NRF_OUT_RESET_CLK_ENA __HAL_RCC_GPIOG_CLK_ENABLE
-#define NRF_OUT_STAY_IN_BLD_PIN GPIO_PIN_15
-#define NRF_OUT_STAY_IN_BLD_PORT GPIOE
-#define NRF_OUT_STAY_IN_BLD_CLK_ENA __HAL_RCC_GPIOE_CLK_ENABLE
+#define NRF_SPI_INSTANCE SPI1
+#define NRF_SPI_CLK_EN __HAL_RCC_SPI1_CLK_ENABLE
+#define NRF_SPI_CLK_DIS __HAL_RCC_SPI1_CLK_DISABLE
+#define NRF_SPI_FORCE_RESET __HAL_RCC_SPI1_FORCE_RESET
+#define NRF_SPI_RELEASE_RESET __HAL_RCC_SPI1_RELEASE_RESET
+#define NRF_SPI_PIN_AF GPIO_AF5_SPI1
+#define NRF_SPI_DMA_RX_REQUEST GPDMA1_REQUEST_SPI1_RX
+#define NRF_SPI_DMA_TX_REQUEST GPDMA1_REQUEST_SPI1_TX
+#define NRF_SPI_INTERRUPT_HANDLER SPI1_IRQHandler
+#define NRF_SPI_IRQN SPI1_IRQn
+#define NRF_SPI_SCK_PORT GPIOA
+#define NRF_SPI_SCK_PIN GPIO_PIN_1
+#define NRF_SPI_SCK_CLK_EN __HAL_RCC_GPIOA_CLK_ENABLE
+#define NRF_SPI_NSS_PORT GPIOA
+#define NRF_SPI_NSS_PIN GPIO_PIN_4
+#define NRF_SPI_NSS_CLK_EN __HAL_RCC_GPIOA_CLK_ENABLE
+#define NRF_SPI_MISO_PORT GPIOA
+#define NRF_SPI_MISO_PIN GPIO_PIN_6
+#define NRF_SPI_MISO_CLK_EN __HAL_RCC_GPIOA_CLK_ENABLE
+#define NRF_SPI_MOSI_PORT GPIOA
+#define NRF_SPI_MOSI_PIN GPIO_PIN_7
+#define NRF_SPI_MOSI_CLK_EN __HAL_RCC_GPIOA_CLK_ENABLE
 #define NRF_OUT_SPI_READY_PIN GPIO_PIN_13
 #define NRF_OUT_SPI_READY_PORT GPIOE
 #define NRF_OUT_SPI_READY_CLK_ENA __HAL_RCC_GPIOE_CLK_ENABLE
@@ -215,6 +228,37 @@
 #define NRF_EXTI_INTERRUPT_NUM EXTI11_IRQn
 #define NRF_EXTI_INTERRUPT_HANDLER EXTI11_IRQHandler
 
+#define NRF_IN_RESERVED_PIN GPIO_PIN_7
+#define NRF_IN_RESERVED_PORT GPIOE
+#define NRF_IN_RESERVED_CLK_ENA __HAL_RCC_GPIOE_CLK_ENABLE
+#define NRF_OUT_RESET_PIN GPIO_PIN_0
+#define NRF_OUT_RESET_PORT GPIOG
+#define NRF_OUT_RESET_CLK_ENA __HAL_RCC_GPIOG_CLK_ENABLE
+#define NRF_OUT_STAY_IN_BLD_PIN GPIO_PIN_15
+#define NRF_OUT_STAY_IN_BLD_PORT GPIOE
+#define NRF_OUT_STAY_IN_BLD_CLK_ENA __HAL_RCC_GPIOE_CLK_ENABLE
+
+#define NRF_UART_INSTANCE USART3
+#define NRF_UART_CLK_EN __HAL_RCC_USART3_CLK_ENABLE
+#define NRF_UART_CLK_DIS __HAL_RCC_USART3_CLK_DISABLE
+#define NRF_UART_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET
+#define NRF_UART_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET
+#define NRF_UART_INTERRUPT_HANDLER USART3_IRQHandler
+#define NRF_UART_IRQN USART3_IRQn
+#define NRF_UART_PIN_AF GPIO_AF7_USART3
+#define NRF_UART_TX_PORT GPIOB
+#define NRF_UART_TX_PIN GPIO_PIN_10
+#define NRF_UART_TX_CLK_EN __HAL_RCC_GPIOB_CLK_ENABLE
+#define NRF_UART_RX_PORT GPIOB
+#define NRF_UART_RX_PIN GPIO_PIN_1
+#define NRF_UART_RX_CLK_EN __HAL_RCC_GPIOB_CLK_ENABLE
+#define NRF_UART_RTS_PORT GPIOD
+#define NRF_UART_RTS_PIN GPIO_PIN_11
+#define NRF_UART_RTS_CLK_EN __HAL_RCC_GPIOD_CLK_ENABLE
+#define NRF_UART_CTS_PORT GPIOA
+#define NRF_UART_CTS_PIN GPIO_PIN_5
+#define NRF_UART_CTS_CLK_EN __HAL_RCC_GPIOA_CLK_ENABLE
+
 #define ST25R3916B
 #define NFC_SPI_INSTANCE SPI3
 #define NFC_SPI_PIN_AF GPIO_AF6_SPI3
diff --git a/core/embed/models/T3W1/boards/trezor_t3w1_revC.h b/core/embed/models/T3W1/boards/trezor_t3w1_revC.h
index e8f2fc92..c9863dd6 100644
--- a/core/embed/models/T3W1/boards/trezor_t3w1_revC.h
+++ b/core/embed/models/T3W1/boards/trezor_t3w1_revC.h
@@ -212,15 +212,28 @@
 #define SBU_2_PORT GPIOC
 #define SBU_2_CLK_ENA __HAL_RCC_GPIOC_CLK_ENABLE
 
-#define NRF_IN_RESERVED_PIN GPIO_PIN_7
-#define NRF_IN_RESERVED_PORT GPIOE
-#define NRF_IN_RESERVED_CLK_ENA __HAL_RCC_GPIOE_CLK_ENABLE
-#define NRF_OUT_RESET_PIN GPIO_PIN_0
-#define NRF_OUT_RESET_PORT GPIOG
-#define NRF_OUT_RESET_CLK_ENA __HAL_RCC_GPIOG_CLK_ENABLE
-#define NRF_OUT_STAY_IN_BLD_PIN GPIO_PIN_15
-#define NRF_OUT_STAY_IN_BLD_PORT GPIOE
-#define NRF_OUT_STAY_IN_BLD_CLK_ENA __HAL_RCC_GPIOE_CLK_ENABLE
+#define NRF_SPI_INSTANCE SPI1
+#define NRF_SPI_CLK_EN __HAL_RCC_SPI1_CLK_ENABLE
+#define NRF_SPI_CLK_DIS __HAL_RCC_SPI1_CLK_DISABLE
+#define NRF_SPI_FORCE_RESET __HAL_RCC_SPI1_FORCE_RESET
+#define NRF_SPI_RELEASE_RESET __HAL_RCC_SPI1_RELEASE_RESET
+#define NRF_SPI_PIN_AF GPIO_AF5_SPI1
+#define NRF_SPI_DMA_RX_REQUEST GPDMA1_REQUEST_SPI1_RX
+#define NRF_SPI_DMA_TX_REQUEST GPDMA1_REQUEST_SPI1_TX
+#define NRF_SPI_INTERRUPT_HANDLER SPI1_IRQHandler
+#define NRF_SPI_IRQN SPI1_IRQn
+#define NRF_SPI_SCK_PORT GPIOA
+#define NRF_SPI_SCK_PIN GPIO_PIN_1
+#define NRF_SPI_SCK_CLK_EN __HAL_RCC_GPIOA_CLK_ENABLE
+#define NRF_SPI_NSS_PORT GPIOA
+#define NRF_SPI_NSS_PIN GPIO_PIN_4
+#define NRF_SPI_NSS_CLK_EN __HAL_RCC_GPIOA_CLK_ENABLE
+#define NRF_SPI_MISO_PORT GPIOA
+#define NRF_SPI_MISO_PIN GPIO_PIN_6
+#define NRF_SPI_MISO_CLK_EN __HAL_RCC_GPIOA_CLK_ENABLE
+#define NRF_SPI_MOSI_PORT GPIOA
+#define NRF_SPI_MOSI_PIN GPIO_PIN_7
+#define NRF_SPI_MOSI_CLK_EN __HAL_RCC_GPIOA_CLK_ENABLE
 #define NRF_OUT_SPI_READY_PIN GPIO_PIN_13
 #define NRF_OUT_SPI_READY_PORT GPIOE
 #define NRF_OUT_SPI_READY_CLK_ENA __HAL_RCC_GPIOE_CLK_ENABLE
@@ -233,6 +246,37 @@
 #define NRF_EXTI_INTERRUPT_NUM EXTI11_IRQn
 #define NRF_EXTI_INTERRUPT_HANDLER EXTI11_IRQHandler
 
+#define NRF_IN_RESERVED_PIN GPIO_PIN_7
+#define NRF_IN_RESERVED_PORT GPIOE
+#define NRF_IN_RESERVED_CLK_ENA __HAL_RCC_GPIOE_CLK_ENABLE
+#define NRF_OUT_RESET_PIN GPIO_PIN_0
+#define NRF_OUT_RESET_PORT GPIOG
+#define NRF_OUT_RESET_CLK_ENA __HAL_RCC_GPIOG_CLK_ENABLE
+#define NRF_OUT_STAY_IN_BLD_PIN GPIO_PIN_15
+#define NRF_OUT_STAY_IN_BLD_PORT GPIOE
+#define NRF_OUT_STAY_IN_BLD_CLK_ENA __HAL_RCC_GPIOE_CLK_ENABLE
+
+#define NRF_UART_INSTANCE USART3
+#define NRF_UART_CLK_EN __HAL_RCC_USART3_CLK_ENABLE
+#define NRF_UART_CLK_DIS __HAL_RCC_USART3_CLK_DISABLE
+#define NRF_UART_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET
+#define NRF_UART_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET
+#define NRF_UART_INTERRUPT_HANDLER USART3_IRQHandler
+#define NRF_UART_IRQN USART3_IRQn
+#define NRF_UART_PIN_AF GPIO_AF7_USART3
+#define NRF_UART_TX_PORT GPIOB
+#define NRF_UART_TX_PIN GPIO_PIN_10
+#define NRF_UART_TX_CLK_EN __HAL_RCC_GPIOB_CLK_ENABLE
+#define NRF_UART_RX_PORT GPIOB
+#define NRF_UART_RX_PIN GPIO_PIN_1
+#define NRF_UART_RX_CLK_EN __HAL_RCC_GPIOB_CLK_ENABLE
+#define NRF_UART_RTS_PORT GPIOD
+#define NRF_UART_RTS_PIN GPIO_PIN_11
+#define NRF_UART_RTS_CLK_EN __HAL_RCC_GPIOD_CLK_ENABLE
+#define NRF_UART_CTS_PORT GPIOA
+#define NRF_UART_CTS_PIN GPIO_PIN_5
+#define NRF_UART_CTS_CLK_EN __HAL_RCC_GPIOA_CLK_ENABLE
+
 #define ST25R3916B
 #define NFC_SPI_INSTANCE SPI3
 #define NFC_SPI_PIN_AF GPIO_AF6_SPI3