refactor(core): use bitwise-AND for THP sync bit extraction
What the developer wrote
Authored by Roman Zeyde
refactor(core): use bitwise-AND for THP sync bit extraction
[no changelog]
What changed, and why it matters
This is a one-line code cleanup in the Trezor firmware's transport protocol code. It changes how a single sync bit is read from a byte, switching from a right-shift to a bitwise AND. The old and new code should behave identically when the byte only ever holds 0 or 0x80 in that bit position. The change is labeled a 'refactor' with '[no changelog]', so the project does not present it as a security fix. There is no direct evidence of an exploitable bug, but the change removes a subtle assumption that could matter if other bits in the byte were ever set.
Treat as a low-risk refactor. If auditing this area, verify that `cache.sync` is only ever assigned values 0x00 or 0x80 and that no other code paths set lower bits; if so, the change is behavior-preserving. No urgent action is warranted based on this commit alone.
Security signals we found
Single-line change in a protocol synchronization helper
Change is functionally equivalent for intended bit values
No changelog entry or security framing by the vendor
No references to an advisory, CVE, or external report supplied
Evidence from the diff
In core/src/trezor/wire/thp/alternating_bit_protocol.py, the expression bool(cache.sync >> 7) is replaced with bool(cache.sync & 0x80). Both extract the most-significant bit of cache.sync, but they differ when other bits are set: sync >> 7 always returns 0 or 1, while sync & 0x80 returns 0 or 0x80, which bool() still interprets correctly. The change is therefore functionally equivalent for any value where only bit 7 is relevant. The commit is tagged as a refactor and includes no changelog entry. No advisory, CVE, or researcher attribution is present in the supplied materials.
Changed components
core/src/trezor/wire/thp/alternating_bit_protocol.pyTrezor firmware THP (Trezor Host Protocol) alternating-bit protocol sync-bit checkInspect captured patch +1 / −1
diff --git a/core/src/trezor/wire/thp/alternating_bit_protocol.py b/core/src/trezor/wire/thp/alternating_bit_protocol.py
index 4e84b395..6bfa2013 100644
--- a/core/src/trezor/wire/thp/alternating_bit_protocol.py
+++ b/core/src/trezor/wire/thp/alternating_bit_protocol.py
@@ -37,7 +37,7 @@ def is_sending_allowed(cache: ChannelCache) -> bool:
Note: Sending a message in a channel before receipt of ACK message for the previously
sent message (in the channel) is prohibited, as it can lead to desynchronization.
"""
- return bool(cache.sync >> 7)
+ return bool(cache.sync & 0x80)
def get_send_seq_bit(cache: ChannelCache) -> int:
Why this scored 28/100
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