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hashes: Add optimized ARM SHA256d for 64-byte input
Public commit record
73/100 · Adequate
What the developer wrote
Authored by jrakibi
hashes: Add optimized ARM SHA256d for 64-byte input
Add the three transforms for sha256(sha256(64_bytes))
Transforms 1 & 2 compute the inner `sha256(64_bytes)`:
- Transform 1: 64 bytes already fill the first block (no
padding needed), so we apply 64 rounds of compression
normally.
After T1: state = state + initial_state
- Transform 2: the message schedule at this step is constant
and known in advance (64 bytes of padding), so
we precompute W[i]+K[i] into MIDS and apply 64 rounds (no
schedule expansion needed).
After T2: state = state + saved_T1_state
(state now contains sha256(64_bytes))
- Transform 3 computes sha256(output_of_T1_and_T2). The output
is 32 bytes, so the block contains 32 bytes and the rest is
known padding. we precompute the message
schedule for the known words (w8-w15) into FINS.
After T3: state = state + initial_state
(state now contains the sha256d result)
✓ Specific, descriptive subject✓ Names a concrete action or component✓ Provides detailed explanatory context
What changed, and why it matters
This commit adds a new, highly optimized way to compute a double SHA-256 hash on 64-byte inputs for 64-bit ARM processors (aarch64) using special CPU instructions. It is a pure performance improvement and does not change any public APIs or fix any known bug. There is no indication in the commit that it addresses a security vulnerability.
Recommended action
No security action required. Treat as a routine performance optimization. If reviewing for correctness, verify the precomputed MIDS/FINS/FINAL constants and the unrolled schedule updates against the SHA-256 specification and compare output against the existing software or x86_64 implementations via tests.
Security signals we found
01
New unsafe ARM SHA-256 hardware-accelerated code path added
02
Function is gated by target_arch = 'aarch64' and target_feature(enable = 'sha2')
03
No security relevance claimed by commit message or diff
04
No changes to input validation, memory allocation, or public interfaces
Evidence from the diff
The patch introduces sha256d_64_arm(), an unrolled, hardware-accelerated implementation of SHA-256d for exactly 64-byte messages on aarch64 when the sha2 target feature is available. It uses ARM NEON/v8 cryptographic intrinsics (vsha256hq_u32, vsha256h2q_u32, vsha256su0q_u32, vsha256su1q_u32) and precomputed padding constants (MIDS, FINS, FINAL) to fuse the inner SHA-256 compression, its padding block, and the outer SHA-256 compression. The function is unsafe, target-feature-gated, and private to the module. No callers are added in this diff, and no existing logic is modified.
Changed components
hashes/src/sha256/crypto.rsInspect captured patch +497 / −0
diff --git a/hashes/src/sha256/crypto.rs b/hashes/src/sha256/crypto.rs
index 65458adb..262c5df5 100644
--- a/hashes/src/sha256/crypto.rs
+++ b/hashes/src/sha256/crypto.rs
@@ -21,6 +21,8 @@ use core::arch::x86_64::{__m128i, _mm_set_epi64x, _mm_loadu_si128, _mm_shuffle_e
use internals::slice::SliceExt;
+use crate::sha256d;
+
use super::{HashEngine, Midstate, BLOCK_SIZE};
#[cfg(all(feature = "cpufeatures", target_arch = "aarch64"))]
@@ -780,6 +782,501 @@ impl HashEngine {
vst1q_u32(state.as_mut_ptr().add(4), state1);
}
+ #[cfg(all(target_arch = "aarch64", any(feature = "std", feature = "cpufeatures")))]
+ #[target_feature(enable = "sha2")]
+ unsafe fn sha256d_64_arm(output: &mut [u8; 32], input: &[u8; 64]) {
+ use core::arch::aarch64::vst1q_u8;
+
+ // initial state
+ const INIT: [u32; 8] = [
+ 0x6a09e667, 0xbb67ae85, 0x3c6ef372, 0xa54ff53a,
+ 0x510e527f, 0x9b05688c, 0x1f83d9ab, 0x5be0cd19
+ ];
+
+ // SHA256 round constants
+ #[rustfmt::skip]
+ const K: [u32; 64] = [
+ 0x428A2F98, 0x71374491, 0xB5C0FBCF, 0xE9B5DBA5,
+ 0x3956C25B, 0x59F111F1, 0x923F82A4, 0xAB1C5ED5,
+ 0xD807AA98, 0x12835B01, 0x243185BE, 0x550C7DC3,
+ 0x72BE5D74, 0x80DEB1FE, 0x9BDC06A7, 0xC19BF174,
+ 0xE49B69C1, 0xEFBE4786, 0x0FC19DC6, 0x240CA1CC,
+ 0x2DE92C6F, 0x4A7484AA, 0x5CB0A9DC, 0x76F988DA,
+ 0x983E5152, 0xA831C66D, 0xB00327C8, 0xBF597FC7,
+ 0xC6E00BF3, 0xD5A79147, 0x06CA6351, 0x14292967,
+ 0x27B70A85, 0x2E1B2138, 0x4D2C6DFC, 0x53380D13,
+ 0x650A7354, 0x766A0ABB, 0x81C2C92E, 0x92722C85,
+ 0xA2BFE8A1, 0xA81A664B, 0xC24B8B70, 0xC76C51A3,
+ 0xD192E819, 0xD6990624, 0xF40E3585, 0x106AA070,
+ 0x19A4C116, 0x1E376C08, 0x2748774C, 0x34B0BCB5,
+ 0x391C0CB3, 0x4ED8AA4A, 0x5B9CCA4F, 0x682E6FF3,
+ 0x748F82EE, 0x78A5636F, 0x84C87814, 0x8CC70208,
+ 0x90BEFFFA, 0xA4506CEB, 0xBEF9A3F7, 0xC67178F2,
+ ];
+
+ // Precomputed W[i] + K[i] for the 2nd transform (padding block).
+ const MIDS: [u32; 64] = [
+ 0xc28a2f98, 0x71374491, 0xb5c0fbcf, 0xe9b5dba5,
+ 0x3956c25b, 0x59f111f1, 0x923f82a4, 0xab1c5ed5,
+ 0xd807aa98, 0x12835b01, 0x243185be, 0x550c7dc3,
+ 0x72be5d74, 0x80deb1fe, 0x9bdc06a7, 0xc19bf374,
+ 0x649b69c1, 0xf0fe4786, 0x0fe1edc6, 0x240cf254,
+ 0x4fe9346f, 0x6cc984be, 0x61b9411e, 0x16f988fa,
+ 0xf2c65152, 0xa88e5a6d, 0xb019fc65, 0xb9d99ec7,
+ 0x9a1231c3, 0xe70eeaa0, 0xfdb1232b, 0xc7353eb0,
+ 0x3069bad5, 0xcb976d5f, 0x5a0f118f, 0xdc1eeefd,
+ 0x0a35b689, 0xde0b7a04, 0x58f4ca9d, 0xe15d5b16,
+ 0x007f3e86, 0x37088980, 0xa507ea32, 0x6fab9537,
+ 0x17406110, 0x0d8cd6f1, 0xcdaa3b6d, 0xc0bbbe37,
+ 0x83613bda, 0xdb48a363, 0x0b02e931, 0x6fd15ca7,
+ 0x521afaca, 0x31338431, 0x6ed41a95, 0x6d437890,
+ 0xc39c91f2, 0x9eccabbd, 0xb5c9a0e6, 0x532fb63c,
+ 0xd2c741c6, 0x07237ea3, 0xa4954b68, 0x4c191d76
+ ];
+
+ // Precomputed values for Transform 3 rounds 9-16.
+ // FINS[0..3]: msg2 + K[8..11]
+ // FINS[4..7]: vsha256su0q_u32(msg2, msg3)
+ // FINS[8..11]: msg2 + K[12..15]
+ #[rustfmt::skip]
+ const FINS: [u32; 12] = [
+ 0x5807aa98, 0x12835b01, 0x243185be, 0x550c7dc3,
+ 0x80000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x72be5d74, 0x80deb1fe, 0x9bdc06a7, 0xc19bf274,
+ ];
+
+ // Padding processed in the 3rd transform (byteswapped).
+ const FINAL: [u32; 8] = [
+ 0x80000000, 0, 0, 0, 0, 0, 0, 0x100,
+ ];
+
+ let (mut state0, mut state1);
+ let (abcd_save, efgh_save);
+
+ let (mut msg0, mut msg1, mut msg2, mut msg3);
+ let (mut tmp0, mut tmp2, mut tmp);
+
+ // Load state
+ state0 = vld1q_u32(INIT.as_ptr().add(0));
+ state1 = vld1q_u32(INIT.as_ptr().add(4));
+
+ // Load message
+ msg0 = vld1q_u32(input.as_ptr().add(0).cast::<u32>());
+ msg1 = vld1q_u32(input.as_ptr().add(16).cast::<u32>());
+ msg2 = vld1q_u32(input.as_ptr().add(32).cast::<u32>());
+ msg3 = vld1q_u32(input.as_ptr().add(48).cast::<u32>());
+
+ // Reverse for little endian
+ msg0 = vreinterpretq_u32_u8(vrev32q_u8(vreinterpretq_u8_u32(msg0)));
+ msg1 = vreinterpretq_u32_u8(vrev32q_u8(vreinterpretq_u8_u32(msg1)));
+ msg2 = vreinterpretq_u32_u8(vrev32q_u8(vreinterpretq_u8_u32(msg2)));
+ msg3 = vreinterpretq_u32_u8(vrev32q_u8(vreinterpretq_u8_u32(msg3)));
+
+ // Transform 1: Rounds 1-4
+ tmp = vld1q_u32(K.as_ptr().add(0));
+ tmp0 = vaddq_u32(msg0, tmp);
+ tmp2 = state0;
+ msg0 = vsha256su0q_u32(msg0, msg1);
+ state0 = vsha256hq_u32(state0, state1, tmp0);
+ state1 = vsha256h2q_u32(state1, tmp2, tmp0);
+ msg0 = vsha256su1q_u32(msg0, msg2, msg3);
+
+ // Transform 1: Rounds 5-8
+ tmp = vld1q_u32(K.as_ptr().add(4));
+ tmp0 = vaddq_u32(msg1, tmp);
+ tmp2 = state0;
+ msg1 = vsha256su0q_u32(msg1, msg2);
+ state0 = vsha256hq_u32(state0, state1, tmp0);
+ state1 = vsha256h2q_u32(state1, tmp2, tmp0);
+ msg1 = vsha256su1q_u32(msg1, msg3, msg0);
+
+ // Transform 1: Rounds 9-12
+ tmp = vld1q_u32(K.as_ptr().add(8));
+ tmp0 = vaddq_u32(msg2, tmp);
+ tmp2 = state0;
+ msg2 = vsha256su0q_u32(msg2, msg3);
+ state0 = vsha256hq_u32(state0, state1, tmp0);
+ state1 = vsha256h2q_u32(state1, tmp2, tmp0);
+ msg2 = vsha256su1q_u32(msg2, msg0, msg1);
+
+ // Transform 1: Rounds 13-16
+ tmp = vld1q_u32(K.as_ptr().add(12));
+ tmp0 = vaddq_u32(msg3, tmp);
+ tmp2 = state0;
+ msg3 = vsha256su0q_u32(msg3, msg0);
+ state0 = vsha256hq_u32(state0, state1, tmp0);
+ state1 = vsha256h2q_u32(state1, tmp2, tmp0);
+ msg3 = vsha256su1q_u32(msg3, msg1, msg2);
+
+ // Transform 1: Rounds 17-20
+ tmp = vld1q_u32(K.as_ptr().add(16));
+ tmp0 = vaddq_u32(msg0, tmp);
+ tmp2 = state0;
+ msg0 = vsha256su0q_u32(msg0, msg1);
+ state0 = vsha256hq_u32(state0, state1, tmp0);
+ state1 = vsha256h2q_u32(state1, tmp2, tmp0);
+ msg0 = vsha256su1q_u32(msg0, msg2, msg3);
+
+ // Transform 1: Rounds 21-24
+ tmp = vld1q_u32(K.as_ptr().add(20));
+ tmp0 = vaddq_u32(msg1, tmp);
+ tmp2 = state0;
+ msg1 = vsha256su0q_u32(msg1, msg2);
+ state0 = vsha256hq_u32(state0, state1, tmp0);
+ state1 = vsha256h2q_u32(state1, tmp2, tmp0);
+ msg1 = vsha256su1q_u32(msg1, msg3, msg0);
+
+ // Transform 1: Rounds 25-28
+ tmp = vld1q_u32(K.as_ptr().add(24));
+ tmp0 = vaddq_u32(msg2, tmp);
+ tmp2 = state0;
+ msg2 = vsha256su0q_u32(msg2, msg3);
+ state0 = vsha256hq_u32(state0, state1, tmp0);
+ state1 = vsha256h2q_u32(state1, tmp2, tmp0);
+ msg2 = vsha256su1q_u32(msg2, msg0, msg1);
+
+ // Transform 1: Rounds 29-32
+ tmp = vld1q_u32(K.as_ptr().add(28));
+ tmp0 = vaddq_u32(msg3, tmp);
+ tmp2 = state0;
+ msg3 = vsha256su0q_u32(msg3, msg0);
+ state0 = vsha256hq_u32(state0, state1, tmp0);
+ state1 = vsha256h2q_u32(state1, tmp2, tmp0);
+ msg3 = vsha256su1q_u32(msg3, msg1, msg2);
+
+ // Transform 1: Rounds 33-36
+ tmp = vld1q_u32(K.as_ptr().add(32));
+ tmp0 = vaddq_u32(msg0, tmp);
+ tmp2 = state0;
+ msg0 = vsha256su0q_u32(msg0, msg1);
+ state0 = vsha256hq_u32(state0, state1, tmp0);
+ state1 = vsha256h2q_u32(state1, tmp2, tmp0);
+ msg0 = vsha256su1q_u32(msg0, msg2, msg3);
+
+ // Transform 1: Rounds 37-40
+ tmp = vld1q_u32(K.as_ptr().add(36));
+ tmp0 = vaddq_u32(msg1, tmp);
+ tmp2 = state0;
+ msg1 = vsha256su0q_u32(msg1, msg2);
+ state0 = vsha256hq_u32(state0, state1, tmp0);
+ state1 = vsha256h2q_u32(state1, tmp2, tmp0);
+ msg1 = vsha256su1q_u32(msg1, msg3, msg0);
+
+ // Transform 1: Rounds 41-44
+ tmp = vld1q_u32(K.as_ptr().add(40));
+ tmp0 = vaddq_u32(msg2, tmp);
+ tmp2 = state0;
+ msg2 = vsha256su0q_u32(msg2, msg3);
+ state0 = vsha256hq_u32(state0, state1, tmp0);
+ state1 = vsha256h2q_u32(state1, tmp2, tmp0);
+ msg2 = vsha256su1q_u32(msg2, msg0, msg1);
+
+ // Transform 1: Rounds 45-48
+ tmp = vld1q_u32(K.as_ptr().add(44));
+ tmp0 = vaddq_u32(msg3, tmp);
+ tmp2 = state0;
+ msg3 = vsha256su0q_u32(msg3, msg0);
+ state0 = vsha256hq_u32(state0, state1, tmp0);
+ state1 = vsha256h2q_u32(state1, tmp2, tmp0);
+ msg3 = vsha256su1q_u32(msg3, msg1, msg2);
+
+ // Transform 1: Rounds 49-52
+ tmp = vld1q_u32(K.as_ptr().add(48));
+ tmp0 = vaddq_u32(msg0, tmp);
+ tmp2 = state0;
+ state0 = vsha256hq_u32(state0, state1, tmp0);
+ state1 = vsha256h2q_u32(state1, tmp2, tmp0);
+
+ // Transform 1: Rounds 53-56
+ tmp = vld1q_u32(K.as_ptr().add(52));
+ tmp0 = vaddq_u32(msg1, tmp);
+ tmp2 = state0;
+ state0 = vsha256hq_u32(state0, state1, tmp0);
+ state1 = vsha256h2q_u32(state1, tmp2, tmp0);
+
+ // Transform 1: Rounds 57-60
+ tmp = vld1q_u32(K.as_ptr().add(56));
+ tmp0 = vaddq_u32(msg2, tmp);
+ tmp2 = state0;
+ state0 = vsha256hq_u32(state0, state1, tmp0);
+ state1 = vsha256h2q_u32(state1, tmp2, tmp0);
+
+ // Transform 1: Rounds 61-64
+ tmp = vld1q_u32(K.as_ptr().add(60));
+ tmp0 = vaddq_u32(msg3, tmp);
+ tmp2 = state0;
+ state0 = vsha256hq_u32(state0, state1, tmp0);
+ state1 = vsha256h2q_u32(state1, tmp2, tmp0);
+
+ // Transform 1: Update state
+ tmp = vld1q_u32(&INIT[0]);
+ state0 = vaddq_u32(state0, tmp);
+ tmp = vld1q_u32(&INIT[4]);
+ state1 = vaddq_u32(state1, tmp);
+
+ // ------------------ Transform 2 -------------------
+
+ // Transform 2: Save state
+ abcd_save = state0;
+ efgh_save = state1;
+
+ // Transform 2: Rounds 1-4
+ tmp = vld1q_u32(MIDS.as_ptr().add(0));
+ tmp2 = state0;
+ state0 = vsha256hq_u32(state0, state1, tmp);
+ state1 = vsha256h2q_u32(state1, tmp2, tmp);
+
+ // Transform 2: Rounds 5-8
+ tmp = vld1q_u32(MIDS.as_ptr().add(4));
+ tmp2 = state0;
+ state0 = vsha256hq_u32(state0, state1, tmp);
+ state1 = vsha256h2q_u32(state1, tmp2, tmp);
+
+ // Transform 2: Rounds 9-12
+ tmp = vld1q_u32(MIDS.as_ptr().add(8));
+ tmp2 = state0;
+ state0 = vsha256hq_u32(state0, state1, tmp);
+ state1 = vsha256h2q_u32(state1, tmp2, tmp);
+
+ // Transform 2: Rounds 13-16
+ tmp = vld1q_u32(MIDS.as_ptr().add(12));
+ tmp2 = state0;
+ state0 = vsha256hq_u32(state0, state1, tmp);
+ state1 = vsha256h2q_u32(state1, tmp2, tmp);
+
+ // Transform 2: Rounds 17-20
+ tmp = vld1q_u32(MIDS.as_ptr().add(16));
+ tmp2 = state0;
+ state0 = vsha256hq_u32(state0, state1, tmp);
+ state1 = vsha256h2q_u32(state1, tmp2, tmp);
+
+ // Transform 2: Rounds 21-24
+ tmp = vld1q_u32(MIDS.as_ptr().add(20));
+ tmp2 = state0;
+ state0 = vsha256hq_u32(state0, state1, tmp);
+ state1 = vsha256h2q_u32(state1, tmp2, tmp);
+
+ // Transform 2: Rounds 25-28
+ tmp = vld1q_u32(MIDS.as_ptr().add(24));
+ tmp2 = state0;
+ state0 = vsha256hq_u32(state0, state1, tmp);
+ state1 = vsha256h2q_u32(state1, tmp2, tmp);
+
+ // Transform 2: Rounds 29-32
+ tmp = vld1q_u32(MIDS.as_ptr().add(28));
+ tmp2 = state0;
+ state0 = vsha256hq_u32(state0, state1, tmp);
+ state1 = vsha256h2q_u32(state1, tmp2, tmp);
+
+ // Transform 2: Rounds 33-36
+ tmp = vld1q_u32(MIDS.as_ptr().add(32));
+ tmp2 = state0;
+ state0 = vsha256hq_u32(state0, state1, tmp);
+ state1 = vsha256h2q_u32(state1, tmp2, tmp);
+
+ // Transform 2: Rounds 37-40
+ tmp = vld1q_u32(MIDS.as_ptr().add(36));
+ tmp2 = state0;
+ state0 = vsha256hq_u32(state0, state1, tmp);
+ state1 = vsha256h2q_u32(state1, tmp2, tmp);
+
+ // Transform 2: Rounds 41-44
+ tmp = vld1q_u32(MIDS.as_ptr().add(40));
+ tmp2 = state0;
+ state0 = vsha256hq_u32(state0, state1, tmp);
+ state1 = vsha256h2q_u32(state1, tmp2, tmp);
+
+ // Transform 2: Rounds 45-48
+ tmp = vld1q_u32(MIDS.as_ptr().add(44));
+ tmp2 = state0;
+ state0 = vsha256hq_u32(state0, state1, tmp);
+ state1 = vsha256h2q_u32(state1, tmp2, tmp);
+
+ // Transform 2: Rounds 49-52
+ tmp = vld1q_u32(MIDS.as_ptr().add(48));
+ tmp2 = state0;
+ state0 = vsha256hq_u32(state0, state1, tmp);
+ state1 = vsha256h2q_u32(state1, tmp2, tmp);
+
+ // Transform 2: Rounds 53-56
+ tmp = vld1q_u32(MIDS.as_ptr().add(52));
+ tmp2 = state0;
+ state0 = vsha256hq_u32(state0, state1, tmp);
+ state1 = vsha256h2q_u32(state1, tmp2, tmp);
+
+ // Transform 2: Rounds 57-60
+ tmp = vld1q_u32(MIDS.as_ptr().add(56));
+ tmp2 = state0;
+ state0 = vsha256hq_u32(state0, state1, tmp);
+ state1 = vsha256h2q_u32(state1, tmp2, tmp);
+
+ // Transform 2: Rounds 61-64
+ tmp = vld1q_u32(MIDS.as_ptr().add(60));
+ tmp2 = state0;
+ state0 = vsha256hq_u32(state0, state1, tmp);
+ state1 = vsha256h2q_u32(state1, tmp2, tmp);
+
+ // Transform 2: Update state
+ state0 = vaddq_u32(state0, abcd_save);
+ state1 = vaddq_u32(state1, efgh_save);
+
+ // ------------------ Transform 3 -------------------
+
+ msg0 = state0;
+ msg1 = state1;
+ msg2 = vld1q_u32(FINAL.as_ptr().add(0));
+ msg3 = vld1q_u32(FINAL.as_ptr().add(4));
+
+ // Transform 3: Load state
+ state0 = vld1q_u32(INIT.as_ptr());
+ state1 = vld1q_u32(INIT.as_ptr().add(4));
+
+ // Transform 3: Rounds 1-4
+ tmp = vld1q_u32(K.as_ptr().add(0));
+ tmp0 = vaddq_u32(msg0, tmp);
+ tmp2 = state0;
+ msg0 = vsha256su0q_u32(msg0, msg1);
+ state0 = vsha256hq_u32(state0, state1, tmp0);
+ state1 = vsha256h2q_u32(state1, tmp2, tmp0);
+ msg0 = vsha256su1q_u32(msg0, msg2, msg3);
+
+ // Transform 3: Rounds 5-8
+ tmp = vld1q_u32(K.as_ptr().add(4));
+ tmp0 = vaddq_u32(msg1, tmp);
+ tmp2 = state0;
+ msg1 = vsha256su0q_u32(msg1, msg2);
+ state0 = vsha256hq_u32(state0, state1, tmp0);
+ state1 = vsha256h2q_u32(state1, tmp2, tmp0);
+ msg1 = vsha256su1q_u32(msg1, msg3, msg0);
+
+ // Transform 3: Rounds 9-12
+ tmp = vld1q_u32(FINS.as_ptr().add(0));
+ tmp2 = state0;
+ msg2 = vld1q_u32(FINS.as_ptr().add(4));
+ state0 = vsha256hq_u32(state0, state1, tmp);
+ state1 = vsha256h2q_u32(state1, tmp2, tmp);
+ msg2 = vsha256su1q_u32(msg2, msg0, msg1);
+
+ // Transform 3: Rounds 13-16
+ tmp = vld1q_u32(FINS.as_ptr().add(8));
+ tmp2 = state0;
+ msg3 = vsha256su0q_u32(msg3, msg0);
+ state0 = vsha256hq_u32(state0, state1, tmp);
+ state1 = vsha256h2q_u32(state1, tmp2, tmp);
+ msg3 = vsha256su1q_u32(msg3, msg1, msg2);
+
+ // Transform 3: Rounds 17-20
+ tmp = vld1q_u32(K.as_ptr().add(16));
+ tmp0 = vaddq_u32(msg0, tmp);
+ tmp2 = state0;
+ msg0 = vsha256su0q_u32(msg0, msg1);
+ state0 = vsha256hq_u32(state0, state1, tmp0);
+ state1 = vsha256h2q_u32(state1, tmp2, tmp0);
+ msg0 = vsha256su1q_u32(msg0, msg2, msg3);
+
+ // Transform 3: Rounds 21-24
+ tmp = vld1q_u32(K.as_ptr().add(20));
+ tmp0 = vaddq_u32(msg1, tmp);
+ tmp2 = state0;
+ msg1 = vsha256su0q_u32(msg1, msg2);
+ state0 = vsha256hq_u32(state0, state1, tmp0);
+ state1 = vsha256h2q_u32(state1, tmp2, tmp0);
+ msg1 = vsha256su1q_u32(msg1, msg3, msg0);
+
+ // Transform 3: Rounds 25-28
+ tmp = vld1q_u32(K.as_ptr().add(24));
+ tmp0 = vaddq_u32(msg2, tmp);
+ tmp2 = state0;
+ msg2 = vsha256su0q_u32(msg2, msg3);
+ state0 = vsha256hq_u32(state0, state1, tmp0);
+ state1 = vsha256h2q_u32(state1, tmp2, tmp0);
+ msg2 = vsha256su1q_u32(msg2, msg0, msg1);
+
+ // Transform 3: Rounds 29-32
+ tmp = vld1q_u32(K.as_ptr().add(28));
+ tmp0 = vaddq_u32(msg3, tmp);
+ tmp2 = state0;
+ msg3 = vsha256su0q_u32(msg3, msg0);
+ state0 = vsha256hq_u32(state0, state1, tmp0);
+ state1 = vsha256h2q_u32(state1, tmp2, tmp0);
+ msg3 = vsha256su1q_u32(msg3, msg1, msg2);
+
+ // Transform 3: Rounds 33-36
+ tmp = vld1q_u32(K.as_ptr().add(32));
+ tmp0 = vaddq_u32(msg0, tmp);
+ tmp2 = state0;
+ msg0 = vsha256su0q_u32(msg0, msg1);
+ state0 = vsha256hq_u32(state0, state1, tmp0);
+ state1 = vsha256h2q_u32(state1, tmp2, tmp0);
+ msg0 = vsha256su1q_u32(msg0, msg2, msg3);
+
+ // Transform 3: Rounds 37-40
+ tmp = vld1q_u32(K.as_ptr().add(36));
+ tmp0 = vaddq_u32(msg1, tmp);
+ tmp2 = state0;
+ msg1 = vsha256su0q_u32(msg1, msg2);
+ state0 = vsha256hq_u32(state0, state1, tmp0);
+ state1 = vsha256h2q_u32(state1, tmp2, tmp0);
+ msg1 = vsha256su1q_u32(msg1, msg3, msg0);
+
+ // Transform 3: Rounds 41-44
+ tmp = vld1q_u32(K.as_ptr().add(40));
+ tmp0 = vaddq_u32(msg2, tmp);
+ tmp2 = state0;
+ msg2 = vsha256su0q_u32(msg2, msg3);
+ state0 = vsha256hq_u32(state0, state1, tmp0);
+ state1 = vsha256h2q_u32(state1, tmp2, tmp0);
+ msg2 = vsha256su1q_u32(msg2, msg0, msg1);
+
+ // Transform 3: Rounds 45-48
+ tmp = vld1q_u32(K.as_ptr().add(44));
+ tmp0 = vaddq_u32(msg3, tmp);
+ tmp2 = state0;
+ msg3 = vsha256su0q_u32(msg3, msg0);
+ state0 = vsha256hq_u32(state0, state1, tmp0);
+ state1 = vsha256h2q_u32(state1, tmp2, tmp0);
+ msg3 = vsha256su1q_u32(msg3, msg1, msg2);
+
+ // Transform 3: Rounds 49-52
+ tmp = vld1q_u32(K.as_ptr().add(48));
+ tmp0 = vaddq_u32(msg0, tmp);
+ tmp2 = state0;
+ state0 = vsha256hq_u32(state0, state1, tmp0);
+ state1 = vsha256h2q_u32(state1, tmp2, tmp0);
+
+ // Transform 3: Rounds 53-56
+ tmp = vld1q_u32(K.as_ptr().add(52));
+ tmp0 = vaddq_u32(msg1, tmp);
+ tmp2 = state0;
+ state0 = vsha256hq_u32(state0, state1, tmp0);
+ state1 = vsha256h2q_u32(state1, tmp2, tmp0);
+
+ // Transform 3: Rounds 57-60
+ tmp = vld1q_u32(K.as_ptr().add(56));
+ tmp0 = vaddq_u32(msg2, tmp);
+ tmp2 = state0;
+ state0 = vsha256hq_u32(state0, state1, tmp0);
+ state1 = vsha256h2q_u32(state1, tmp2, tmp0);
+
+ // Transform 3: Rounds 61-64
+ tmp = vld1q_u32(K.as_ptr().add(60));
+ tmp0 = vaddq_u32(msg3, tmp);
+ tmp2 = state0;
+ state0 = vsha256hq_u32(state0, state1, tmp0);
+ state1 = vsha256h2q_u32(state1, tmp2, tmp0);
+
+ // Transform 3: Update state
+ tmp = vld1q_u32(INIT.as_ptr().add(0));
+ state0 = vaddq_u32(state0, tmp);
+ tmp = vld1q_u32(INIT.as_ptr().add(4));
+ state1 = vaddq_u32(state1, tmp);
+
+ // Store result
+ vst1q_u8(output.as_mut_ptr().add(0), vrev32q_u8(vreinterpretq_u8_u32(state0)));
+ vst1q_u8(output.as_mut_ptr().add(16), vrev32q_u8(vreinterpretq_u8_u32(state1)));
+ }
+
+
// Algorithm copied from libsecp256k1
fn software_process_block(state: &mut[u32; 8], blocks: &[u8]) {
debug_assert!(!blocks.is_empty() && blocks.len() % BLOCK_SIZE == 0);
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