Merge branch 'nickez/vendor-stm32-rust-crate'

### external/vendor/cortex-m-rt-macros/.cargo-checksum.json
@@ -0,0 +1 @@
+{"files":{".cargo_vcs_info.json":"943b2029f65262df94b03cba0c1efe99c174d3f3790b7e3c2afcdae407ac2862","Cargo.toml":"fe4fb8327a7c921e9de94726700ebf6d1a3f24dd393a8d76d98be756f543f876","Cargo.toml.orig":"8ec2f680cbb2919285e0043c6d0faf058a5729f10e25885eb1e1301af847160b","src/lib.rs":"e573325bc4b83dc7624a25d796f207692d8b94394d37adf8fdf84cd58036d8b5"},"package":"e37549a379a9e0e6e576fd208ee60394ccb8be963889eebba3ffe0980364f472"}
\ No newline at end of file

### external/vendor/cortex-m-rt-macros/.cargo_vcs_info.json
@@ -0,0 +1,6 @@
+{
+  "git": {
+    "sha1": "91772718fec2e07b0ccabeb019e509a53d3eecda"
+  },
+  "path_in_vcs": "cortex-m-rt/macros"
+}
\ No newline at end of file

### external/vendor/cortex-m-rt-macros/Cargo.toml
@@ -0,0 +1,55 @@
+# THIS FILE IS AUTOMATICALLY GENERATED BY CARGO
+#
+# When uploading crates to the registry Cargo will automatically
+# "normalize" Cargo.toml files for maximal compatibility
+# with all versions of Cargo and also rewrite `path` dependencies
+# to registry (e.g., crates.io) dependencies.
+#
+# If you are reading this file be aware that the original Cargo.toml
+# will likely look very different (and much more reasonable).
+# See Cargo.toml.orig for the original contents.
+
+[package]
+edition = "2021"
+rust-version = "1.61"
+name = "cortex-m-rt-macros"
+version = "0.7.5"
+authors = ["Jorge Aparicio <jorge@japaric.io>"]
+build = false
+autobins = false
+autoexamples = false
+autotests = false
+autobenches = false
+description = "Attributes re-exported in `cortex-m-rt`"
+documentation = "https://docs.rs/cortex-m-rt"
+readme = false
+keywords = [
+    "arm",
+    "cortex-m",
+    "runtime",
+    "startup",
+]
+categories = [
+    "embedded",
+    "no-std",
+]
+license = "MIT OR Apache-2.0"
+repository = "https://github.com/rust-embedded/cortex-m"
+
+[lib]
+name = "cortex_m_rt_macros"
+path = "src/lib.rs"
+proc-macro = true
+
+[dependencies.proc-macro2]
+version = "1.0"
+
+[dependencies.quote]
+version = "1.0"
+
+[dependencies.syn]
+version = "2.0"
+features = [
+    "extra-traits",
+    "full",
+]

### external/vendor/cortex-m-rt-macros/Cargo.toml.orig
@@ -0,0 +1,23 @@
+[package]
+authors = ["Jorge Aparicio <jorge@japaric.io>"]
+categories = ["embedded", "no-std"]
+description = "Attributes re-exported in `cortex-m-rt`"
+documentation = "https://docs.rs/cortex-m-rt"
+keywords = ["arm", "cortex-m", "runtime", "startup"]
+license = "MIT OR Apache-2.0"
+name = "cortex-m-rt-macros"
+repository = "https://github.com/rust-embedded/cortex-m"
+version = "0.7.5"
+edition = "2021"
+rust-version = "1.61"
+
+[lib]
+proc-macro = true
+
+[dependencies]
+quote = "1.0"
+proc-macro2 = "1.0"
+
+[dependencies.syn]
+features = ["extra-traits", "full"]
+version = "2.0"

### external/vendor/cortex-m-rt-macros/src/lib.rs
@@ -0,0 +1,788 @@
+//! Internal implementation details of `cortex-m-rt`.
+//!
+//! Do not use this crate directly.
+
+extern crate proc_macro;
+
+use proc_macro::TokenStream;
+use proc_macro2::Span;
+use quote::quote;
+use std::iter;
+use std::{collections::HashSet, fmt::Display};
+use syn::{
+    parse::{self, Parse},
+    parse_macro_input,
+    spanned::Spanned,
+    AttrStyle, Attribute, FnArg, Ident, Item, ItemFn, ItemStatic, ReturnType, Stmt, Type,
+    Visibility,
+};
+
+#[proc_macro_attribute]
+pub fn entry(args: TokenStream, input: TokenStream) -> TokenStream {
+    let mut f = parse_macro_input!(input as ItemFn);
+
+    // check the function signature
+    let valid_signature = f.sig.constness.is_none()
+        && f.vis == Visibility::Inherited
+        && f.sig.abi.is_none()
+        && f.sig.inputs.is_empty()
+        && f.sig.generics.params.is_empty()
+        && f.sig.generics.where_clause.is_none()
+        && f.sig.variadic.is_none()
+        && match f.sig.output {
+            ReturnType::Default => false,
+            ReturnType::Type(_, ref ty) => matches!(**ty, Type::Never(_)),
+        };
+
+    if !valid_signature {
+        return parse::Error::new(
+            f.span(),
+            "`#[entry]` function must have signature `[unsafe] fn() -> !`",
+        )
+        .to_compile_error()
+        .into();
+    }
+
+    if !args.is_empty() {
+        return parse::Error::new(Span::call_site(), "This attribute accepts no arguments")
+            .to_compile_error()
+            .into();
+    }
+
+    // XXX should we blacklist other attributes?
+    let (statics, stmts) = match extract_static_muts(f.block.stmts) {
+        Err(e) => return e.to_compile_error().into(),
+        Ok(x) => x,
+    };
+
+    f.sig.ident = Ident::new(&format!("__cortex_m_rt_{}", f.sig.ident), Span::call_site());
+    f.sig.inputs.extend(statics.iter().map(|statik| {
+        let ident = &statik.ident;
+        let ty = &statik.ty;
+        let attrs = &statik.attrs;
+
+        // Note that we use an explicit `'static` lifetime for the entry point arguments. This makes
+        // it more flexible, and is sound here, since the entry will not be called again, ever.
+        syn::parse::<FnArg>(
+            quote!(#[allow(non_snake_case)] #(#attrs)* #ident: &'static mut #ty).into(),
+        )
+        .unwrap()
+    }));
+    f.block.stmts = stmts;
+
+    let tramp_ident = Ident::new(&format!("{}_trampoline", f.sig.ident), Span::call_site());
+    let ident = &f.sig.ident;
+
+    let resource_args = statics
+        .iter()
+        .map(|statik| {
+            let (ref cfgs, ref attrs) = extract_cfgs(statik.attrs.clone());
+            let ident = &statik.ident;
+            let ty = &statik.ty;
+            let expr = &statik.expr;
+            quote! {
+                #(#cfgs)*
+                {
+                    #(#attrs)*
+                    static mut #ident: #ty = #expr;
+                    unsafe { &mut #ident }
+                }
+            }
+        })
+        .collect::<Vec<_>>();
+
+    if let Err(error) = check_attr_whitelist(&f.attrs, WhiteListCaller::Entry) {
+        return error;
+    }
+
+    let (ref cfgs, ref attrs) = extract_cfgs(f.attrs.clone());
+
+    quote!(
+        #(#cfgs)*
+        #(#attrs)*
+        #[doc(hidden)]
+        #[export_name = "main"]
+        pub unsafe extern "C" fn #tramp_ident() {
+            #[allow(static_mut_refs)]
+            #ident(
+                #(#resource_args),*
+            )
+        }
+
+        #f
+    )
+    .into()
+}
+
+#[derive(Debug, PartialEq)]
+enum Exception {
+    DefaultHandler,
+    HardFault(HardFaultArgs),
+    NonMaskableInt,
+    Other,
+}
+
+impl Display for Exception {
+    fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result {
+        match self {
+            Exception::DefaultHandler => write!(f, "`DefaultHandler`"),
+            Exception::HardFault(_) => write!(f, "`HardFault` handler"),
+            Exception::NonMaskableInt => write!(f, "`NonMaskableInt` handler"),
+            Exception::Other => write!(f, "Other exception handler"),
+        }
+    }
+}
+
+#[derive(Debug, PartialEq)]
+struct HardFaultArgs {
+    trampoline: bool,
+}
+
+impl Default for HardFaultArgs {
+    fn default() -> Self {
+        Self { trampoline: true }
+    }
+}
+
+impl Parse for HardFaultArgs {
+    fn parse(input: parse::ParseStream) -> syn::Result<Self> {
+        let mut items = Vec::new();
+        // Read a list of `ident = value,`
+        loop {
+            if input.is_empty() {
+                break;
+            }
+
+            let name = input.parse::<Ident>()?;
+            input.parse::<syn::Token!(=)>()?;
+            let value = input.parse::<syn::Lit>()?;
+
+            items.push((name, value));
+
+            if input.is_empty() {
+                break;
+            }
+
+            input.parse::<syn::Token!(,)>()?;
+        }
+
+        let mut args = Self::default();
+
+        for (name, value) in items {
+            match name.to_string().as_str() {
+                "trampoline" => match value {
+                    syn::Lit::Bool(val) => {
+                        args.trampoline = val.value();
+                    }
+                    _ => {
+                        return Err(syn::Error::new_spanned(
+                            value,
+                            "Not a valid value. `trampoline` takes a boolean literal",
+                        ))
+                    }
+                },
+                _ => {
+                    return Err(syn::Error::new_spanned(name, "Not a valid argument name"));
+                }
+            }
+        }
+
+        Ok(args)
+    }
+}
+
+#[proc_macro_attribute]
+pub fn exception(args: TokenStream, input: TokenStream) -> TokenStream {
+    let mut f = parse_macro_input!(input as ItemFn);
+
+    if let Err(error) = check_attr_whitelist(&f.attrs, WhiteListCaller::Exception) {
+        return error;
+    }
+
+    let fspan = f.span();
+    let ident = f.sig.ident.clone();
+
+    let ident_s = ident.to_string();
+    let exn = match &*ident_s {
+        "DefaultHandler" => {
+            if !args.is_empty() {
+                return parse::Error::new(Span::call_site(), "This attribute accepts no arguments")
+                    .to_compile_error()
+                    .into();
+            }
+            Exception::DefaultHandler
+        }
+        "HardFault" => Exception::HardFault(parse_macro_input!(args)),
+        "NonMaskableInt" => {
+            if !args.is_empty() {
+                return parse::Error::new(Span::call_site(), "This attribute accepts no arguments")
+                    .to_compile_error()
+                    .into();
+            }
+            Exception::NonMaskableInt
+        }
+        // NOTE that at this point we don't check if the exception is available on the target (e.g.
+        // MemoryManagement is not available on Cortex-M0)
+        "MemoryManagement" | "BusFault" | "UsageFault" | "SecureFault" | "SVCall"
+        | "DebugMonitor" | "PendSV" | "SysTick" => {
+            if !args.is_empty() {
+                return parse::Error::new(Span::call_site(), "This attribute accepts no arguments")
+                    .to_compile_error()
+                    .into();
+            }
+
+            Exception::Other
+        }
+        _ => {
+            return parse::Error::new(ident.span(), "This is not a valid exception name")
+                .to_compile_error()
+                .into();
+        }
+    };
+
+    if f.sig.unsafety.is_none() {
+        match exn {
+            Exception::DefaultHandler | Exception::HardFault(_) | Exception::NonMaskableInt => {
+                // These are unsafe to define.
+                let name = format!("{}", exn);
+                return parse::Error::new(ident.span(), format_args!("defining a {} is unsafe and requires an `unsafe fn` (see the cortex-m-rt docs)", name))
+                    .to_compile_error()
+                    .into();
+            }
+            Exception::Other => {}
+        }
+    }
+
+    // Emit a reference to the `Exception` variant corresponding to our exception.
+    // This will fail compilation when the target doesn't have that exception.
+    let assertion = match exn {
+        Exception::Other => {
+            quote! {
+                const _: () = {
+                    let _ = ::cortex_m_rt::Exception::#ident;
+                };
+            }
+        }
+        _ => quote!(),
+    };
+
+    let handler = match exn {
+        Exception::DefaultHandler => {
+            let valid_signature = f.sig.constness.is_none()
+                && f.vis == Visibility::Inherited
+                && f.sig.abi.is_none()
+                && f.sig.inputs.len() == 1
+                && f.sig.generics.params.is_empty()
+                && f.sig.generics.where_clause.is_none()
+                && f.sig.variadic.is_none()
+                && match f.sig.output {
+                    ReturnType::Default => true,
+                    ReturnType::Type(_, ref ty) => match **ty {
+                        Type::Tuple(ref tuple) => tuple.elems.is_empty(),
+                        Type::Never(..) => true,
+                        _ => false,
+                    },
+                };
+
+            if !valid_signature {
+                return parse::Error::new(
+                    fspan,
+                    "`DefaultHandler` must have signature `unsafe fn(i16) [-> !]`",
+                )
+                .to_compile_error()
+                .into();
+            }
+
+            f.sig.ident = Ident::new(&format!("__cortex_m_rt_{}", f.sig.ident), Span::call_site());
+            let tramp_ident = Ident::new(&format!("{}_trampoline", f.sig.ident), Span::call_site());
+            let ident = &f.sig.ident;
+
+            let (ref cfgs, ref attrs) = extract_cfgs(f.attrs.clone());
+
+            quote!(
+                #(#cfgs)*
+                #(#attrs)*
+                #[doc(hidden)]
+                #[export_name = #ident_s]
+                pub unsafe extern "C" fn #tramp_ident() {
+                    extern crate core;
+
+                    const SCB_ICSR: *const u32 = 0xE000_ED04 as *const u32;
+
+                    let irqn = unsafe { (core::ptr::read_volatile(SCB_ICSR) & 0x1FF) as i16 - 16 };
+
+                    #ident(irqn)
+                }
+
+                #f
+            )
+        }
+        Exception::HardFault(args) => {
+            let valid_signature = f.sig.constness.is_none()
+                && f.vis == Visibility::Inherited
+                && f.sig.abi.is_none()
+                && if args.trampoline {
+                    f.sig.inputs.len() == 1
+                        && match &f.sig.inputs[0] {
+                            FnArg::Typed(arg) => match arg.ty.as_ref() {
+                                Type::Reference(r) => {
+                                    r.lifetime.is_none() && r.mutability.is_none()
+                                }
+                                _ => false,
+                            },
+                            _ => false,
+                        }
+                } else {
+                    f.sig.inputs.is_empty()
+                }
+                && f.sig.generics.params.is_empty()
+                && f.sig.generics.where_clause.is_none()
+                && f.sig.variadic.is_none()
+                && match f.sig.output {
+                    ReturnType::Default => false,
+                    ReturnType::Type(_, ref ty) => matches!(**ty, Type::Never(_)),
+                };
+
+            if !valid_signature {
+                return parse::Error::new(
+                    fspan,
+                    if args.trampoline {
+                        "`HardFault` handler must have signature `unsafe fn(&ExceptionFrame) -> !`"
+                    } else {
+                        "`HardFault` handler must have signature `unsafe fn() -> !`"
+                    },
+                )
+                .to_compile_error()
+                .into();
+            }
+
+            f.sig.ident = Ident::new(&format!("__cortex_m_rt_{}", f.sig.ident), Span::call_site());
+            let tramp_ident = Ident::new(&format!("{}_trampoline", f.sig.ident), Span::call_site());
+
+            if args.trampoline {
+                let ident = &f.sig.ident;
+
+                let (ref cfgs, ref attrs) = extract_cfgs(f.attrs.clone());
+
+                quote!(
+                    #(#cfgs)*
+                    #(#attrs)*
+                    #[doc(hidden)]
+                    #[export_name = "_HardFault"]
+                    // Only emit link_section when building for embedded targets,
+                    // because some hosted platforms (used to check the build)
+                    // cannot handle the long link section names.
+                    #[cfg_attr(target_os = "none", link_section = ".HardFault.user")]
+                    unsafe extern "C" fn #tramp_ident(frame: &::cortex_m_rt::ExceptionFrame) {
+                        #ident(frame)
+                    }
+
+                    #f
+
+                    // HardFault exceptions are bounced through this trampoline which grabs the stack pointer at
+                    // the time of the exception and passes it to the user's HardFault handler in r0.
+                    // Depending on the stack mode in EXC_RETURN, fetches stack from either MSP or PSP.
+                    core::arch::global_asm!(
+                        ".cfi_sections .debug_frame
+                        .section .HardFaultTrampoline, \"ax\"
+                        .global HardFault
+                        .type HardFault,%function
+                        .thumb_func
+                        .cfi_startproc
+                        HardFault:",
+                           "mov r0, lr
+                            movs r1, #4
+                            tst r0, r1
+                            bne 0f
+                            mrs r0, MSP
+                            b _HardFault
+                        0:
+                            mrs r0, PSP
+                            b _HardFault",
+                        ".cfi_endproc
+                        .size HardFault, . - HardFault",
+                    );
+                )
+            } else {
+                quote!(
+                    #[doc(hidden)]
+                    #[export_name = "_HardFault"]
+                    unsafe extern "C" fn #tramp_ident() {
+                        // This trampoline has no function except making the compiler diagnostics better.
+                    }
+
+                    #[export_name = "HardFault"]
+                    // Only emit link_section when building for embedded targets,
+                    // because some hosted platforms (used to check the build)
+                    // cannot handle the long link section names.
+                    #[cfg_attr(target_os = "none", link_section = ".HardFault.user")]
+                    #f
+                )
+            }
+        }
+        Exception::NonMaskableInt | Exception::Other => {
+            let valid_signature = f.sig.constness.is_none()
+                && f.vis == Visibility::Inherited
+                && f.sig.abi.is_none()
+                && f.sig.inputs.is_empty()
+                && f.sig.generics.params.is_empty()
+                && f.sig.generics.where_clause.is_none()
+                && f.sig.variadic.is_none()
+                && match f.sig.output {
+                    ReturnType::Default => true,
+                    ReturnType::Type(_, ref ty) => match **ty {
+                        Type::Tuple(ref tuple) => tuple.elems.is_empty(),
+                        Type::Never(..) => true,
+                        _ => false,
+                    },
+                };
+
+            if !valid_signature {
+                return parse::Error::new(
+                    fspan,
+                    "`#[exception]` handlers other than `DefaultHandler` and `HardFault` must have \
+                     signature `[unsafe] fn() [-> !]`",
+                )
+                .to_compile_error()
+                .into();
+            }
+
+            let (statics, stmts) = match extract_static_muts(f.block.stmts) {
+                Err(e) => return e.to_compile_error().into(),
+                Ok(x) => x,
+            };
+
+            f.sig.ident = Ident::new(&format!("__cortex_m_rt_{}", f.sig.ident), Span::call_site());
+            f.sig.inputs.extend(statics.iter().map(|statik| {
+                let ident = &statik.ident;
+                let ty = &statik.ty;
+                let attrs = &statik.attrs;
+                syn::parse::<FnArg>(
+                    quote!(#[allow(non_snake_case)] #(#attrs)* #ident: &mut #ty).into(),
+                )
+                .unwrap()
+            }));
+            f.block.stmts = iter::once(
+                syn::parse2(quote! {{
+                    // check that this exception actually exists
+                    ::cortex_m_rt::exception::#ident;
+                }})
+                .unwrap(),
+            )
+            .chain(stmts)
+            .collect();
+
+            let tramp_ident = Ident::new(&format!("{}_trampoline", f.sig.ident), Span::call_site());
+            let ident = &f.sig.ident;
+
+            let resource_args = statics
+                .iter()
+                .map(|statik| {
+                    let (ref cfgs, ref attrs) = extract_cfgs(statik.attrs.clone());
+                    let ident = &statik.ident;
+                    let ty = &statik.ty;
+                    let expr = &statik.expr;
+                    quote! {
+                        #(#cfgs)*
+                        {
+                            #(#attrs)*
+                            static mut #ident: #ty = #expr;
+                            unsafe { &mut #ident }
+                        }
+                    }
+                })
+                .collect::<Vec<_>>();
+
+            let (ref cfgs, ref attrs) = extract_cfgs(f.attrs.clone());
+
+            quote!(
+                #(#cfgs)*
+                #(#attrs)*
+                #[doc(hidden)]
+                #[export_name = #ident_s]
+                pub unsafe extern "C" fn #tramp_ident() {
+                    #[allow(static_mut_refs)]
+                    #ident(
+                        #(#resource_args),*
+                    )
+                }
+
+                #f
+            )
+        }
+    };
+
+    quote!(
+        #assertion
+        #handler
+    )
+    .into()
+}
+
+#[proc_macro_attribute]
+pub fn interrupt(args: TokenStream, input: TokenStream) -> TokenStream {
+    let mut f: ItemFn = syn::parse(input).expect("`#[interrupt]` must be applied to a function");
+
+    if !args.is_empty() {
+        return parse::Error::new(Span::call_site(), "This attribute accepts no arguments")
+            .to_compile_error()
+            .into();
+    }
+
+    let fspan = f.span();
+    let ident = f.sig.ident.clone();
+    let ident_s = ident.to_string();
+
+    // XXX should we blacklist other attributes?
+
+    let valid_signature = f.sig.constness.is_none()
+        && f.vis == Visibility::Inherited
+        && f.sig.abi.is_none()
+        && f.sig.inputs.is_empty()
+        && f.sig.generics.params.is_empty()
+        && f.sig.generics.where_clause.is_none()
+        && f.sig.variadic.is_none()
+        && match f.sig.output {
+            ReturnType::Default => true,
+            ReturnType::Type(_, ref ty) => match **ty {
+                Type::Tuple(ref tuple) => tuple.elems.is_empty(),
+                Type::Never(..) => true,
+                _ => false,
+            },
+        };
+
+    if !valid_signature {
+        return parse::Error::new(
+            fspan,
+            "`#[interrupt]` handlers must have signature `[unsafe] fn() [-> !]`",
+        )
+        .to_compile_error()
+        .into();
+    }
+
+    let (statics, stmts) = match extract_static_muts(f.block.stmts.iter().cloned()) {
+        Err(e) => return e.to_compile_error().into(),
+        Ok(x) => x,
+    };
+
+    f.sig.ident = Ident::new(&format!("__cortex_m_rt_{}", f.sig.ident), Span::call_site());
+    f.sig.inputs.extend(statics.iter().map(|statik| {
+        let ident = &statik.ident;
+        let ty = &statik.ty;
+        let attrs = &statik.attrs;
+        syn::parse::<FnArg>(quote!(#[allow(non_snake_case)] #(#attrs)* #ident: &mut #ty).into())
+            .unwrap()
+    }));
+    f.block.stmts = iter::once(
+        syn::parse2(quote! {{
+            // Check that this interrupt actually exists
+            interrupt::#ident;
+        }})
+        .unwrap(),
+    )
+    .chain(stmts)
+    .collect();
+
+    let tramp_ident = Ident::new(&format!("{}_trampoline", f.sig.ident), Span::call_site());
+    let ident = &f.sig.ident;
+
+    let resource_args = statics
+        .iter()
+        .map(|statik| {
+            let (ref cfgs, ref attrs) = extract_cfgs(statik.attrs.clone());
+            let ident = &statik.ident;
+            let ty = &statik.ty;
+            let expr = &statik.expr;
+            quote! {
+                #(#cfgs)*
+                {
+                    #(#attrs)*
+                    static mut #ident: #ty = #expr;
+                    unsafe { &mut #ident }
+                }
+            }
+        })
+        .collect::<Vec<_>>();
+
+    if let Err(error) = check_attr_whitelist(&f.attrs, WhiteListCaller::Interrupt) {
+        return error;
+    }
+
+    let (ref cfgs, ref attrs) = extract_cfgs(f.attrs.clone());
+
+    quote!(
+        #(#cfgs)*
+        #(#attrs)*
+        #[doc(hidden)]
+        #[export_name = #ident_s]
+        pub unsafe extern "C" fn #tramp_ident() {
+            #[allow(static_mut_refs)]
+            #ident(
+                #(#resource_args),*
+            )
+        }
+
+        #f
+    )
+    .into()
+}
+
+#[proc_macro_attribute]
+pub fn pre_init(args: TokenStream, input: TokenStream) -> TokenStream {
+    let f = parse_macro_input!(input as ItemFn);
+
+    // check the function signature
+    let valid_signature = f.sig.constness.is_none()
+        && f.vis == Visibility::Inherited
+        && f.sig.unsafety.is_some()
+        && f.sig.abi.is_none()
+        && f.sig.inputs.is_empty()
+        && f.sig.generics.params.is_empty()
+        && f.sig.generics.where_clause.is_none()
+        && f.sig.variadic.is_none()
+        && match f.sig.output {
+            ReturnType::Default => true,
+            ReturnType::Type(_, ref ty) => match **ty {
+                Type::Tuple(ref tuple) => tuple.elems.is_empty(),
+                _ => false,
+            },
+        };
+
+    if !valid_signature {
+        return parse::Error::new(
+            f.span(),
+            "`#[pre_init]` function must have signature `unsafe fn()`",
+        )
+        .to_compile_error()
+        .into();
+    }
+
+    if !args.is_empty() {
+        return parse::Error::new(Span::call_site(), "This attribute accepts no arguments")
+            .to_compile_error()
+            .into();
+    }
+
+    if let Err(error) = check_attr_whitelist(&f.attrs, WhiteListCaller::PreInit) {
+        return error;
+    }
+
+    // XXX should we blacklist other attributes?
+    let attrs = f.attrs;
+    let ident = f.sig.ident;
+    let block = f.block;
+
+    quote!(
+        #[export_name = "__pre_init"]
+        #[allow(missing_docs)]  // we make a private fn public, which can trigger this lint
+        #(#attrs)*
+        pub unsafe fn #ident() #block
+    )
+    .into()
+}
+
+/// Extracts `static mut` vars from the beginning of the given statements
+fn extract_static_muts(
+    stmts: impl IntoIterator<Item = Stmt>,
+) -> Result<(Vec<ItemStatic>, Vec<Stmt>), parse::Error> {
+    let mut istmts = stmts.into_iter();
+
+    let mut seen = HashSet::new();
+    let mut statics = vec![];
+    let mut stmts = vec![];
+    for stmt in istmts.by_ref() {
+        match stmt {
+            Stmt::Item(Item::Static(var)) => match var.mutability {
+                syn::StaticMutability::Mut(_) => {
+                    if seen.contains(&var.ident) {
+                        return Err(parse::Error::new(
+                            var.ident.span(),
+                            format!("the name `{}` is defined multiple times", var.ident),
+                        ));
+                    }
+
+                    seen.insert(var.ident.clone());
+                    statics.push(var);
+                }
+                _ => stmts.push(Stmt::Item(Item::Static(var))),
+            },
+            _ => {
+                stmts.push(stmt);
+                break;
+            }
+        }
+    }
+
+    stmts.extend(istmts);
+
+    Ok((statics, stmts))
+}
+
+fn extract_cfgs(attrs: Vec<Attribute>) -> (Vec<Attribute>, Vec<Attribute>) {
+    let mut cfgs = vec![];
+    let mut not_cfgs = vec![];
+
+    for attr in attrs {
+        if eq(&attr, "cfg") {
+            cfgs.push(attr);
+        } else {
+            not_cfgs.push(attr);
+        }
+    }
+
+    (cfgs, not_cfgs)
+}
+
+enum WhiteListCaller {
+    Entry,
+    Exception,
+    Interrupt,
+    PreInit,
+}
+
+fn check_attr_whitelist(attrs: &[Attribute], caller: WhiteListCaller) -> Result<(), TokenStream> {
+    let whitelist = &[
+        "doc",
+        "link_section",
+        "cfg",
+        "allow",
+        "warn",
+        "deny",
+        "forbid",
+        "cold",
+        "naked",
+        "expect",
+    ];
+
+    'o: for attr in attrs {
+        for val in whitelist {
+            if eq(attr, val) {
+                continue 'o;
+            }
+        }
+
+        let err_str = match caller {
+            WhiteListCaller::Entry => "this attribute is not allowed on a cortex-m-rt entry point",
+            WhiteListCaller::Exception => {
+                "this attribute is not allowed on an exception handler controlled by cortex-m-rt"
+            }
+            WhiteListCaller::Interrupt => {
+                "this attribute is not allowed on an interrupt handler controlled by cortex-m-rt"
+            }
+            WhiteListCaller::PreInit => {
+                "this attribute is not allowed on a pre-init controlled by cortex-m-rt"
+            }
+        };
+
+        return Err(parse::Error::new(attr.span(), err_str)
+            .to_compile_error()
+            .into());
+    }
+
+    Ok(())
+}
+
+/// Returns `true` if `attr.path` matches `name`
+fn eq(attr: &Attribute, name: &str) -> bool {
+    attr.style == AttrStyle::Outer && attr.path().is_ident(name)
+}

### external/vendor/cortex-m-rt/.cargo-checksum.json
@@ -0,0 +1 @@
+{"files":{".cargo/config.toml":"906b46f92d786174dfce31f1d338770568d3617c5b93e8331fc9d3377cd6afe6",".cargo_vcs_info.json":"c87d46603cc3b1b815eea03f189804adc90607ae72e5c5c50d33ac79d2bc04ad","CHANGELOG.md":"38cb74681fbfb3f0f0d6a0fb3dfb41ad2eded8302776f8edbf2a77a6ae5b5ff6","Cargo.lock":"08d150b9fbdf3e8a902a04a6e8b57563c139758285fcc1da17d58931c9142cd7","Cargo.toml":"2bade3faff536bea755d13fbcabfb3ea35d6c6dce957df79af1786399520575e","Cargo.toml.orig":"fbd8d2d40237341c7407e3692cec4310191a985479eacbaba05561adfa67b650","README.md":"19fbdc898f675a2fcec4d061513105364af1cce851ee32704204a4c1853a79ec","build.rs":"99ca7a5ed5ad2697a406a5cf0fb3e8547a04a2ca5e26b4db43d49ab592f92f4a","ci/script.sh":"69a9358ed9c6b17447cb51ca34506c4d8b3a069b415cfa1264636cc332983d09","examples/alignment.rs":"3c653dbf7be49e7e0b9bd9f3b5d9fb56f62267c178ee338e0d5f04eff924f357","examples/cfg-static.rs":"a82b62a4af2792bc15add71de6845836d2bcf16f08fb55768b2ad640bc6001f4","examples/data_overflow.rs":"b339968260f9ea3f8454cc8bb2ce532be50bcf9b81f13b607a89bbfa7fb0e1d1","examples/device.rs":"b1e6e10b7fbdf0784bc9dead47596572c42d518f767f4bda5c7457417ac75eff","examples/divergent-default-handler.rs":"ddcceb8a6bcf939e66320e1c876932b5f9b0c58a5f70797ddf63a86a17478611","examples/divergent-exception.rs":"6c286edd17afa258e202fe72d3c682410de6310cb9327134816d4684907d6006","examples/entry-static.rs":"e5579c8e8a7d414cd51af983eadd87e39b334e4d6312f48d557c00e3ef6b2b48","examples/hard-fault-trampoline.rs":"f214137ae3d05b177f78dc270bb6fdd33618eeeffd4ad33fde12878ab22c5694","examples/main.rs":"82b9d5d1649e8da328cca8f6dab6144be3443f8a1e4cc76a43f4bea364173451","examples/minimal.rs":"f66ace7010aa8a5b8ca47a97b254939047314b46cedb19689e4625d71a9cbad3","examples/override-exception.rs":"8aafc496badda846f42b9a75c47426175b3e70841d08e7b41371c1413827943a","examples/pre_init.rs":"2a13b45353761ec4f632ee89e865f46d353c02fb73b6d72768e9ef498dba9946","examples/qemu.rs":"bbc31554710816cb238cee8ac670a869c414fe200aa8c048874d2692e9b222bd","examples/state.rs":"6927d661beced2acaa6059cf394298e4d1ccd3d17175945123a41e67cdfc792c","examples/unsafe-default-handler.rs":"aabce6a3380be15d3d059b9dbf809b93f67ecd750c38d83190fdc9f8a1f286aa","examples/unsafe-entry.rs":"a0db7e3961800989cb2658efdaff86cd7f9459414b899f4b69117c752692484a","examples/unsafe-exception.rs":"ea534617e988672dfaf385c403818f55f295de2531af1d3ecd0d5984d7b9187f","examples/unsafe-hard-fault.rs":"4139e666b022b172a6772f24c70b699f7cda0228185428d5be2c7c92650e5614","examples/unsafety.rs":"e39698bc3e75cae3e7a96d5e008b2ca3fb47970c024863698a7b55b8bf3fc1c4","examples/warnings.rs":"4fd9ee498f738161f618d2feb9b4045398647361feffc84a8027437e0926e333","link.x.in":"c6890afc1cefc9f78574104c7c0cd06ec5c485df3e441021b4c2b3593ccaf5c7","src/lib.rs":"e530ce139e7d53337f468aab4102df11f95caf808914f1bda8937ae1ace03c86","tests/README.md":"c955f3a0b55d39230f90b8dbfd59d39e8463c6391e9f0a33c98dfda9d16e6c21","tests/compile-fail/default-handler-bad-signature-1.rs":"fda1cfe10f8546bafe63d07cbe3307fa73e56ef001dece4b7724a11a586c05a1","tests/compile-fail/default-handler-bad-signature-2.rs":"1f59db99c9d1e46e3823a34224d19b0d41531e6813b52a2ede822b69c5c63ac1","tests/compile-fail/default-handler-hidden.rs":"a75665fe6a89a19f33a2c2d0fc3495f433a17544d0a8d3c07f0a53a9847d6991","tests/compile-fail/default-handler-twice.rs":"df94e46696f6ff0486c178ce0c1f615a2432630feb5da01dca0f694536a7aed1","tests/compile-fail/duplicate-static.rs":"0ce0e47bd2ff975921ef0246812f63e3b5ef86c9e7459213acddae2be4fa907d","tests/compile-fail/entry-args.rs":"b375df87c096746c6ffec50d923f8c8c135483a4667895da67d45aa1c1699a78","tests/compile-fail/entry-bad-signature-1.rs":"0febd74608e8659038a7459b5680190bc4a82be7879c42e052c4d1b45cb93288","tests/compile-fail/entry-bad-signature-2.rs":"80cc72e8221bdbad15d2866e675d7dd18ef6bf2a1159823e811f9f243bf2ecb5","tests/compile-fail/entry-bad-signature-3.rs":"36b831e838a0ad53127426ee8abb742dbb94586d08ef1b96568e00592bcfed01","tests/compile-fail/entry-hidden.rs":"c8d30a641aa8b935716b64c32bd7eceee05bd1d19b21e8bb4751fc526c50bca4","tests/compile-fail/entry-soundness.rs":"d44ed5a86a882c84b105dab182d6057e04faceb80be98a1d21ee3f66221867eb","tests/compile-fail/entry-twice.rs":"d838b3ca815fee86e26b5c349ff436639cce79875ca0cc7cf7e79d44532bfb6c","tests/compile-fail/exception-args.rs":"c02ae0ba76fcae0fdf0c4da0d74e565377b763e4a7bafd552e905895283681da","tests/compile-fail/exception-bad-signature-1.rs":"e5b92cc8b663e159f113449badadba1a41e13282eb015ea029a07e2733e8b867","tests/compile-fail/exception-bad-signature-2.rs":"ee0b8e063aa683f5c962f5d5fa40dbc82194d7a6b8cecd46e3ac5025f7c548e3","tests/compile-fail/exception-hidden.rs":"9e3bb7dcdb090e5afefba4e83abf333b1f9ea3d01ed138f4181e6f6796a46ac1","tests/compile-fail/exception-nmi-unsafe.rs":"1262c0b3b376b10f4fdc7f50d91ad244714761f5c183128aa73c940dc33e4327","tests/compile-fail/exception-soundness.rs":"ffb5e5cd19c11b52325e77a5706ba9ccf47a892f3a46e82d70b603a527871ef9","tests/compile-fail/exception-twice.rs":"bba3c0c92d22a99a7672aaf1037001b35a77eb0527191753bdfd585b6e279af0","tests/compile-fail/exception-v8only.rs":"990d1755e6cd13f17e186ef0307bccefaa27449da683b46a004d462e85f99abe","tests/compile-fail/hard-fault-bad-signature-1.rs":"7af9b0f4b59c79b1a50aafa57a8dbab1abf1f5240be6876a0d1faebc925425c2","tests/compile-fail/hard-fault-bad-signature-2.rs":"c3b2c797d9f577bf1217e6170dfd385b76ffa4a05ffe8ec6e46d99a5a8684703","tests/compile-fail/hard-fault-bad-signature-3.rs":"061cd0e091021eb354d51f5c46707b9661a448ae775df97866f6a816f9ab3f3c","tests/compile-fail/hard-fault-hidden.rs":"405a6d91aaa6d85e0da7e9901047b254d2c3fc7aa18fbdc71b511785bd4ff5b5","tests/compile-fail/hard-fault-twice-mixed-trampoline.rs":"582e2b86d548742fb67658053b1dc82a7088698abdd804a1e62c0eb66c6f425e","tests/compile-fail/hard-fault-twice.rs":"64e1c6e6a9b69d1a22e9a41ce68dd2366bc6a4393ff7bf9aaea1a856c09d4c5d","tests/compile-fail/interrupt-args.rs":"a840ba3af7831f23e0078441376f1fa8c8d8f11e9419fbf984044d3f63ca8df1","tests/compile-fail/interrupt-bad-signature-1.rs":"4c5cc9501b4787011316ddaecee819aa2bfbb2e675a2929da609e78849de6669","tests/compile-fail/interrupt-bad-signature-2.rs":"43ceca9d1f83c84481a6e310ff638099ba13e840146d0d19b4121e297a5ec351","tests/compile-fail/interrupt-invalid.rs":"f169f4bb1d0d9c2aabe6e1ec61b07bfb300b566d9c02d2fa4915084c70709a15","tests/compile-fail/interrupt-not-reexported.rs":"66f4eefd0ff2a619cb6c39435ba2e69b07aa514007e6ae197c65239b39e4c725","tests/compile-fail/interrupt-soundness.rs":"c1580705712100f6df278e9698a244d2fa4c058ca23556d36253ff0d529a9b4c","tests/compile-fail/interrupt-twice.rs":"86bff6d7a738ad1026cd17784445b62ff4d75b4810dcaa737bb4d6c3442ebec0","tests/compile-fail/non-static-resource.rs":"2603f7514ce8e1b81dbf0c543d4ce7fea81e24f1332bc0f821ad97395ecb7119","tests/compile-fail/pre-init-args.rs":"21ace9a720927454ed2f081b9e395d902e096627fcdee6c1109fcb8cd3f22559","tests/compile-fail/pre-init-bad-signature-1.rs":"9c6c37e1acecec6feddedb1860a9d6be102e0e477aa50d48ba1c64315d3d5b1b","tests/compile-fail/pre-init-bad-signature-2.rs":"a7c1f405e5a143f54e29eca0aab388c672fb60050c34a9de0d21939c09696142","tests/compile-fail/pre-init-hidden.rs":"87450d6d1ec0bea69703b1f9275d7ea3387f67d4e226e6cce7de9589268b7ded","tests/compile-fail/pre-init-twice.rs":"4f6b93d7d2651f5df5a2e566ad3765c42bf386d979887cb77ca271b98889a934","tests/compile-fail/unsafe-init-static.rs":"141eceec11c27ee5d614c3344b58c34dcb2a129f5106ddbe324d168943e794c1","tests/compile-fail/whitelist-1.rs":"372a7313b459b882b50c2ced878489d1eaf3ca58d5db9ce69c45d30b1f40a0f2","tests/compile-fail/whitelist-2.rs":"b1ebbfe9dfc401e0aaa9319d4552af73affa4bf6c1537ca5e3e2ac82c066758a","tests/compile-fail/whitelist-3.rs":"9b6e60d29ad8c07e21d38793f6d8d795e8235c8cc217560b1676d6757ceb5f14","tests/compile-fail/whitelist-4.rs":"b6e7d2b6048d138da0e2fdaef868974fcc6a041e4873f75ca2b7b8979ce10100","tests/compile-fail/whitelist-double-attr.rs":"1e798d43b5bae228efe2b6267272e7f3456f07f8135bcc81e233b93696c340f1","tests/compiletest.rs":"862ed0b30b6c69eb06c9e90218f89567859efc45a26e83887150ec4e07f70053"},"package":"801d4dec46b34c299ccf6b036717ae0fce602faa4f4fe816d9013b9a7c9f5ba6"}
\ No newline at end of file

### external/vendor/cortex-m-rt/.cargo/config.toml
@@ -0,0 +1,34 @@
+[target.thumbv6m-none-eabi]
+runner = "qemu-system-arm -cpu cortex-m0 -machine lm3s6965evb -nographic -semihosting-config enable=on,target=native -kernel"
+
+[target.thumbv7m-none-eabi]
+runner = "qemu-system-arm -cpu cortex-m3 -machine lm3s6965evb -nographic -semihosting-config enable=on,target=native -kernel"
+
+[target.thumbv7em-none-eabi]
+runner = "qemu-system-arm -cpu cortex-m4 -machine lm3s6965evb -nographic -semihosting-config enable=on,target=native -kernel"
+
+[target.thumbv7em-none-eabihf]
+runner = "qemu-system-arm -cpu cortex-m4 -machine lm3s6965evb -nographic -semihosting-config enable=on,target=native -kernel"
+
+[target.'cfg(all(target_arch = "arm", target_os = "none"))']
+# uncomment ONE of these three option to make `cargo run` start a GDB session
+# which option to pick depends on your system
+# runner = "arm-none-eabi-gdb -q -x openocd.gdb"
+# runner = "gdb-multiarch -q -x openocd.gdb"
+# runner = "gdb -q -x openocd.gdb"
+
+rustflags = [
+  # LLD (shipped with the Rust toolchain) is used as the default linker
+  "-C", "link-arg=-Tlink.x",
+
+  # if you run into problems with LLD switch to the GNU linker by commenting out
+  # this line
+  # "-C", "linker=arm-none-eabi-ld",
+
+  # if you need to link to pre-compiled C libraries provided by a C toolchain
+  # use GCC as the linker by commenting out both lines above and then
+  # uncommenting the three lines below
+  # "-C", "linker=arm-none-eabi-gcc",
+  # "-C", "link-arg=-Wl,-Tlink.x",
+  # "-C", "link-arg=-nostartfiles",
+]

### external/vendor/cortex-m-rt/.cargo_vcs_info.json
@@ -0,0 +1,6 @@
+{
+  "git": {
+    "sha1": "91772718fec2e07b0ccabeb019e509a53d3eecda"
+  },
+  "path_in_vcs": "cortex-m-rt"
+}
\ No newline at end of file

### external/vendor/cortex-m-rt/CHANGELOG.md
@@ -0,0 +1,699 @@
+# Change Log
+
+All notable changes to this project will be documented in this file.
+
+The format is based on [Keep a Changelog](http://keepachangelog.com/)
+and this project adheres to [Semantic Versioning](http://semver.org/).
+
+## [Unreleased]
+
+## [v0.7.5]
+
+- Fix incorrect dependency on cortex-m-rt-macros in v0.7.4 which led to
+  incorrect HardFault handlers being generated.
+- MSRV is now Rust 1.61 to support syn verions >=2.0.68
+- The `_stack_end` symbol is added, e.g. for use with MSPLIM (#565)
+- Macros now expand to include an `unsafe` block and `allow(static_mut_refs)`
+  when generating the `&'static mut` references in entry/interrupt handlers
+  (#561, #558)
+- `expect` attribute now permitted on entry/interrupt handlers (#557)
+- Up to 496 interrupts now permitted on ARMv8-M (#555)
+- Add new `paint-stack` feature which writes a fixed value to the entire stack
+  during initialisation (#548)
+- The hard fault handler `_HardFault` is now placed in the `.HardFault.user`
+  linker section (#535)
+
+## [v0.7.4]
+
+- Add `zero-init-ram` feature to initialize RAM with zeros on startup.
+  This can be necessary to properly initialise hardware error detection.
+- Add optional `exception` argument for `HardFault`.
+  It has one option `trampoline` which is `true` by default. When set to `false`,
+  no trampoline will be created and the function will be called as the
+  exception handler directly.
+- MSRV increased to 1.60.0 to align with `embedded-hal` version 1.
+- Improve linker error message when code does not fit into flash.
+- Update documentation on using custom linker scripts and linker sections
+  and on the `pre_init` function.
+
+## [v0.7.3]
+
+- Fixed a potential miscompilation caused by the initial stack pointer
+  not being 8-byte aligned. This issue affected 0.7.1 and 0.7.2; for
+  more details please see [the advisory] ([#467]).
+- A linker error is generated if the initial stack pointer is not 8-byte aligned ([#464]).
+- The initial stack pointer is now forced to be 8-byte aligned in the linker script,
+  to defend against it being overridden outside of the cortex-m-rt linker script ([#465]).
+
+[the advisory]: https://github.com/rust-embedded/cortex-m/discussions/469
+[#464]: https://github.com/rust-embedded/cortex-m/issues/464
+[#465]: https://github.com/rust-embedded/cortex-m/issues/465
+[#467]: https://github.com/rust-embedded/cortex-m/issues/467
+
+## [v0.7.2]
+
+- MSRV is now Rust 1.59.
+- Moved precompiled assembly blobs to `global_asm!`, requiring Rust 1.59.
+- Add new `set_vtor` and `set-sp` features to conditionally set the VTOR and SP
+  registers at device reset ([#423]).
+- Allow (unstable) `naked` attribute on interrupt handlers and `pre_init`.
+
+## Fixes
+
+- Fix `cortex_m_rt::exception` macro no longer being usable fully-qualified ([#414])
+- Fix veneer limit position in linker script ([#434]).
+
+[#414]: https://github.com/rust-embedded/cortex-m/issues/414
+[#423]: https://github.com/rust-embedded/cortex-m/issues/423
+[#434]: https://github.com/rust-embedded/cortex-m/issues/434
+
+## Notes
+
+- From this release onwards, cortex-m-rt lives in the cortex-m repository;
+  issue numbers refer there.
+
+## [v0.7.1]
+
+## Fixes
+
+- Fix stack unwinding past `Reset` function ([#337])
+
+[#337]: https://github.com/rust-embedded/cortex-m-rt/pull/337
+
+## [v0.7.0]
+
+### New Features
+
+- Add support for CMSE secure gateway veneers ([#297]).
+- Allow using the crate with custom target JSON specs ([#304]).
+- Export Exception enum for other crates to use ([#224]).
+
+[#224]: https://github.com/rust-embedded/cortex-m-rt/pull/224
+[#297]: https://github.com/rust-embedded/cortex-m-rt/pull/297
+[#304]: https://github.com/rust-embedded/cortex-m-rt/pull/304
+
+### Fixes
+
+- Various fixes to the linker script ([#265], [#286], [#287], [#323]).
+- Use the correct ABI for the `main` symbol ([#278]).
+- Add barriers after FPU enabling ([#279]).
+- (ARMv6-M) Set LR value to a known value on reset ([#293]).
+- Added CFI and size info to external assembly subroutines (`HardFaultTrampoline` and `FpuTrampoline`) ([#294]).
+- Allow building the crate for macOS targets ([#306], [#310]).
+- Perform RAM initialization in assembly, to avoid potential UB in Rust ([#301]).
+- Perform volatile reads of ICSR in DefaultHandler ([#315]).
+
+[#265]: https://github.com/rust-embedded/cortex-m-rt/pull/265
+[#278]: https://github.com/rust-embedded/cortex-m-rt/pull/278
+[#279]: https://github.com/rust-embedded/cortex-m-rt/pull/279
+[#286]: https://github.com/rust-embedded/cortex-m-rt/pull/286
+[#287]: https://github.com/rust-embedded/cortex-m-rt/pull/287
+[#293]: https://github.com/rust-embedded/cortex-m-rt/pull/293
+[#294]: https://github.com/rust-embedded/cortex-m-rt/pull/294
+[#301]: https://github.com/rust-embedded/cortex-m-rt/pull/301
+[#306]: https://github.com/rust-embedded/cortex-m-rt/pull/306
+[#310]: https://github.com/rust-embedded/cortex-m-rt/pull/310
+[#315]: https://github.com/rust-embedded/cortex-m-rt/pull/315
+[#323]: https://github.com/rust-embedded/cortex-m-rt/pull/323
+
+### Breaking Changes
+
+- Make `ExceptionFrame`s fields private, adding setters and getters instead
+  ([#239]).
+- Only allow certain attributes on handlers, and apply them to the trampoline
+  too ([#228]).
+- Make it unsafe to define exception handlers for NMIs ([#289]).
+- Check that exceptions exist on the target chip when registering a handler for
+  them ([#308]).
+
+[#239]: https://github.com/rust-embedded/cortex-m-rt/pull/239
+[#228]: https://github.com/rust-embedded/cortex-m-rt/pull/228
+[#289]: https://github.com/rust-embedded/cortex-m-rt/pull/289
+[#308]: https://github.com/rust-embedded/cortex-m-rt/pull/308
+
+### Other
+
+- Change macros crate to use same version number as cortex-m-rt crate ([#245]).
+- Discourage use of `pre_init` in documentation ([#248]).
+- Backport: Use `links` in Cargo.toml to prevent multiple linking of
+  cortex-m-rt ([#276]).
+
+[#245]: https://github.com/rust-embedded/cortex-m-rt/pull/245
+[#248]: https://github.com/rust-embedded/cortex-m-rt/pull/248
+[#276]: https://github.com/rust-embedded/cortex-m-rt/pull/276
+
+## Backport release: [v0.6.15] - 2021-07-12
+
+### Fixed
+
+- Backport: Mark .bss as NOLOAD ([#265])
+- Backport: Fix possible overflow of .data region ([#286])
+- Backport: Perform volatile reads of ICSR in DefaultHandler ([#315])
+
+### Other
+- Backport: Use `links` in Cargo.toml to prevent multiple linking of
+  cortex-m-rt ([#276])
+- Backport: Use same verison for macros crate as for cortex-m-rt itself
+  ([#245])
+
+[#245]: https://github.com/rust-embedded/cortex-m-rt/pull/245
+[#265]: https://github.com/rust-embedded/cortex-m-rt/pull/265
+[#276]: https://github.com/rust-embedded/cortex-m-rt/pull/276
+[#286]: https://github.com/rust-embedded/cortex-m-rt/pull/286
+[#315]: https://github.com/rust-embedded/cortex-m-rt/pull/315
+
+## [v0.6.14] - 2021-05-19
+
+### Fixed
+
+- Backport: Allow building the crate for macOS targets ([#306], [#310]).
+
+[#306]: https://github.com/rust-embedded/cortex-m-rt/issues/306
+[#310]: https://github.com/rust-embedded/cortex-m-rt/issues/310
+
+## Backport release: [v0.6.13] - 2020-09-07
+
+### Fixed
+
+- (ARMv6-M) Set LR value to a known value on reset (as the ARM spec requires)
+- Added CFI and size info to external assembly subroutines (`HardFaultTrampoline`)
+
+## Backport release: [v0.6.12] - 2020-01-26
+
+### Fixed
+
+- Fixed lint warnings getting emitted on macro-generated code.
+
+## [v0.6.11] - 2019-12-04
+
+### Changed
+
+- Macros now generate a second trampoline function instead of randomizing the
+  function's symbol name. This makes the build deterministic.
+- [breaking-change] `static mut` resources no longer have `'static` lifetime
+  except in the `#[entry]` function (this is a soundness fix; see [#212]).
+
+[#212]: https://github.com/rust-embedded/cortex-m-rt/issues/212
+
+## [v0.6.10] - 2019-07-25
+
+### Fixed
+
+- Linker template now takes and discard `*(.ARM.exidx)`
+
+## [v0.6.9] - 2019-07-11
+
+### Added
+
+- Input `.uninit.*` sections are now collected into an output `.uninit` section.
+  Uninitialized static variables are meant to be placed in these sections. The
+  output `.uninit` section is not initialized by the runtime.
+
+## [v0.6.8] - 2019-04-02
+
+### Fixed
+
+- Correct stack-pointer is selected on `HardFault`
+- Linker template now takes and discard `*(.ARM.extab.*)`
+- Misc. documentation fixes
+
+### Changed
+
+- Architecture added: `armv8-m.main`
+- Cortex-M team added to `authors`
+- The nightly build is allowed to fail in CI
+
+## [v0.6.7] - 2018-12-15
+
+### Fixed
+
+- entry / exception / interrupt: `#[cfg]` attributes used on `static mut`
+  variables are now properly handled.
+
+## [v0.6.6] - 2018-12-06
+
+### Changed
+
+- Misuse of attributes now produce compiler errors with proper spans instead of
+  panicking messages.
+
+- The `HardFault` symbol has been renamed to `HardFaultTrampoline`; likewise the
+  `UserHardFault` symbol has been renamed to `HardFault`. If you were using
+  breakpoints on `UserHardFault` to detect hard fault you should now put those
+  breakpoints on the `HardFault` symbol.
+
+### Fixed
+
+- Attributes on local `static mut` variables (declared at the beginning of
+  `entry` / `interrupt` / `exception`) are now respected.
+
+- The "GDB can now unwind HardFault callstacks" fix from the previous release
+  broke `HardFault`'s' `&ExceptionFrame` argument (the pointer was off by 8
+  bytes). This release fixes that problem without compromising GDB's ability to
+  unwind `HardFault`s.
+
+## [v0.6.5] - 2018-10-23
+
+### Changed
+
+- We now keep `.stack_sizes` by default, for use with external tooling.
+- (macros) New `#[interrupt]` attribute added, similar to `#[exception]` for
+  use with device-specific interrupt handlers.
+
+### Fixed
+
+- GDB can now unwind HardFault callstacks
+
+## [v0.6.4] - 2018-09-25
+
+### Changed
+
+- (macros) Improved the error message when any of the attribute is used on the
+  wrong kind of item.
+
+### Fixed
+
+- (macros) The expansion of the `exception` attribute now uses the `extern "C"`
+  ABI which is what the hardware expects.
+
+- (macros) `entry` and `exception` now respect the declared unsafety. That is
+  `#[entry] unsafe main() -> !` won't require `unsafe` blocks to use `unsafe`
+  API.
+
+## [v0.6.3] - 2018-09-09
+
+### Fixed
+
+- Fixed the `rand` problem for real.
+
+## [v0.6.2] - 2018-09-09
+
+### Fixed
+
+- Worked around a Cargo limitation that broke builds that depend on `rand`.
+
+- Updated the documentation link in the README to point to working docs.
+
+## [v0.6.1] - 2018-09-06
+
+### Changed
+
+- Produce a better error message if two (or more) copies of `cortex-m-rt` are
+  going to be linked into a binary.
+
+## [v0.6.0] - 2018-09-06
+
+### Changed
+
+- [breaking-change] the `entry!`, `pre_init!` and `exception!` macros have been
+  replaced with attributes: `#[entry]`, `#[pre_init]` and `#[exception]`,
+  respectively. This also changes the toolchain requirement to 1.30-beta or
+  newer.
+
+## [v0.5.3] - 2018-08-27
+
+### Changed
+
+- This crate no longer depends on `arm-none-eabi-gcc`.
+
+## [v0.5.2] - 2018-08-11
+
+### Added
+
+* A `pre_init!` macro and related functionality to run a function immediately
+  after reset, before memory initialisation
+
+### Changed
+
+- The `entry!` and `exception!` macros now also accept a closure instead of a path.
+
+- `DefaultHandler` and `UserHardFault` now default to an infinite loop if left undefined.
+
+### Fixed
+
+* Linked script modified to correctly detect `FLASH` overflow caused by `.data`
+
+## [v0.5.1] - 2018-05-14
+
+### Fixed
+
+- A recompilation problem where this `cortex-m-rt` would be recompiled every time `cargo build` is
+  invoked.
+
+## [v0.5.0] - 2018-05-12
+
+### Added
+
+- An `entry!` macro to set the entry point of the program.
+
+- A `heap_start` function that returns a pointer into the start of the heap region.
+
+- A `device` feature. When disabled this crate provides the interrupt vectors; when enabled the
+  interrupt vectors are expected to be provided by another crate. Read the documentation for
+  details.
+
+### Changed
+
+- This crate now compiles on the beta and stable channels.
+
+- [breaking-change] this crate now requires `arm-none-eabi-gcc` to be installed and available in
+  `$PATH` to compile.
+
+- [breaking-change] the `start` lang item has been removed. The standard `main` interface won't
+  work. Instead use `#![no_main]` and the `entry!` macro. See documentation for details.
+
+- [breaking-change] the `default_handler!` macro has been merged into the `exception!` macro. Use
+  `exception!(*, ..)` to set the default exception handler.
+
+- [breaking-change] there's no weak default handler so a default handler must be defined by the
+  application, or one of its dependencies.
+
+- [breaking-change] the syntax of the third argument of the `exception!` handler has changed. See
+  the documentation of the macro for details.
+
+- [breaking-change] the exception names that the `exception!` macro accepts has changed to match the
+  CMSIS specification. See the documentation of the macro for the list of names it accepts.
+
+- [breaking-change] The number of symbol interfaces has been reduced. Check the advanced section of
+  the documentation for details.
+
+## [v0.4.0] - 2018-04-09
+
+### Added
+
+- LLD support. The linker script provided by this crate has been tweaked to support both LLD and GNU
+  LD. To use LLD as a linker change `.cargo/config` to look like this:
+
+``` diff
+ [target.thumbv7m-none-eabi]
+ rustflags = [
+   "-C", "link-arg=-Tlink.x",
+-  "-C", "linker=arm-none-eabi-ld",
+-  "-Z", "linker-flavor=ld",
++  "-C", "linker=lld",
++  "-Z", "linker-flavor=ld.lld",
+ ]
+```
+
+### Removed
+
+- [breaking-change] Stack overflow protection has been removed. Unfortunately, supporting this
+  feature produces totally wrong `arm-none-eabi-size` reports when LLD is used to link the
+  program. If you need the stack overflow protection feature you can continue to use version
+  v0.3.13+.
+
+- [breaking-change] The "abort-on-panic" Cargo feature, which provided a `panic_fmt` implementation,
+  has been removed. If you were using this feature you can instead use a [panic implementation
+  crate][panic-impl].
+
+[panic-impl]: https://crates.io/keywords/panic-impl
+
+## [v0.3.15] - 2018-04-08
+
+### Fixed
+
+- Support the newest nightly
+
+## [v0.3.14] - 2018-04-01
+
+### Fixed
+
+- `dev` channel support
+
+## [v0.3.13] - 2018-02-17
+
+### Added
+
+- Fictitious `.stack` and `.heap` linker sections that represent the locations of the stack and the
+  heap in RAM. You can visualize these linker sections by running `arm-none-eabi-size -Ax` over your
+  binary.
+
+- Zero cost stack overflow protection when you use the `cortex-m-rt-ld` linker. Check documentation
+  for details.
+
+- A `_heap_size` symbol that indicates how large the heap is. This symbol is only used when
+  `cortex-m-rt-ld` is used as a linker.
+
+## [v0.3.12] - 2018-01-17
+
+### Fixed
+
+- Support for recent nightlies.
+
+## [v0.3.11] - 2018-01-17 - YANKED
+
+### Changed
+
+- Dynamically support recent nightlies, which have the `termination` lang item, and
+  nightly-2017-09-22, which doesn't. That nightly version is used by the docs.rs builder. Supporting
+  that version instead of rejecting it ensures this crate and its reverse-dependencies will get
+  their documentation built by the docs.rs service.
+
+## [v0.3.10] - 2018-01-17 - YANKED
+
+### Removed
+
+- The nightly date check from build script that improved error messages for users of old,
+  unsupported nightlies. Unfortunately the check was preventing this crate and reverse-dependencies
+  from getting their documentation build on docs.rs
+
+## [v0.3.9] - 2018-01-07
+
+### Fixed
+
+- `cargo doc` warnings
+
+## [v0.3.8] - 2017-12-29
+
+### Added
+
+- `Termination` lang item
+
+### Changed
+
+- The `start` lang item to match the new signature
+
+## [v0.3.7] - 2017-12-23
+
+### Added
+
+- Support for overriding the DEBUG_MONITOR exception handler on ARMv7-M.
+
+## [v0.3.6] - 2017-10-03
+
+### Fixed
+
+- Builds with multiple codegen units by forcing the linker to look harder for the exceptions vector
+  table.
+
+## [v0.3.5] - 2017-07-21
+
+### Fixed
+
+- Remove duplication of default exception handlers. This saves 32 bytes of Flash
+  memory (.text).
+
+## [v0.3.4] - 2017-07-19
+
+### Changed
+
+- Align the end of .rodata to a 4-byte boundary. With this the sections that
+  will go into Flash memory will be 4 byte aligned at the start and at the
+  end. Which seems to be required (?) by Cortex-M0 devices.
+
+- .bss and .data are now padded so their sizes are multiple of 4 bytes. This
+  improves the output of `objdump`; before, the output showed "Address
+  0x20000004 is out of bounds".
+
+- Linking now aborts if any of the input files contains a .got section. Dynamic
+  relocations are not supported and Rust code is not relocatable by default.
+  This error only occurs if C code that was compiled with the -fPIC flag is
+  linked in. The error message will tell the user how to compile their C code
+  without -fPIC.
+
+## [v0.3.3] - 2017-07-14
+
+### Changed
+
+- Updated the documentation: it's no longer necessary to use the
+  compiler-builtins repository since that crate landed in rust-lang/rust and
+  it's now available in the `rust-src` component.
+
+## [v0.3.2] - 2017-07-07
+
+### Changed
+
+- Tweaked documentation
+
+## [v0.3.1] - 2017-07-07
+
+### Fixed
+
+- A warning when compiling for x86_64 and the "abort-on-panic" feature is
+  enabled.
+
+## [v0.3.0] - 2017-07-07
+
+### Added
+
+- A `default_handler!` macro to override the default exception handler.
+
+- An `exception!` macro to override the handler for a particular exception.
+
+### Changed
+
+- The FPU will now be enabled before `main` if the target has FPU support.
+
+- [breaking-change] the features "panic-over-itm" and "panic-over-semihosting"
+  has been removed. the `panic_fmt` language item is now *not* included by
+  default. An opt-in feature named "abort-on-panic" can be enabled to make this
+  crate provide a `panic_fmt` implementation that simply aborts.
+
+- [breaking-change] The sections `.rodata.{exceptions,interrupts}` have been
+  renamed to `.vector_table.{exceptions,interrupts}`. This break the old
+  mechanism for registering exceptions (`static EXCEPTIONS`); use the new ones:
+  `default_handler!` and `exception!`.
+
+- The `_stack_start` is now optional in the `memory.x` file. If unspecified its
+  value will be set to `ORIGIN(RAM) + LENGTH(RAM)`.
+
+## [v0.2.4] - 2017-06-03
+
+### Added
+
+- A non-allocatable `.stlog` section to support the [`stlog`] logging framework.
+
+[`stlog`]: https://crates.io/crates/stlog
+
+## [v0.2.3] - 2017-05-30
+
+### Added
+
+- A `_stext` symbol which can be specified in the linker script to customize the
+  location of the `.text` section. If not specified the `.text` section will be
+  placed right after the `.vector_table` section.
+
+## [v0.2.2] - 2017-05-27
+
+### Added
+
+- A `_sheap` symbol where the heap can be located.
+
+### Changed
+
+- The linker sections have renamed / reorder to make `arm-none-eabi-size -A`
+  more useful. You'll now see something like this:
+
+```
+$ arm-none-eabi-size -A hello
+hello  :
+section                size        addr
+.vector_table          1024   134217728
+.text                   288   134218752
+.rodata                  14   134219040
+```
+
+- `cortex-m-rt::reset_handler` is now the entry point of all programs that link
+  to `cortex-m-rt`. This makes GDB's `load` command work correctly. It will now
+  set the Program Counter to `reset_handler` after flashing the program so
+  there's no need to reset the microcontroller after flashing.
+
+- Renamed `__exceptions` and `__interrupts` symbols, which are only used
+  internally, to `_eexceptions` and `_einterrupts` respectively for consistency.
+
+### Fixed
+
+- Include input `.text` and `.rodata` sections (note: no suffix as in
+  `.text.foo`) in the output file. (C) Code compiled without the equivalent
+  `-ffunction-sections` / `-fdata-sections` may place stuff in those unsuffixed
+  sections.
+
+## [v0.2.1] - 2017-05-07
+
+### Fixed
+
+- Do not load the `.debug_gdb_script` section in flash. It's only needed for
+  debugging.
+
+## [v0.2.0] - 2017-04-27
+
+### Changed
+
+- [breaking-change] the `_stack_start` symbol is now required and must be
+  provided in the `memory.x` file when using the "linker-script" feature. This
+  symbol indicates where in memory the call stack will be allocated.
+
+## [v0.1.3] - 2017-04-25
+
+### Fixed
+
+- A `rustdoc` warning
+
+## [v0.1.2] - 2017-04-22
+
+### Changed
+
+- Unclutter the `reset_handler` function for a better debugging experience.
+
+## [v0.1.1] - 2017-04-15
+
+### Changed
+
+- Improved linker error messages
+
+## v0.1.0 - 2017-04-12
+
+Initial release
+
+[Unreleased]: https://github.com/rust-embedded/cortex-m/compare/c-m-rt-v0.7.5...HEAD
+[v0.7.4]: https://github.com/rust-embedded/cortex-m/compare/c-m-rt-v0.7.4...c-m-rt-v0.7.5
+[v0.7.4]: https://github.com/rust-embedded/cortex-m/compare/c-m-rt-v0.7.3...c-m-rt-v0.7.4
+[v0.7.3]: https://github.com/rust-embedded/cortex-m/compare/c-m-rt-v0.7.2...c-m-rt-v0.7.3
+[v0.7.2]: https://github.com/rust-embedded/cortex-m/compare/c-m-rt-v0.7.1...c-m-rt-v0.7.2
+[v0.7.1]: https://github.com/rust-embedded/cortex-m-rt/compare/v0.7.0...v0.7.1
+[v0.7.0]: https://github.com/rust-embedded/cortex-m-rt/compare/v0.6.11...v0.7.0
+[v0.6.15]: https://github.com/rust-embedded/cortex-m-rt/compare/v0.6.14...v0.6.15
+[v0.6.14]: https://github.com/rust-embedded/cortex-m-rt/compare/v0.6.13...v0.6.14
+[v0.6.13]: https://github.com/rust-embedded/cortex-m-rt/compare/v0.6.12...v0.6.13
+[v0.6.12]: https://github.com/rust-embedded/cortex-m-rt/compare/v0.6.11...v0.6.12
+[v0.6.11]: https://github.com/rust-embedded/cortex-m-rt/compare/v0.6.10...v0.6.11
+[v0.6.10]: https://github.com/rust-embedded/cortex-m-rt/compare/v0.6.9...v0.6.10
+[v0.6.9]: https://github.com/rust-embedded/cortex-m-rt/compare/v0.6.8...v0.6.9
+[v0.6.8]: https://github.com/rust-embedded/cortex-m-rt/compare/v0.6.7...v0.6.8
+[v0.6.7]: https://github.com/rust-embedded/cortex-m-rt/compare/v0.6.6...v0.6.7
+[v0.6.6]: https://github.com/rust-embedded/cortex-m-rt/compare/v0.6.5...v0.6.6
+[v0.6.5]: https://github.com/rust-embedded/cortex-m-rt/compare/v0.6.4...v0.6.5
+[v0.6.4]: https://github.com/rust-embedded/cortex-m-rt/compare/v0.6.3...v0.6.4
+[v0.6.3]: https://github.com/rust-embedded/cortex-m-rt/compare/v0.6.2...v0.6.3
+[v0.6.2]: https://github.com/rust-embedded/cortex-m-rt/compare/v0.6.1...v0.6.2
+[v0.6.1]: https://github.com/rust-embedded/cortex-m-rt/compare/v0.6.0...v0.6.1
+[v0.6.0]: https://github.com/rust-embedded/cortex-m-rt/compare/v0.5.3...v0.6.0
+[v0.5.3]: https://github.com/rust-embedded/cortex-m-rt/compare/v0.5.2...v0.5.3
+[v0.5.2]: https://github.com/rust-embedded/cortex-m-rt/compare/v0.5.1...v0.5.2
+[v0.5.1]: https://github.com/rust-embedded/cortex-m-rt/compare/v0.5.0...v0.5.1
+[v0.5.0]: https://github.com/rust-embedded/cortex-m-rt/compare/v0.4.0...v0.5.0
+[v0.4.0]: https://github.com/rust-embedded/cortex-m-rt/compare/v0.3.15...v0.4.0
+[v0.3.15]: https://github.com/rust-embedded/cortex-m-rt/compare/v0.3.14...v0.3.15
+[v0.3.14]: https://github.com/rust-embedded/cortex-m-rt/compare/v0.3.13...v0.3.14
+[v0.3.13]: https://github.com/rust-embedded/cortex-m-rt/compare/v0.3.12...v0.3.13
+[v0.3.12]: https://github.com/rust-embedded/cortex-m-rt/compare/v0.3.11...v0.3.12
+[v0.3.11]: https://github.com/rust-embedded/cortex-m-rt/compare/v0.3.10...v0.3.11
+[v0.3.10]: https://github.com/rust-embedded/cortex-m-rt/compare/v0.3.9...v0.3.10
+[v0.3.9]: https://github.com/rust-embedded/cortex-m-rt/compare/v0.3.8...v0.3.9
+[v0.3.8]: https://github.com/rust-embedded/cortex-m-rt/compare/v0.3.7...v0.3.8
+[v0.3.7]: https://github.com/rust-embedded/cortex-m-rt/compare/v0.3.6...v0.3.7
+[v0.3.6]: https://github.com/rust-embedded/cortex-m-rt/compare/v0.3.5...v0.3.6
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+
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+ "windows_aarch64_gnullvm 0.42.2",
+ "windows_aarch64_msvc 0.42.2",
+ "windows_i686_gnu 0.42.2",
+ "windows_i686_msvc 0.42.2",
+ "windows_x86_64_gnu 0.42.2",
+ "windows_x86_64_gnullvm 0.42.2",
+ "windows_x86_64_msvc 0.42.2",
+]
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+ "windows-targets",
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+ "windows_aarch64_msvc 0.48.5",
+ "windows_i686_gnu 0.48.5",
+ "windows_i686_msvc 0.48.5",
+ "windows_x86_64_gnu 0.48.5",
+ "windows_x86_64_gnullvm 0.48.5",
+ "windows_x86_64_msvc 0.48.5",
+]
+
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+
+[[package]]
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+source = "registry+https://github.com/rust-lang/crates.io-index"
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### external/vendor/cortex-m-rt/Cargo.toml
@@ -0,0 +1,155 @@
+# THIS FILE IS AUTOMATICALLY GENERATED BY CARGO
+#
+# When uploading crates to the registry Cargo will automatically
+# "normalize" Cargo.toml files for maximal compatibility
+# with all versions of Cargo and also rewrite `path` dependencies
+# to registry (e.g., crates.io) dependencies.
+#
+# If you are reading this file be aware that the original Cargo.toml
+# will likely look very different (and much more reasonable).
+# See Cargo.toml.orig for the original contents.
+
+[package]
+edition = "2021"
+rust-version = "1.61"
+name = "cortex-m-rt"
+version = "0.7.5"
+authors = [
+    "The Cortex-M Team <cortex-m@teams.rust-embedded.org>",
+    "Jorge Aparicio <jorge@japaric.io>",
+    "Hideki Sekine <sekineh@me.com>",
+]
+build = "build.rs"
+links = "cortex-m-rt"
+autobins = false
+autoexamples = false
+autotests = false
+autobenches = false
+description = "Minimal runtime / startup for Cortex-M microcontrollers"
+documentation = "https://docs.rs/cortex-m-rt/"
+readme = "README.md"
+keywords = [
+    "arm",
+    "cortex-m",
+    "runtime",
+    "startup",
+]
+categories = [
+    "embedded",
+    "no-std",
+]
+license = "MIT OR Apache-2.0"
+repository = "https://github.com/rust-embedded/cortex-m"
+
+[package.metadata.docs.rs]
+features = ["device"]
+
+[lib]
+name = "cortex_m_rt"
+path = "src/lib.rs"
+
+[[example]]
+name = "alignment"
+path = "examples/alignment.rs"
+
+[[example]]
+name = "cfg-static"
+path = "examples/cfg-static.rs"
+
+[[example]]
+name = "data_overflow"
+path = "examples/data_overflow.rs"
+
+[[example]]
+name = "device"
+path = "examples/device.rs"
+required-features = ["device"]
+
+[[example]]
+name = "divergent-default-handler"
+path = "examples/divergent-default-handler.rs"
+
+[[example]]
+name = "divergent-exception"
+path = "examples/divergent-exception.rs"
+
+[[example]]
+name = "entry-static"
+path = "examples/entry-static.rs"
+
+[[example]]
+name = "hard-fault-trampoline"
+path = "examples/hard-fault-trampoline.rs"
+
+[[example]]
+name = "main"
+path = "examples/main.rs"
+
+[[example]]
+name = "minimal"
+path = "examples/minimal.rs"
+
+[[example]]
+name = "override-exception"
+path = "examples/override-exception.rs"
+
+[[example]]
+name = "pre_init"
+path = "examples/pre_init.rs"
+
+[[example]]
+name = "qemu"
+path = "examples/qemu.rs"
+
+[[example]]
+name = "state"
+path = "examples/state.rs"
+
+[[example]]
+name = "unsafe-default-handler"
+path = "examples/unsafe-default-handler.rs"
+
+[[example]]
+name = "unsafe-entry"
+path = "examples/unsafe-entry.rs"
+
+[[example]]
+name = "unsafe-exception"
+path = "examples/unsafe-exception.rs"
+
+[[example]]
+name = "unsafe-hard-fault"
+path = "examples/unsafe-hard-fault.rs"
+
+[[example]]
+name = "unsafety"
+path = "examples/unsafety.rs"
+
+[[example]]
+name = "warnings"
+path = "examples/warnings.rs"
+required-features = ["device"]
+
+[[test]]
+name = "compiletest"
+path = "tests/compiletest.rs"
+required-features = ["device"]
+
+[dependencies.cortex-m-rt-macros]
+version = "=0.7.5"
+
+[dev-dependencies.cortex-m]
+version = "0.7.4"
+
+[dev-dependencies.panic-halt]
+version = "0.2.0"
+
+[features]
+device = []
+paint-stack = []
+set-sp = []
+set-vtor = []
+zero-init-ram = []
+
+[target.'cfg(not(target_os = "none"))'.dev-dependencies.compiletest_rs]
+version = "0.11"

### external/vendor/cortex-m-rt/Cargo.toml.orig
@@ -0,0 +1,52 @@
+[package]
+authors = [
+    "The Cortex-M Team <cortex-m@teams.rust-embedded.org>",
+    "Jorge Aparicio <jorge@japaric.io>",
+    "Hideki Sekine <sekineh@me.com>",
+]
+categories = ["embedded", "no-std"]
+description = "Minimal runtime / startup for Cortex-M microcontrollers"
+documentation = "https://docs.rs/cortex-m-rt/"
+keywords = ["arm", "cortex-m", "runtime", "startup"]
+license = "MIT OR Apache-2.0"
+name = "cortex-m-rt"
+readme = "README.md"
+repository = "https://github.com/rust-embedded/cortex-m"
+version = "0.7.5"
+autoexamples = true
+links = "cortex-m-rt" # Prevent multiple versions of cortex-m-rt being linked
+edition = "2021"
+rust-version = "1.61"
+
+[dependencies]
+cortex-m-rt-macros = { path = "macros", version = "=0.7.5" }
+
+[dev-dependencies]
+cortex-m = { version = "0.7.4", path = "../cortex-m" }
+panic-halt = "0.2.0"
+cortex-m-semihosting = { path = "../cortex-m-semihosting" }
+
+[target.'cfg(not(target_os = "none"))'.dev-dependencies]
+compiletest_rs = "0.11"
+
+[[example]]
+name = "device"
+required-features = ["device"]
+
+[[example]]
+name = "warnings"
+required-features = ["device"]
+
+[[test]]
+name = "compiletest"
+required-features = ["device"]
+
+[features]
+device = []
+set-sp = []
+set-vtor = []
+zero-init-ram = []
+paint-stack = []
+
+[package.metadata.docs.rs]
+features = ["device"]

### external/vendor/cortex-m-rt/README.md
@@ -0,0 +1,41 @@
+[![crates.io](https://img.shields.io/crates/v/cortex-m-rt.svg)](https://crates.io/crates/cortex-m-rt)
+[![crates.io](https://img.shields.io/crates/d/cortex-m-rt.svg)](https://crates.io/crates/cortex-m-rt)
+
+# `cortex-m-rt`
+
+> Startup code and minimal runtime for Cortex-M microcontrollers
+
+This project is developed and maintained by the [Cortex-M team][team].
+
+# [Documentation](https://docs.rs/cortex-m-rt)
+
+# Minimum Supported Rust Version (MSRV)
+
+This crate is guaranteed to compile on stable Rust 1.61.0 and up. It *might*
+compile with older versions but that may change in any new patch release.
+
+# License
+
+Licensed under either of
+
+- Apache License, Version 2.0 ([LICENSE-APACHE](LICENSE-APACHE) or
+  http://www.apache.org/licenses/LICENSE-2.0)
+
+- MIT license ([LICENSE-MIT](LICENSE-MIT) or http://opensource.org/licenses/MIT)
+
+at your option.
+
+## Contribution
+
+Unless you explicitly state otherwise, any contribution intentionally submitted
+for inclusion in the work by you, as defined in the Apache-2.0 license, shall be
+dual licensed as above, without any additional terms or conditions.
+
+## Code of Conduct
+
+Contribution to this crate is organized under the terms of the [Rust Code of
+Conduct][CoC], the maintainer of this crate, the [Cortex-M team][team], promises
+to intervene to uphold that code of conduct.
+
+[CoC]: ../CODE_OF_CONDUCT.md
+[team]: https://github.com/rust-embedded/wg#the-cortex-m-team

### external/vendor/cortex-m-rt/build.rs
@@ -0,0 +1,91 @@
+use std::fs::File;
+use std::io::Write;
+use std::path::{Path, PathBuf};
+use std::{env, ffi::OsStr};
+
+fn main() {
+    let mut target = env::var("TARGET").unwrap();
+
+    // When using a custom target JSON, `$TARGET` contains the path to that JSON file. By
+    // convention, these files are named after the actual target triple, eg.
+    // `thumbv7m-customos-elf.json`, so we extract the file stem here to allow custom target specs.
+    let path = Path::new(&target);
+    if path.extension() == Some(OsStr::new("json")) {
+        target = path
+            .file_stem()
+            .map_or(target.clone(), |stem| stem.to_str().unwrap().to_string());
+    }
+
+    // Put the linker script somewhere the linker can find it
+    let out = &PathBuf::from(env::var_os("OUT_DIR").unwrap());
+    let link_x = include_bytes!("link.x.in");
+    let mut f = if env::var_os("CARGO_FEATURE_DEVICE").is_some() {
+        let mut f = File::create(out.join("link.x")).unwrap();
+
+        f.write_all(link_x).unwrap();
+
+        // *IMPORTANT*: The weak aliases (i.e. `PROVIDED`) must come *after* `EXTERN(__INTERRUPTS)`.
+        // Otherwise the linker will ignore user defined interrupts and always populate the table
+        // with the weak aliases.
+        writeln!(
+            f,
+            r#"
+/* Provides weak aliases (cf. PROVIDED) for device specific interrupt handlers */
+/* This will usually be provided by a device crate generated using svd2rust (see `device.x`) */
+INCLUDE device.x"#
+        )
+        .unwrap();
+        f
+    } else {
+        let mut f = File::create(out.join("link.x")).unwrap();
+        f.write_all(link_x).unwrap();
+        f
+    };
+
+    println!("cargo:rustc-check-cfg=cfg(armv6m)");
+    println!("cargo:rustc-check-cfg=cfg(armv7m)");
+    println!("cargo:rustc-check-cfg=cfg(armv8m)");
+    println!("cargo:rustc-check-cfg=cfg(cortex_m)");
+    println!("cargo:rustc-check-cfg=cfg(has_fpu)");
+
+    let max_int_handlers = if target.starts_with("thumbv6m-") {
+        println!("cargo:rustc-cfg=cortex_m");
+        println!("cargo:rustc-cfg=armv6m");
+        32
+    } else if target.starts_with("thumbv7m-") || target.starts_with("thumbv7em-") {
+        println!("cargo:rustc-cfg=cortex_m");
+        println!("cargo:rustc-cfg=armv7m");
+        240
+    } else if target.starts_with("thumbv8m") {
+        println!("cargo:rustc-cfg=cortex_m");
+        println!("cargo:rustc-cfg=armv8m");
+        496
+    } else {
+        // Non ARM target. We assume you're just testing the syntax.
+        // This value seems as good as any.
+        240
+    };
+
+    if target.ends_with("-eabihf") {
+        println!("cargo:rustc-cfg=has_fpu");
+    }
+
+    // checking the size of the interrupts portion of the vector table is sub-architecture dependent
+    writeln!(
+        f,
+        r#"
+ASSERT(SIZEOF(.vector_table) <= 0x{:x}, "
+There can't be more than {1} interrupt handlers. This may be a bug in
+your device crate, or you may have registered more than {1} interrupt
+handlers.");
+"#,
+        max_int_handlers * 4 + 0x40,
+        max_int_handlers
+    )
+    .unwrap();
+
+    println!("cargo:rustc-link-search={}", out.display());
+
+    println!("cargo:rerun-if-changed=build.rs");
+    println!("cargo:rerun-if-changed=link.x.in");
+}

### external/vendor/cortex-m-rt/ci/script.sh
@@ -0,0 +1,87 @@
+#!/usr/bin/env bash
+
+set -euxo pipefail
+
+main() {
+    cargo check --target "$TARGET"
+
+    cargo check --target "$TARGET" --features device
+
+    # A `critical_section` implementation is always needed.
+    needed_features=cortex-m/critical-section-single-core
+
+    if [ "$TARGET" = x86_64-unknown-linux-gnu ] && [ "$TRAVIS_RUST_VERSION" = stable ]; then
+        ( cd macros && cargo check && cargo test )
+
+        cargo test --features "device,${needed_features}" --test compiletest
+    fi
+
+    local examples=(
+        alignment
+        divergent-default-handler
+        divergent-exception
+        entry-static
+        hard-fault-trampoline
+        main
+        minimal
+        override-exception
+        pre_init
+        qemu
+        state
+        unsafe-default-handler
+        unsafe-entry
+        unsafe-exception
+        unsafe-hard-fault
+    )
+    local fail_examples=(
+        data_overflow
+    )
+    local linkers=(
+        # Link with arm-none-eabi-ld
+        "-C linker=arm-none-eabi-ld"
+        # Link with arm-none-eabi-gcc, requires -nostartfiles
+        "-C linker=arm-none-eabi-gcc -C link-arg=-nostartfiles"
+        # Link with rust-lld (default)
+        ""
+    )
+    if [ "$TARGET" != x86_64-unknown-linux-gnu ]; then
+        # Only test on stable and nightly, not MSRV.
+        if [ "$TRAVIS_RUST_VERSION" = stable ] || [ "$TRAVIS_RUST_VERSION" = nightly ]; then
+            RUSTDOCFLAGS="-Cpanic=abort" cargo test --features "${needed_features}" --doc
+        fi
+
+        for linker in "${linkers[@]}"; do
+            for ex in "${examples[@]}"; do
+                cargo rustc --target "$TARGET" --example "$ex" --features "${needed_features}" -- $linker
+                cargo rustc --target "$TARGET" --example "$ex" --features "${needed_features}" --release -- $linker
+            done
+            for ex in "${fail_examples[@]}"; do
+                cargo rustc --target "$TARGET" --example "$ex" --features "${needed_features}" -- $linker && exit 1
+                cargo rustc --target "$TARGET" --example "$ex" --features "${needed_features}" --release -- $linker && exit 1
+            done
+            cargo rustc --target "$TARGET" --example device --features "device,${needed_features}" -- $linker
+            cargo rustc --target "$TARGET" --example device --features "device,${needed_features}" --release -- $linker
+
+            cargo rustc --target "$TARGET" --example minimal --features "set-sp,${needed_features}" -- $linker
+            cargo rustc --target "$TARGET" --example minimal --features "set-sp,${needed_features}" --release -- $linker
+            cargo rustc --target "$TARGET" --example minimal --features "zero-init-ram,${needed_features}" -- $linker
+            cargo rustc --target "$TARGET" --example minimal --features "zero-init-ram,${needed_features}" --release -- $linker
+            cargo rustc --target "$TARGET" --example minimal --features "set-vtor,${needed_features}" -- $linker
+            cargo rustc --target "$TARGET" --example minimal --features "set-vtor,${needed_features}" --release -- $linker
+        done
+    fi
+
+    case $TARGET in
+        thumbv6m-none-eabi|thumbv7m-none-eabi)
+            for linker in "${linkers[@]}"; do
+                env RUSTFLAGS="$linker -C link-arg=-Tlink.x" cargo run \
+                    --target "$TARGET" --features "${needed_features}" --example qemu | grep "x = 42"
+                env RUSTFLAGS="$linker -C link-arg=-Tlink.x" cargo run \
+                    --target "$TARGET" --features "${needed_features}" --example qemu --release | grep "x = 42"
+            done
+
+            ;;
+    esac
+}
+
+main

### external/vendor/cortex-m-rt/examples/alignment.rs
@@ -0,0 +1,33 @@
+//! This is not an example; this is a link-pass test
+
+#![deny(warnings)]
+#![no_main]
+#![no_std]
+
+extern crate cortex_m_rt as rt;
+extern crate panic_halt;
+
+use core::ptr;
+
+use rt::entry;
+
+static mut BSS1: u16 = 0;
+static mut BSS2: u8 = 0;
+static mut DATA1: u8 = 1;
+static mut DATA2: u16 = 1;
+static RODATA1: &[u8; 3] = b"012";
+static RODATA2: &[u8; 2] = b"34";
+
+#[entry]
+fn main() -> ! {
+    unsafe {
+        let _bss1 = ptr::read_volatile(ptr::addr_of!(BSS1));
+        let _bss2 = ptr::read_volatile(ptr::addr_of!(BSS2));
+        let _data1 = ptr::read_volatile(ptr::addr_of!(DATA1));
+        let _data2 = ptr::read_volatile(ptr::addr_of!(DATA2));
+        let _rodata1 = ptr::read_volatile(ptr::addr_of!(RODATA1));
+        let _rodata2 = ptr::read_volatile(ptr::addr_of!(RODATA2));
+    }
+
+    loop {}
+}

### external/vendor/cortex-m-rt/examples/cfg-static.rs
@@ -0,0 +1,27 @@
+//! using `#[cfg]` on `static` shouldn't cause compile errors
+
+#![deny(unsafe_code)]
+#![deny(warnings)]
+#![no_main]
+#![no_std]
+// This example uses an undefined cfg, `cfg(never)`
+#![allow(unexpected_cfgs)]
+
+extern crate cortex_m_rt as rt;
+extern crate panic_halt;
+
+use rt::{entry, exception};
+
+#[entry]
+fn main() -> ! {
+    #[cfg(never)]
+    static mut COUNT: u32 = 0;
+
+    loop {}
+}
+
+#[exception]
+fn SysTick() {
+    #[cfg(never)]
+    static mut FOO: u32 = 0;
+}

### external/vendor/cortex-m-rt/examples/data_overflow.rs
@@ -0,0 +1,31 @@
+//! This is not an example; this is a linker overflow detection test
+//! which should fail to link due to .data overflowing FLASH.
+
+#![deny(warnings)]
+#![no_main]
+#![no_std]
+
+extern crate cortex_m_rt as rt;
+extern crate panic_halt;
+
+use core::ptr;
+use rt::entry;
+
+// This large static array uses most of .rodata
+const RODATA_SIZE: usize = 250 * 1024;
+static RODATA: [u8; RODATA_SIZE] = [1u8; RODATA_SIZE];
+
+// This large mutable array causes .data to use the rest of FLASH
+// without also overflowing RAM.
+const DATA_SIZE: usize = 8 * 1024;
+static mut DATA: [u8; DATA_SIZE] = [1u8; DATA_SIZE];
+
+#[entry]
+fn main() -> ! {
+    unsafe {
+        let _bigdata: u8 = ptr::read_volatile(ptr::addr_of!(RODATA) as *const u8);
+        let _bigdata: u8 = ptr::read_volatile(ptr::addr_of!(DATA) as *const u8);
+    }
+
+    loop {}
+}

### external/vendor/cortex-m-rt/examples/device.rs
@@ -0,0 +1,37 @@
+//! Manually create the interrupts portion of the vector table
+
+#![deny(unsafe_code)]
+#![deny(warnings)]
+#![no_main]
+#![no_std]
+
+extern crate cortex_m_rt as rt;
+extern crate panic_halt;
+
+use rt::entry;
+
+#[entry]
+fn main() -> ! {
+    loop {}
+}
+
+// interrupts portion of the vector table
+#[repr(C)]
+pub union Vector {
+    handler: unsafe extern "C" fn(),
+    reserved: usize,
+}
+
+extern "C" {
+    fn WWDG();
+    fn PVD();
+}
+
+#[allow(unsafe_code)]
+#[link_section = ".vector_table.interrupts"]
+#[no_mangle]
+pub static __INTERRUPTS: [Vector; 3] = [
+    Vector { handler: WWDG },
+    Vector { reserved: 0 },
+    Vector { handler: PVD },
+];

### external/vendor/cortex-m-rt/examples/divergent-default-handler.rs
@@ -0,0 +1,18 @@
+#![deny(warnings)]
+#![no_main]
+#![no_std]
+
+extern crate cortex_m_rt;
+extern crate panic_halt;
+
+use cortex_m_rt::{entry, exception};
+
+#[entry]
+fn foo() -> ! {
+    loop {}
+}
+
+#[exception]
+unsafe fn DefaultHandler(_irqn: i16) -> ! {
+    loop {}
+}

### external/vendor/cortex-m-rt/examples/divergent-exception.rs
@@ -0,0 +1,18 @@
+#![deny(warnings)]
+#![no_main]
+#![no_std]
+
+extern crate cortex_m_rt;
+extern crate panic_halt;
+
+use cortex_m_rt::{entry, exception};
+
+#[entry]
+fn foo() -> ! {
+    loop {}
+}
+
+#[exception]
+fn SysTick() -> ! {
+    loop {}
+}

### external/vendor/cortex-m-rt/examples/entry-static.rs
@@ -0,0 +1,20 @@
+//! `static mut` variables local to the entry point are safe to use
+
+#![deny(unsafe_code)]
+#![deny(warnings)]
+#![no_main]
+#![no_std]
+
+extern crate cortex_m_rt as rt;
+extern crate panic_halt;
+
+use rt::entry;
+
+#[entry]
+fn main() -> ! {
+    static mut COUNT: u32 = 0;
+
+    loop {
+        *COUNT += 1;
+    }
+}

### external/vendor/cortex-m-rt/examples/hard-fault-trampoline.rs
@@ -0,0 +1,31 @@
+//! This is not an example; this is a linker test that ensures
+//! that the jump from HardFault to _HardFault doesn't exceed
+//! the 2kB limit of the branch instruction.
+
+#![deny(warnings)]
+#![no_main]
+#![no_std]
+
+extern crate cortex_m_rt;
+extern crate panic_halt;
+
+use core::arch::asm;
+use cortex_m_rt::{entry, exception, ExceptionFrame};
+
+// This defines both `HardFault` and `_HardFault`. Both should have
+// link_section attributes placing them at the end of the .text section,
+// close to each other. If one of them is missing that attribute, they
+// will end up separated by `foo`, which will make the linker fail.
+#[exception(trampoline = true)]
+unsafe fn HardFault(_ef: &ExceptionFrame) -> ! {
+    loop {}
+}
+
+#[entry]
+fn foo() -> ! {
+    unsafe {
+        // 2kB of NOP instructions to make the function artificially larger
+        asm!(".fill 1024,2,0xbf00",);
+    }
+    loop {}
+}

### external/vendor/cortex-m-rt/examples/main.rs
@@ -0,0 +1,13 @@
+//! Directly plug a `main` symbol instead of using `#[entry]`
+
+#![deny(warnings)]
+#![no_main]
+#![no_std]
+
+extern crate cortex_m_rt as rt;
+extern crate panic_halt;
+
+#[no_mangle]
+pub unsafe extern "C" fn main() -> ! {
+    loop {}
+}

### external/vendor/cortex-m-rt/examples/minimal.rs
@@ -0,0 +1,17 @@
+//! Minimal `cortex-m-rt` based program
+
+#![deny(unsafe_code)]
+#![deny(warnings)]
+#![no_main]
+#![no_std]
+
+extern crate cortex_m_rt as rt;
+extern crate panic_halt;
+
+use rt::entry;
+
+// the program entry point
+#[entry]
+fn main() -> ! {
+    loop {}
+}

### external/vendor/cortex-m-rt/examples/override-exception.rs
@@ -0,0 +1,29 @@
+//! How to override the hard fault exception handler and the default exception handler
+
+#![deny(warnings)]
+#![no_main]
+#![no_std]
+
+extern crate cortex_m;
+extern crate cortex_m_rt as rt;
+extern crate panic_halt;
+
+use cortex_m::asm;
+use rt::{entry, exception, ExceptionFrame};
+
+#[entry]
+fn main() -> ! {
+    loop {}
+}
+
+#[exception]
+unsafe fn DefaultHandler(_irqn: i16) {
+    asm::bkpt();
+}
+
+#[exception]
+unsafe fn HardFault(_ef: &ExceptionFrame) -> ! {
+    asm::bkpt();
+
+    loop {}
+}

### external/vendor/cortex-m-rt/examples/pre_init.rs
@@ -0,0 +1,20 @@
+//! `cortex-m-rt` based program with a function run before RAM is initialized.
+
+#![deny(warnings)]
+#![no_main]
+#![no_std]
+
+extern crate cortex_m_rt as rt;
+extern crate panic_halt;
+
+use rt::{entry, pre_init};
+
+#[pre_init]
+unsafe fn disable_watchdog() {
+    // Do what you need to disable the watchdog.
+}
+
+#[entry]
+fn main() -> ! {
+    loop {}
+}

### external/vendor/cortex-m-rt/examples/qemu.rs
@@ -0,0 +1,34 @@
+#![no_main]
+#![no_std]
+
+use core::{
+    fmt::Write,
+    sync::atomic::{AtomicU32, Ordering},
+};
+
+static DATA_VAL: AtomicU32 = AtomicU32::new(1234);
+
+static BSS_VAL: AtomicU32 = AtomicU32::new(0);
+
+#[cortex_m_rt::entry]
+fn main() -> ! {
+    let x = 42;
+
+    loop {
+        let mut hstdout = cortex_m_semihosting::hio::hstdout().unwrap();
+        // check that .data and .bss were initialised OK
+        if DATA_VAL.load(Ordering::Relaxed) == 1234 && BSS_VAL.load(Ordering::Relaxed) == 0 {
+            _ = writeln!(hstdout, "x = {}", x);
+        }
+        cortex_m_semihosting::debug::exit(cortex_m_semihosting::debug::EXIT_SUCCESS);
+    }
+}
+
+// Define a panic handler that uses semihosting to exit immediately,
+// so that any panics cause qemu to quit instead of hang.
+#[panic_handler]
+fn panic(_: &core::panic::PanicInfo) -> ! {
+    loop {
+        cortex_m_semihosting::debug::exit(cortex_m_semihosting::debug::EXIT_FAILURE);
+    }
+}

### external/vendor/cortex-m-rt/examples/state.rs
@@ -0,0 +1,24 @@
+//! Preserving state across executions of an exception handler
+
+#![deny(unsafe_code)]
+#![deny(warnings)]
+#![no_main]
+#![no_std]
+
+extern crate cortex_m_rt as rt;
+extern crate panic_halt;
+
+use rt::{entry, exception};
+
+#[entry]
+fn main() -> ! {
+    loop {}
+}
+
+// exception handler with state
+#[exception]
+fn SysTick() {
+    static mut STATE: u32 = 0;
+
+    *STATE += 1;
+}

### external/vendor/cortex-m-rt/examples/unsafe-default-handler.rs
@@ -0,0 +1,16 @@
+#![deny(warnings)]
+#![no_main]
+#![no_std]
+
+extern crate cortex_m_rt;
+extern crate panic_halt;
+
+use cortex_m_rt::{entry, exception};
+
+#[entry]
+fn foo() -> ! {
+    loop {}
+}
+
+#[exception]
+unsafe fn DefaultHandler(_irqn: i16) {}

### external/vendor/cortex-m-rt/examples/unsafe-entry.rs
@@ -0,0 +1,13 @@
+#![deny(warnings)]
+#![no_main]
+#![no_std]
+
+extern crate cortex_m_rt;
+extern crate panic_halt;
+
+use cortex_m_rt::entry;
+
+#[entry]
+unsafe fn foo() -> ! {
+    loop {}
+}

### external/vendor/cortex-m-rt/examples/unsafe-exception.rs
@@ -0,0 +1,16 @@
+#![deny(warnings)]
+#![no_main]
+#![no_std]
+
+extern crate cortex_m_rt;
+extern crate panic_halt;
+
+use cortex_m_rt::{entry, exception};
+
+#[entry]
+fn foo() -> ! {
+    loop {}
+}
+
+#[exception]
+unsafe fn SysTick() {}

### external/vendor/cortex-m-rt/examples/unsafe-hard-fault.rs
@@ -0,0 +1,18 @@
+#![deny(warnings)]
+#![no_main]
+#![no_std]
+
+extern crate cortex_m_rt;
+extern crate panic_halt;
+
+use cortex_m_rt::{entry, exception, ExceptionFrame};
+
+#[entry]
+fn foo() -> ! {
+    loop {}
+}
+
+#[exception]
+unsafe fn HardFault(_ef: &ExceptionFrame) -> ! {
+    loop {}
+}

### external/vendor/cortex-m-rt/examples/unsafety.rs
@@ -0,0 +1,36 @@
+//! Checks that the declared unsafety is respected by the attributes
+
+#![deny(warnings)]
+#![no_main]
+#![no_std]
+
+extern crate cortex_m_rt;
+extern crate panic_halt;
+
+use cortex_m_rt::{entry, exception, ExceptionFrame};
+
+#[entry]
+unsafe fn main() -> ! {
+    foo();
+
+    loop {}
+}
+
+#[exception]
+unsafe fn DefaultHandler(_irqn: i16) {
+    foo();
+}
+
+#[exception]
+unsafe fn HardFault(_ef: &ExceptionFrame) -> ! {
+    foo();
+
+    loop {}
+}
+
+#[exception]
+unsafe fn SysTick() {
+    foo();
+}
+
+unsafe fn foo() {}

### external/vendor/cortex-m-rt/examples/warnings.rs
@@ -0,0 +1,51 @@
+//! Tests that a crate can still build with all warnings enabled.
+//!
+//! The code generated by the `cortex-m-rt` macros might need to manually
+//! `#[allow]` some of them (even though Rust does that by default for a few
+//! warnings too).
+
+#![no_std]
+#![no_main]
+#![deny(warnings, missing_docs, rust_2018_idioms)]
+
+extern crate cortex_m_rt;
+extern crate panic_halt;
+
+use cortex_m_rt::{entry, exception, interrupt, pre_init, ExceptionFrame};
+
+#[allow(non_camel_case_types)]
+enum interrupt {
+    INT,
+}
+
+extern "C" {
+    fn INT();
+}
+
+#[repr(C)]
+union Vector {
+    #[allow(dead_code)]
+    handler: unsafe extern "C" fn(),
+}
+
+#[link_section = ".vector_table.interrupts"]
+#[no_mangle]
+#[used]
+static __INTERRUPTS: [Vector; 1] = [Vector { handler: INT }];
+
+/// Dummy interrupt.
+#[interrupt]
+fn INT() {}
+
+#[exception]
+fn HardFault(_eh: &ExceptionFrame) -> ! {
+    loop {}
+}
+
+#[entry]
+fn main() -> ! {
+    loop {}
+}
+
+#[pre_init]
+unsafe fn pre_init() {}

### external/vendor/cortex-m-rt/link.x.in
@@ -0,0 +1,279 @@
+/* # Developer notes
+
+- Symbols that start with a double underscore (__) are considered "private"
+
+- Symbols that start with a single underscore (_) are considered "semi-public"; they can be
+  overridden in a user linker script, but should not be referred from user code (e.g. `extern "C" {
+  static mut __sbss }`).
+
+- `EXTERN` forces the linker to keep a symbol in the final binary. We use this to make sure a
+  symbol is not dropped if it appears in or near the front of the linker arguments and "it's not
+  needed" by any of the preceding objects (linker arguments)
+
+- `PROVIDE` is used to provide default values that can be overridden by a user linker script
+
+- On alignment: it's important for correctness that the VMA boundaries of both .bss and .data *and*
+  the LMA of .data are all 4-byte aligned. These alignments are assumed by the RAM initialization
+  routine. There's also a second benefit: 4-byte aligned boundaries means that you won't see
+  "Address (..) is out of bounds" in the disassembly produced by `objdump`.
+*/
+
+/* Provides information about the memory layout of the device */
+/* This will be provided by the user (see `memory.x`) or by a Board Support Crate */
+INCLUDE memory.x
+
+/* # Entry point = reset vector */
+EXTERN(__RESET_VECTOR);
+EXTERN(Reset);
+ENTRY(Reset);
+
+/* # Exception vectors */
+/* This is effectively weak aliasing at the linker level */
+/* The user can override any of these aliases by defining the corresponding symbol themselves (cf.
+   the `exception!` macro) */
+EXTERN(__EXCEPTIONS); /* depends on all the these PROVIDED symbols */
+
+EXTERN(DefaultHandler);
+
+PROVIDE(NonMaskableInt = DefaultHandler);
+EXTERN(HardFaultTrampoline);
+PROVIDE(MemoryManagement = DefaultHandler);
+PROVIDE(BusFault = DefaultHandler);
+PROVIDE(UsageFault = DefaultHandler);
+PROVIDE(SecureFault = DefaultHandler);
+PROVIDE(SVCall = DefaultHandler);
+PROVIDE(DebugMonitor = DefaultHandler);
+PROVIDE(PendSV = DefaultHandler);
+PROVIDE(SysTick = DefaultHandler);
+
+PROVIDE(DefaultHandler = DefaultHandler_);
+PROVIDE(HardFault = HardFault_);
+
+/* # Interrupt vectors */
+EXTERN(__INTERRUPTS); /* `static` variable similar to `__EXCEPTIONS` */
+
+/* # Pre-initialization function */
+/* If the user overrides this using the `pre_init!` macro or by creating a `__pre_init` function,
+   then the function this points to will be called before the RAM is initialized. */
+PROVIDE(__pre_init = DefaultPreInit);
+
+/* # Sections */
+SECTIONS
+{
+  PROVIDE(_ram_start = ORIGIN(RAM));
+  PROVIDE(_ram_end = ORIGIN(RAM) + LENGTH(RAM));
+  PROVIDE(_stack_start = _ram_end);
+
+  /* ## Sections in FLASH */
+  /* ### Vector table */
+  .vector_table ORIGIN(FLASH) :
+  {
+    __vector_table = .;
+
+    /* Initial Stack Pointer (SP) value.
+     * We mask the bottom three bits to force 8-byte alignment.
+     * Despite having an assert for this later, it's possible that a separate
+     * linker script could override _stack_start after the assert is checked.
+     */
+    LONG(_stack_start & 0xFFFFFFF8);
+
+    /* Reset vector */
+    KEEP(*(.vector_table.reset_vector)); /* this is the `__RESET_VECTOR` symbol */
+
+    /* Exceptions */
+    __exceptions = .; /* start of exceptions */
+    KEEP(*(.vector_table.exceptions)); /* this is the `__EXCEPTIONS` symbol */
+    __eexceptions = .; /* end of exceptions */
+
+    /* Device specific interrupts */
+    KEEP(*(.vector_table.interrupts)); /* this is the `__INTERRUPTS` symbol */
+  } > FLASH
+
+  PROVIDE(_stext = ADDR(.vector_table) + SIZEOF(.vector_table));
+
+  /* ### .text */
+  .text _stext :
+  {
+    __stext = .;
+    *(.Reset);
+
+    *(.text .text.*);
+
+    /* The HardFaultTrampoline uses the `b` instruction to enter `HardFault`,
+       so must be placed close to it. */
+    *(.HardFaultTrampoline);
+    *(.HardFault.*);
+
+    . = ALIGN(4); /* Pad .text to the alignment to workaround overlapping load section bug in old lld */
+    __etext = .;
+  } > FLASH
+
+  /* ### .rodata */
+  .rodata : ALIGN(4)
+  {
+    . = ALIGN(4);
+    __srodata = .;
+    *(.rodata .rodata.*);
+
+    /* 4-byte align the end (VMA) of this section.
+       This is required by LLD to ensure the LMA of the following .data
+       section will have the correct alignment. */
+    . = ALIGN(4);
+    __erodata = .;
+  } > FLASH
+
+  /* ## Sections in RAM */
+  /* ### .data */
+  .data : ALIGN(4)
+  {
+    . = ALIGN(4);
+    __sdata = .;
+    *(.data .data.*);
+    . = ALIGN(4); /* 4-byte align the end (VMA) of this section */
+  } > RAM AT>FLASH
+  /* Allow sections from user `memory.x` injected using `INSERT AFTER .data` to
+   * use the .data loading mechanism by pushing __edata. Note: do not change
+   * output region or load region in those user sections! */
+  . = ALIGN(4);
+  __edata = .;
+
+  /* LMA of .data */
+  __sidata = LOADADDR(.data);
+
+  /* ### .gnu.sgstubs
+     This section contains the TrustZone-M veneers put there by the Arm GNU linker. */
+  /* Security Attribution Unit blocks must be 32 bytes aligned. */
+  /* Note that this pads the FLASH usage to 32 byte alignment. */
+  .gnu.sgstubs : ALIGN(32)
+  {
+    . = ALIGN(32);
+    __veneer_base = .;
+    *(.gnu.sgstubs*)
+    . = ALIGN(32);
+  } > FLASH
+  /* Place `__veneer_limit` outside the `.gnu.sgstubs` section because veneers are
+   * always inserted last in the section, which would otherwise be _after_ the `__veneer_limit` symbol.
+   */
+  . = ALIGN(32);
+  __veneer_limit = .;
+
+  /* ### .bss */
+  .bss (NOLOAD) : ALIGN(4)
+  {
+    . = ALIGN(4);
+    __sbss = .;
+    *(.bss .bss.*);
+    *(COMMON); /* Uninitialized C statics */
+    . = ALIGN(4); /* 4-byte align the end (VMA) of this section */
+  } > RAM
+  /* Allow sections from user `memory.x` injected using `INSERT AFTER .bss` to
+   * use the .bss zeroing mechanism by pushing __ebss. Note: do not change
+   * output region or load region in those user sections! */
+  . = ALIGN(4);
+  __ebss = .;
+
+  /* ### .uninit */
+  .uninit (NOLOAD) : ALIGN(4)
+  {
+    . = ALIGN(4);
+    __suninit = .;
+    *(.uninit .uninit.*);
+    . = ALIGN(4);
+    __euninit = .;
+  } > RAM
+
+  /* Place the heap right after `.uninit` in RAM */
+  PROVIDE(__sheap = __euninit);
+
+  /* Place stack end at the end of allocated RAM */
+  PROVIDE(_stack_end = __euninit);
+
+  /* ## .got */
+  /* Dynamic relocations are unsupported. This section is only used to detect relocatable code in
+     the input files and raise an error if relocatable code is found */
+  .got (NOLOAD) :
+  {
+    KEEP(*(.got .got.*));
+  }
+
+  /* ## Discarded sections */
+  /DISCARD/ :
+  {
+    /* Unused exception related info that only wastes space */
+    *(.ARM.exidx);
+    *(.ARM.exidx.*);
+    *(.ARM.extab.*);
+  }
+}
+
+/* Do not exceed this mark in the error messages below                                    | */
+/* # Alignment checks */
+ASSERT(ORIGIN(FLASH) % 4 == 0, "
+ERROR(cortex-m-rt): the start of the FLASH region must be 4-byte aligned");
+
+ASSERT(ORIGIN(RAM) % 4 == 0, "
+ERROR(cortex-m-rt): the start of the RAM region must be 4-byte aligned");
+
+ASSERT(__sdata % 4 == 0 && __edata % 4 == 0, "
+BUG(cortex-m-rt): .data is not 4-byte aligned");
+
+ASSERT(__sidata % 4 == 0, "
+BUG(cortex-m-rt): the LMA of .data is not 4-byte aligned");
+
+ASSERT(__sbss % 4 == 0 && __ebss % 4 == 0, "
+BUG(cortex-m-rt): .bss is not 4-byte aligned");
+
+ASSERT(__sheap % 4 == 0, "
+BUG(cortex-m-rt): start of .heap is not 4-byte aligned");
+
+ASSERT(_stack_start % 8 == 0, "
+ERROR(cortex-m-rt): stack start address is not 8-byte aligned.
+If you have set _stack_start, check it's set to an address which is a multiple of 8 bytes.
+If you haven't, stack starts at the end of RAM by default. Check that both RAM
+origin and length are set to multiples of 8 in the `memory.x` file.");
+
+ASSERT(_stack_end % 4 == 0, "
+ERROR(cortex-m-rt): end of stack is not 4-byte aligned");
+
+ASSERT(_stack_start >= _stack_end, "
+ERROR(cortex-m-rt): stack end address is not below stack start.");
+
+/* # Position checks */
+
+/* ## .vector_table
+ *
+ * If the *start* of exception vectors is not 8 bytes past the start of the
+ * vector table, then we somehow did not place the reset vector, which should
+ * live 4 bytes past the start of the vector table.
+ */
+ASSERT(__exceptions == ADDR(.vector_table) + 0x8, "
+BUG(cortex-m-rt): the reset vector is missing");
+
+ASSERT(__eexceptions == ADDR(.vector_table) + 0x40, "
+BUG(cortex-m-rt): the exception vectors are missing");
+
+ASSERT(SIZEOF(.vector_table) > 0x40, "
+ERROR(cortex-m-rt): The interrupt vectors are missing.
+Possible solutions, from most likely to less likely:
+- Link to a svd2rust generated device crate
+- Check that you actually use the device/hal/bsp crate in your code
+- Disable the 'device' feature of cortex-m-rt to build a generic application (a dependency
+may be enabling it)
+- Supply the interrupt handlers yourself. Check the documentation for details.");
+
+/* ## .text */
+ASSERT(ADDR(.vector_table) + SIZEOF(.vector_table) <= _stext, "
+ERROR(cortex-m-rt): The .text section can't be placed inside the .vector_table section
+Set _stext to an address greater than the end of .vector_table (See output of `nm`)");
+
+ASSERT(_stext > ORIGIN(FLASH) && _stext < ORIGIN(FLASH) + LENGTH(FLASH), "
+ERROR(cortex-m-rt): The .text section must be placed inside the FLASH memory.
+Set _stext to an address within the FLASH region.");
+
+/* # Other checks */
+ASSERT(SIZEOF(.got) == 0, "
+ERROR(cortex-m-rt): .got section detected in the input object files
+Dynamic relocations are not supported. If you are linking to C code compiled using
+the 'cc' crate then modify your build script to compile the C code _without_
+the -fPIC flag. See the documentation of the `cc::Build.pic` method for details.");
+/* Do not exceed this mark in the error messages above                                    | */

### external/vendor/cortex-m-rt/src/lib.rs
@@ -0,0 +1,1282 @@
+//! Startup code and minimal runtime for Cortex-M microcontrollers
+//!
+//! This crate contains all the required parts to build a `no_std` application (binary crate) that
+//! targets a Cortex-M microcontroller.
+//!
+//! # Features
+//!
+//! This crates takes care of:
+//!
+//! - The memory layout of the program. In particular, it populates the vector table so the device
+//!   can boot correctly, and properly dispatch exceptions and interrupts.
+//!
+//! - Initializing `static` variables before the program entry point.
+//!
+//! - Enabling the FPU before the program entry point if the target is `-eabihf`.
+//!
+//! This crate also provides the following attributes:
+//!
+//! - [`#[entry]`][attr-entry] to declare the entry point of the program
+//! - [`#[exception]`][attr-exception] to override an exception handler. If not overridden all
+//!   exception handlers default to an infinite loop.
+//!
+//! This crate also implements a related attribute called `#[interrupt]`, which allows you
+//! to define interrupt handlers. However, since which interrupts are available depends on the
+//! microcontroller in use, this attribute should be re-exported and used from a peripheral
+//! access crate (PAC).
+//!
+//! A [`#[pre_init]`][attr-pre_init] macro is also provided to run a function before RAM
+//! initialisation, but its use is deprecated as it is not defined behaviour to execute Rust
+//! code before initialisation. It is still possible to create a custom `pre_init` function
+//! using assembly.
+//!
+//! The documentation for these attributes can be found in the [Attribute Macros](#attributes)
+//! section.
+//!
+//! # Requirements
+//!
+//! ## `memory.x`
+//!
+//! This crate expects the user, or some other crate, to provide the memory layout of the target
+//! device via a linker script named `memory.x`, described in this section.  The `memory.x` file is
+//! used during linking by the `link.x` script provided by this crate. If you are using a custom
+//! linker script, you do not need a `memory.x` file.
+//!
+//! ### `MEMORY`
+//!
+//! The linker script must specify the memory available in the device as, at least, two `MEMORY`
+//! regions: one named `FLASH` and one named `RAM`. The `.text` and `.rodata` sections of the
+//! program will be placed in the `FLASH` region, whereas the `.bss` and `.data` sections, as well
+//! as the heap, will be placed in the `RAM` region.
+//!
+//! ```text
+//! /* Linker script for the STM32F103C8T6 */
+//! MEMORY
+//! {
+//!   FLASH : ORIGIN = 0x08000000, LENGTH = 64K
+//!   RAM   : ORIGIN = 0x20000000, LENGTH = 20K
+//! }
+//! ```
+//!
+//! ### `_stack_start` / `_stack_end`
+//!
+//! The `_stack_start` optional symbol can be used to indicate where the call stack of the program
+//! should be placed. If this symbol is not used then the stack will be placed at the *end* of the
+//! `RAM` region -- the stack grows downwards towards smaller address. This is generally a sensible
+//! default and most applications will not need to specify `_stack_start`. The same goes for
+//! `_stack_end` which is automatically placed after the end of statically allocated RAM.
+//!
+//! **NOTE:** If you change `_stack_start`, make sure to also set `_stack_end` correctly to match
+//! new stack area if you are using it, e.g for MSPLIM. The `_stack_end` is not used internally by
+//! `cortex-m-rt` and is only for application use.
+//!
+//! For Cortex-M, the `_stack_start` must always be aligned to 8 bytes, which is enforced by
+//! the linker script. If you override it, ensure that whatever value you set is a multiple
+//! of 8 bytes. The `_stack_end` is aligned to 4 bytes.
+//!
+//! This symbol can be used to place the stack in a different memory region, for example:
+//!
+//! ```text
+//! /* Linker script for the STM32F303VCT6 with stack in CCM */
+//! MEMORY
+//! {
+//!     FLASH : ORIGIN = 0x08000000, LENGTH = 256K
+//!
+//!     /* .bss, .data and the heap go in this region */
+//!     RAM   : ORIGIN = 0x20000000, LENGTH = 40K
+//!
+//!     /* Core coupled (faster) RAM dedicated to hold the stack */
+//!     CCRAM : ORIGIN = 0x10000000, LENGTH = 8K
+//! }
+//!
+//! _stack_start = ORIGIN(CCRAM) + LENGTH(CCRAM);
+//! _stack_end = ORIGIN(CCRAM); /* Optional, add if used by the application */
+//! ```
+//!
+//! ### `_stext`
+//!
+//! This optional symbol can be used to control where the `.text` section is placed. If omitted the
+//! `.text` section will be placed right after the vector table, which is placed at the beginning of
+//! `FLASH`. Some devices store settings like Flash configuration right after the vector table;
+//! for these devices one must place the `.text` section after this configuration section --
+//! `_stext` can be used for this purpose.
+//!
+//! ```text
+//! MEMORY
+//! {
+//!   /* .. */
+//! }
+//!
+//! /* The device stores Flash configuration in 0x400-0x40C so we place .text after that */
+//! _stext = ORIGIN(FLASH) + 0x40C
+//! ```
+//!
+//! # An example
+//!
+//! This section presents a minimal application built on top of `cortex-m-rt`. Apart from the
+//! mandatory `memory.x` linker script describing the memory layout of the device, the hard fault
+//! handler and the default exception handler must also be defined somewhere in the dependency
+//! graph (see [`#[exception]`]). In this example we define them in the binary crate:
+//!
+//! ```no_run
+//! #![no_main]
+//! #![no_std]
+//!
+//! // Some panic handler needs to be included. This one halts the processor on panic.
+//! use panic_halt as _;
+//!
+//! use cortex_m_rt::entry;
+//!
+//! // Use `main` as the entry point of this application, which may not return.
+//! #[entry]
+//! fn main() -> ! {
+//!     // initialization
+//!
+//!     loop {
+//!         // application logic
+//!     }
+//! }
+//! ```
+//!
+//! To actually build this program you need to place a `memory.x` linker script somewhere the linker
+//! can find it, e.g. in the current directory; and then link the program using `cortex-m-rt`'s
+//! linker script: `link.x`. The required steps are shown below:
+//!
+//! ```text
+//! $ cat > memory.x <<EOF
+//! MEMORY
+//! {
+//!   FLASH : ORIGIN = 0x08000000, LENGTH = 64K
+//!   RAM : ORIGIN = 0x20000000, LENGTH = 20K
+//! }
+//! EOF
+//!
+//! $ cargo rustc --target thumbv7m-none-eabi -- -C link-arg=-nostartfiles -C link-arg=-Tlink.x
+//!
+//! $ file target/thumbv7m-none-eabi/debug/app
+//! app: ELF 32-bit LSB executable, ARM, EABI5 version 1 (SYSV), statically linked, (..)
+//! ```
+//!
+//! # Optional features
+//!
+//! ## `device`
+//!
+//! If this feature is disabled then this crate populates the whole vector table. All the interrupts
+//! in the vector table, even the ones unused by the target device, will be bound to the default
+//! exception handler. This makes the final application device agnostic: you will be able to run it
+//! on any Cortex-M device -- provided that you correctly specified its memory layout in `memory.x`
+//! -- without hitting undefined behavior.
+//!
+//! If this feature is enabled then the interrupts section of the vector table is left unpopulated
+//! and some other crate, or the user, will have to populate it. This mode is meant to be used in
+//! conjunction with crates generated using `svd2rust`. Those peripheral access crates, or PACs,
+//! will populate the missing part of the vector table when their `"rt"` feature is enabled.
+//!
+//! ## `set-sp`
+//!
+//! If this feature is enabled, the stack pointer (SP) is initialised in the reset handler to the
+//! `_stack_start` value from the linker script. This is not usually required, but some debuggers
+//! do not initialise SP when performing a soft reset, which can lead to stack corruption.
+//!
+//! ## `set-vtor`
+//!
+//! If this feature is enabled, the vector table offset register (VTOR) is initialised in the reset
+//! handler to the start of the vector table defined in the linker script. This is not usually
+//! required, but some bootloaders do not set VTOR before jumping to application code, leading to
+//! your main function executing but interrupt handlers not being used.
+//!
+//! ## `zero-init-ram`
+//!
+//! If this feature is enabled, RAM is initialized with zeros during startup from the `_ram_start`
+//! value to the `_ram_end` value from the linker script. This is not usually required, but might be
+//! necessary to properly initialize memory integrity measures on some hardware.
+//!
+//! ## `paint-stack`
+//!
+//! Everywhere between `__sheap` and `_stack_start` is painted with the fixed value
+//! `STACK_PAINT_VALUE`, which is `0xCCCC_CCCC`.
+//! You can then inspect memory during debugging to determine how much of the stack has been used -
+//! where the stack has been used the 'paint' will have been 'scrubbed off' and the memory will
+//! have a value other than `STACK_PAINT_VALUE`.
+//!
+//! # Inspection
+//!
+//! This section covers how to inspect a binary that builds on top of `cortex-m-rt`.
+//!
+//! ## Sections (`size`)
+//!
+//! `cortex-m-rt` uses standard sections like `.text`, `.rodata`, `.bss` and `.data` as one would
+//! expect. `cortex-m-rt` separates the vector table in its own section, named `.vector_table`. This
+//! lets you distinguish how much space is taking the vector table in Flash vs how much is being
+//! used by actual instructions (`.text`) and constants (`.rodata`).
+//!
+//! ```text
+//! $ size -Ax target/thumbv7m-none-eabi/examples/app
+//! target/thumbv7m-none-eabi/release/examples/app  :
+//! section             size         addr
+//! .vector_table      0x400    0x8000000
+//! .text               0x88    0x8000400
+//! .rodata              0x0    0x8000488
+//! .data                0x0   0x20000000
+//! .bss                 0x0   0x20000000
+//! ```
+//!
+//! Without the `-A` argument `size` reports the sum of the sizes of `.text`, `.rodata` and
+//! `.vector_table` under "text".
+//!
+//! ```text
+//! $ size target/thumbv7m-none-eabi/examples/app
+//!   text    data     bss     dec     hex filename
+//!   1160       0       0    1660     67c target/thumbv7m-none-eabi/release/app
+//! ```
+//!
+//! ## Symbols (`objdump`, `nm`)
+//!
+//! One will always find the following (unmangled) symbols in `cortex-m-rt` applications:
+//!
+//! - `Reset`. This is the reset handler. The microcontroller will execute this function upon
+//!   booting. This function will call the user program entry point (cf. [`#[entry]`][attr-entry])
+//!   using the `main` symbol so you will also find that symbol in your program.
+//!
+//! - `DefaultHandler`. This is the default handler. If not overridden using `#[exception] fn
+//!   DefaultHandler(..` this will be an infinite loop.
+//!
+//! - `HardFault` and `_HardFault`. These function handle the hard fault handling and what they
+//!   do depends on whether the hard fault is overridden and whether the trampoline is enabled (which it is by default).
+//!   - No override: Both are the same function. The function is an infinite loop defined in the cortex-m-rt crate.
+//!   - Trampoline enabled: `HardFault` is the real hard fault handler defined in assembly. This function is simply a
+//!     trampoline that jumps into the rust defined `_HardFault` function. This second function jumps to the user-defined
+//!     handler with the exception frame as parameter. This second jump is usually optimised away with inlining.
+//!   - Trampoline disabled: `HardFault` is the user defined function. This means the user function is called directly
+//!     from the vector table. `_HardFault` still exists, but is an empty function that is purely there for compiler
+//!     diagnostics.
+//!
+//! - `__STACK_START`. This is the first entry in the `.vector_table` section. This symbol contains
+//!   the initial value of the stack pointer; this is where the stack will be located -- the stack
+//!   grows downwards towards smaller addresses.
+//!
+//! - `__RESET_VECTOR`. This is the reset vector, a pointer to the `Reset` function. This vector
+//!   is located in the `.vector_table` section after `__STACK_START`.
+//!
+//! - `__EXCEPTIONS`. This is the core exceptions portion of the vector table; it's an array of 14
+//!   exception vectors, which includes exceptions like `HardFault` and `SysTick`. This array is
+//!   located after `__RESET_VECTOR` in the `.vector_table` section.
+//!
+//! - `__INTERRUPTS`. This is the device specific interrupt portion of the vector table; its exact
+//!   size depends on the target device but if the `"device"` feature has not been enabled it will
+//!   have a size of 32 vectors (on ARMv6-M), 240 vectors (on ARMv7-M) or 496 vectors (on ARMv8-M).
+//!   This array is located after `__EXCEPTIONS` in the `.vector_table` section.
+//!
+//! - `__pre_init`. This is a function to be run before RAM is initialized. It defaults to an empty
+//!   function. As this runs before RAM is initialised, it is not sound to use a Rust function for
+//!   `pre_init`, and instead it should typically be written in assembly using `global_asm` or an
+//!   external assembly file.
+//!
+//! If you override any exception handler you'll find it as an unmangled symbol, e.g. `SysTick` or
+//! `SVCall`, in the output of `objdump`,
+//!
+//! # Advanced usage
+//!
+//! ## Custom linker script
+//!
+//! To use your own linker script, ensure it is placed in the linker search path (for example in
+//! the crate root or in Cargo's `OUT_DIR`) and use it with `-C link-arg=-Tmy_script.ld` instead
+//! of the normal `-C link-arg=-Tlink.x`. The provided `link.x` may be used as a starting point
+//! for customisation.
+//!
+//! ## Setting the program entry point
+//!
+//! This section describes how [`#[entry]`][attr-entry] is implemented. This information is useful
+//! to developers who want to provide an alternative to [`#[entry]`][attr-entry] that provides extra
+//! guarantees.
+//!
+//! The `Reset` handler will call a symbol named `main` (unmangled) *after* initializing `.bss` and
+//! `.data`, and enabling the FPU (if the target has an FPU). A function with the `entry` attribute
+//! will be set to have the export name "`main`"; in addition, its mutable statics are turned into
+//! safe mutable references (see [`#[entry]`][attr-entry] for details).
+//!
+//! The unmangled `main` symbol must have signature `extern "C" fn() -> !` or its invocation from
+//! `Reset`  will result in undefined behavior.
+//!
+//! ## Incorporating device specific interrupts
+//!
+//! This section covers how an external crate can insert device specific interrupt handlers into the
+//! vector table. Most users don't need to concern themselves with these details, but if you are
+//! interested in how PACs generated using `svd2rust` integrate with `cortex-m-rt` read on.
+//!
+//! The information in this section applies when the `"device"` feature has been enabled.
+//!
+//! ### `__INTERRUPTS`
+//!
+//! The external crate must provide the interrupts portion of the vector table via a `static`
+//! variable named`__INTERRUPTS` (unmangled) that must be placed in the `.vector_table.interrupts`
+//! section of its object file.
+//!
+//! This `static` variable will be placed at `ORIGIN(FLASH) + 0x40`. This address corresponds to the
+//! spot where IRQ0 (IRQ number 0) is located.
+//!
+//! To conform to the Cortex-M ABI `__INTERRUPTS` must be an array of function pointers; some spots
+//! in this array may need to be set to 0 if they are marked as *reserved* in the data sheet /
+//! reference manual. We recommend using a `union` to set the reserved spots to `0`; `None`
+//! (`Option<fn()>`) may also work but it's not guaranteed that the `None` variant will *always* be
+//! represented by the value `0`.
+//!
+//! Let's illustrate with an artificial example where a device only has two interrupt: `Foo`, with
+//! IRQ number = 2, and `Bar`, with IRQ number = 4.
+//!
+//! ```no_run
+//! pub union Vector {
+//!     handler: unsafe extern "C" fn(),
+//!     reserved: usize,
+//! }
+//!
+//! extern "C" {
+//!     fn Foo();
+//!     fn Bar();
+//! }
+//!
+//! #[link_section = ".vector_table.interrupts"]
+//! #[no_mangle]
+//! pub static __INTERRUPTS: [Vector; 5] = [
+//!     // 0-1: Reserved
+//!     Vector { reserved: 0 },
+//!     Vector { reserved: 0 },
+//!
+//!     // 2: Foo
+//!     Vector { handler: Foo },
+//!
+//!     // 3: Reserved
+//!     Vector { reserved: 0 },
+//!
+//!     // 4: Bar
+//!     Vector { handler: Bar },
+//! ];
+//! ```
+//!
+//! ### `device.x`
+//!
+//! Linking in `__INTERRUPTS` creates a bunch of undefined references. If the user doesn't set a
+//! handler for *all* the device specific interrupts then linking will fail with `"undefined
+//! reference"` errors.
+//!
+//! We want to provide a default handler for all the interrupts while still letting the user
+//! individually override each interrupt handler. In C projects, this is usually accomplished using
+//! weak aliases declared in external assembly files. We use a similar solution via the `PROVIDE`
+//! command in the linker script: when the `"device"` feature is enabled, `cortex-m-rt`'s linker
+//! script (`link.x`) includes a linker script named `device.x`, which must be provided by
+//! whichever crate provides `__INTERRUPTS`.
+//!
+//! For our running example the `device.x` linker script looks like this:
+//!
+//! ```text
+//! /* device.x */
+//! PROVIDE(Foo = DefaultHandler);
+//! PROVIDE(Bar = DefaultHandler);
+//! ```
+//!
+//! This weakly aliases both `Foo` and `Bar`. `DefaultHandler` is the default exception handler and
+//! that the core exceptions use unless overridden.
+//!
+//! Because this linker script is provided by a dependency of the final application the dependency
+//! must contain a build script that puts `device.x` somewhere the linker can find. An example of
+//! such build script is shown below:
+//!
+//! ```ignore
+//! use std::env;
+//! use std::fs::File;
+//! use std::io::Write;
+//! use std::path::PathBuf;
+//!
+//! fn main() {
+//!     // Put the linker script somewhere the linker can find it
+//!     let out = &PathBuf::from(env::var_os("OUT_DIR").unwrap());
+//!     File::create(out.join("device.x"))
+//!         .unwrap()
+//!         .write_all(include_bytes!("device.x"))
+//!         .unwrap();
+//!     println!("cargo:rustc-link-search={}", out.display());
+//! }
+//! ```
+//!
+//! ## Uninitialized static variables
+//!
+//! The `.uninit` linker section can be used to leave `static mut` variables uninitialized. One use
+//! case of unitialized static variables is to avoid zeroing large statically allocated buffers (say
+//! to be used as thread stacks) -- this can considerably reduce initialization time on devices that
+//! operate at low frequencies.
+//!
+//! The only correct way to use this section is with [`MaybeUninit`] types.
+//!
+//! [`MaybeUninit`]: https://doc.rust-lang.org/core/mem/union.MaybeUninit.html
+//!
+//! ```no_run,edition2018
+//! # extern crate core;
+//! use core::mem::MaybeUninit;
+//!
+//! const STACK_SIZE: usize = 8 * 1024;
+//! const NTHREADS: usize = 4;
+//!
+//! #[link_section = ".uninit.STACKS"]
+//! static mut STACKS: MaybeUninit<[[u8; STACK_SIZE]; NTHREADS]> = MaybeUninit::uninit();
+//! ```
+//!
+//! Be very careful with the `link_section` attribute because it's easy to misuse in ways that cause
+//! undefined behavior.
+//!
+//! ## Extra Sections
+//!
+//! Some microcontrollers provide additional memory regions beyond RAM and FLASH. For example,
+//! some STM32 devices provide "CCM" or core-coupled RAM that is only accessible from the core. In
+//! order to place variables in these sections using [`link_section`] attributes from your code,
+//! you need to modify `memory.x` to declare the additional sections:
+//!
+//! [`link_section`]: https://doc.rust-lang.org/reference/abi.html#the-link_section-attribute
+//!
+//! ```text
+//! MEMORY
+//! {
+//!     FLASH  (rx) : ORIGIN = 0x08000000, LENGTH = 1024K
+//!     RAM    (rw) : ORIGIN = 0x20000000, LENGTH = 128K
+//!     CCMRAM (rw) : ORIGIN = 0x10000000, LENGTH = 64K
+//! }
+//!
+//! SECTIONS
+//! {
+//!     .ccmram (NOLOAD) : ALIGN(4)
+//!     {
+//!         *(.ccmram .ccmram.*);
+//!         . = ALIGN(4);
+//!     } > CCMRAM
+//! }
+//! ```
+//!
+//! You can then use something like this to place a variable into this specific section of memory:
+//!
+//! ```no_run,edition2018
+//! # extern crate core;
+//! # use core::mem::MaybeUninit;
+//! #[link_section=".ccmram.BUFFERS"]
+//! static mut BUF: MaybeUninit<[u8; 1024]> = MaybeUninit::uninit();
+//! ```
+//!
+//! However, note that these sections are not initialised by cortex-m-rt, and so must be used
+//! either with `MaybeUninit` types or you must otherwise arrange for them to be initialised
+//! yourself, such as in `pre_init`.
+//!
+//! [attr-entry]: attr.entry.html
+//! [attr-exception]: attr.exception.html
+//! [attr-pre_init]: attr.pre_init.html
+//!
+//! # Minimum Supported Rust Version (MSRV)
+//!
+//! The MSRV of this release is Rust 1.61.0.
+
+// # Developer notes
+//
+// - `link_section` is used to place symbols in specific places of the final binary. The names used
+// here will appear in the linker script (`link.x`) in conjunction with the `KEEP` command.
+
+#![deny(missing_docs)]
+#![no_std]
+
+extern crate cortex_m_rt_macros as macros;
+
+/// The 32-bit value the stack is painted with before the program runs.
+// Note: keep this value in-sync with the start-up assembly code, as we can't
+// use const values in `global_asm!` yet.
+#[cfg(feature = "paint-stack")]
+pub const STACK_PAINT_VALUE: u32 = 0xcccc_cccc;
+
+#[cfg(cortex_m)]
+use core::arch::global_asm;
+use core::fmt;
+
+/// Parse cfg attributes inside a global_asm call.
+#[cfg(cortex_m)]
+macro_rules! cfg_global_asm {
+    {@inner, [$($x:tt)*], } => {
+        global_asm!{$($x)*}
+    };
+    (@inner, [$($x:tt)*], #[cfg($meta:meta)] $asm:literal, $($rest:tt)*) => {
+        #[cfg($meta)]
+        cfg_global_asm!{@inner, [$($x)* $asm,], $($rest)*}
+        #[cfg(not($meta))]
+        cfg_global_asm!{@inner, [$($x)*], $($rest)*}
+    };
+    {@inner, [$($x:tt)*], $asm:literal, $($rest:tt)*} => {
+        cfg_global_asm!{@inner, [$($x)* $asm,], $($rest)*}
+    };
+    {$($asms:tt)*} => {
+        cfg_global_asm!{@inner, [], $($asms)*}
+    };
+}
+
+// This reset vector is the initial entry point after a system reset.
+// Calls an optional user-provided __pre_init and then initialises RAM.
+// If the target has an FPU, it is enabled.
+// Finally jumps to the user main function.
+#[cfg(cortex_m)]
+cfg_global_asm! {
+    ".cfi_sections .debug_frame
+     .section .Reset, \"ax\"
+     .global Reset
+     .type Reset,%function
+     .thumb_func",
+    ".cfi_startproc
+     Reset:",
+
+    // If enabled, initialise the SP. This is normally initialised by the CPU itself or by a
+    // bootloader, but some debuggers fail to set it when resetting the target, leading to
+    // stack corruptions.
+    #[cfg(feature = "set-sp")]
+    "ldr r0, =_stack_start
+     msr msp, r0",
+
+    // If enabled, initialise VTOR to the start of the vector table. This is normally initialised
+    // by a bootloader when the non-reset value is required, but some bootloaders do not set it,
+    // leading to frustrating issues where everything seems to work but interrupts are never
+    // handled. The VTOR register is optional on ARMv6-M, but when not present is RAZ,WI and
+    // therefore safe to write to.
+    #[cfg(feature = "set-vtor")]
+    "ldr r0, =0xe000ed08
+     ldr r1, =__vector_table
+     str r1, [r0]",
+
+    // Run user pre-init code which must be executed immediately after startup, before the
+    // potentially time-consuming memory initialisation takes place.
+    // Example use cases include disabling default watchdogs or enabling RAM.
+    "bl __pre_init",
+
+    // If enabled, initialize RAM with zeros. This is not usually required, but might be necessary
+    // to properly initialize checksum-based memory integrity measures on safety-critical hardware.
+    #[cfg(feature = "zero-init-ram")]
+    "ldr r0, =_ram_start
+     ldr r1, =_ram_end
+     movs r2, #0
+     0:
+     cmp r1, r0
+     beq 1f
+     stm r0!, {{r2}}
+     b 0b
+     1:",
+
+    // Initialise .bss memory. `__sbss` and `__ebss` come from the linker script.
+    #[cfg(not(feature = "zero-init-ram"))]
+    "ldr r0, =__sbss
+     ldr r1, =__ebss
+     movs r2, #0
+     0:
+     cmp r1, r0
+     beq 1f
+     stm r0!, {{r2}}
+     b 0b
+     1:",
+
+    // If enabled, paint stack/heap RAM with 0xcccccccc.
+    // `__sheap` and `_stack_start` come from the linker script.
+    #[cfg(feature = "paint-stack")]
+    "ldr r0, =__sheap
+     ldr r1, =_stack_start
+     ldr r2, =0xcccccccc // This must match STACK_PAINT_VALUE
+     0:
+     cmp r1, r0
+     beq 1f
+     stm r0!, {{r2}}
+     b 0b
+     1:",
+
+    // Initialise .data memory. `__sdata`, `__sidata`, and `__edata` come from the linker script.
+    "ldr r0, =__sdata
+     ldr r1, =__edata
+     ldr r2, =__sidata
+     0:
+     cmp r1, r0
+     beq 1f
+     ldm r2!, {{r3}}
+     stm r0!, {{r3}}
+     b 0b
+     1:",
+
+    // Potentially enable an FPU.
+    // SCB.CPACR is 0xE000_ED88.
+    // We enable access to CP10 and CP11 from priviliged and unprivileged mode.
+    #[cfg(has_fpu)]
+    "ldr r0, =0xE000ED88
+     ldr r1, =(0b1111 << 20)
+     ldr r2, [r0]
+     orr r2, r2, r1
+     str r2, [r0]
+     dsb
+     isb",
+
+    // Jump to user main function.
+    // `bl` is used for the extended range, but the user main function should not return,
+    // so trap on any unexpected return.
+    "bl main
+     udf #0",
+
+    ".cfi_endproc
+     .size Reset, . - Reset",
+}
+
+/// Attribute to declare an interrupt (AKA device-specific exception) handler
+///
+/// **NOTE**: This attribute is exposed by `cortex-m-rt` only when the `device` feature is enabled.
+/// However, that export is not meant to be used directly -- using it will result in a compilation
+/// error. You should instead use the PAC (usually generated using `svd2rust`) re-export of
+/// that attribute. You need to use the re-export to have the compiler check that the interrupt
+/// exists on the target device.
+///
+/// # Syntax
+///
+/// ``` ignore
+/// extern crate device;
+///
+/// // the attribute comes from the PAC not from cortex-m-rt
+/// use device::interrupt;
+///
+/// #[interrupt]
+/// fn USART1() {
+///     // ..
+/// }
+/// ```
+///
+/// where the name of the function must be one of the device interrupts.
+///
+/// # Usage
+///
+/// `#[interrupt] fn Name(..` overrides the default handler for the interrupt with the given `Name`.
+/// These handlers must have signature `[unsafe] fn() [-> !]`. It's possible to add state to these
+/// handlers by declaring `static mut` variables at the beginning of the body of the function. These
+/// variables will be safe to access from the function body.
+///
+/// If the interrupt handler has not been overridden it will be dispatched by the default exception
+/// handler (`DefaultHandler`).
+///
+/// # Properties
+///
+/// Interrupts handlers can only be called by the hardware. Other parts of the program can't refer
+/// to the interrupt handlers, much less invoke them as if they were functions.
+///
+/// `static mut` variables declared within an interrupt handler are safe to access and can be used
+/// to preserve state across invocations of the handler. The compiler can't prove this is safe so
+/// the attribute will help by making a transformation to the source code: for this reason a
+/// variable like `static mut FOO: u32` will become `let FOO: &mut u32;`.
+///
+/// # Examples
+///
+/// - Using state within an interrupt handler
+///
+/// ``` ignore
+/// extern crate device;
+///
+/// use device::interrupt;
+///
+/// #[interrupt]
+/// fn TIM2() {
+///     static mut COUNT: i32 = 0;
+///
+///     // `COUNT` is safe to access and has type `&mut i32`
+///     *COUNT += 1;
+///
+///     println!("{}", COUNT);
+/// }
+/// ```
+#[cfg(feature = "device")]
+pub use macros::interrupt;
+
+/// Attribute to declare the entry point of the program
+///
+/// The specified function will be called by the reset handler *after* RAM has been initialized. In
+/// the case of the `thumbv7em-none-eabihf` target the FPU will also be enabled before the function
+/// is called.
+///
+/// The type of the specified function must be `[unsafe] fn() -> !` (never ending function)
+///
+/// # Properties
+///
+/// The entry point will be called by the reset handler. The program can't reference to the entry
+/// point, much less invoke it.
+///
+/// `static mut` variables declared within the entry point are safe to access. The compiler can't
+/// prove this is safe so the attribute will help by making a transformation to the source code: for
+/// this reason a variable like `static mut FOO: u32` will become `let FOO: &'static mut u32;`. Note
+/// that `&'static mut` references have move semantics.
+///
+/// # Examples
+///
+/// - Simple entry point
+///
+/// ``` no_run
+/// # #![no_main]
+/// # use cortex_m_rt::entry;
+/// #[entry]
+/// fn main() -> ! {
+///     loop {
+///         /* .. */
+///     }
+/// }
+/// ```
+///
+/// - `static mut` variables local to the entry point are safe to modify.
+///
+/// ``` no_run
+/// # #![no_main]
+/// # use cortex_m_rt::entry;
+/// #[entry]
+/// fn main() -> ! {
+///     static mut FOO: u32 = 0;
+///
+///     let foo: &'static mut u32 = FOO;
+///     assert_eq!(*foo, 0);
+///     *foo = 1;
+///     assert_eq!(*foo, 1);
+///
+///     loop {
+///         /* .. */
+///     }
+/// }
+/// ```
+pub use macros::entry;
+
+/// Attribute to declare an exception handler
+///
+/// # Syntax
+///
+/// ```
+/// # use cortex_m_rt::exception;
+/// #[exception]
+/// fn SysTick() {
+///     // ..
+/// }
+///
+/// # fn main() {}
+/// ```
+///
+/// where the name of the function must be one of:
+///
+/// - `DefaultHandler`
+/// - `NonMaskableInt`
+/// - `HardFault`
+/// - `MemoryManagement` (a)
+/// - `BusFault` (a)
+/// - `UsageFault` (a)
+/// - `SecureFault` (b)
+/// - `SVCall`
+/// - `DebugMonitor` (a)
+/// - `PendSV`
+/// - `SysTick`
+///
+/// (a) Not available on Cortex-M0 variants (`thumbv6m-none-eabi`)
+///
+/// (b) Only available on ARMv8-M
+///
+/// # Usage
+///
+/// ## HardFault handler
+///
+/// `#[exception(trampoline = true)] unsafe fn HardFault(..` sets the hard fault handler.
+/// If the trampoline parameter is set to true, the handler must have signature `unsafe fn(&ExceptionFrame) -> !`.
+/// If set to false, the handler must have signature `unsafe fn() -> !`.
+///
+/// This handler is not allowed to return as that can cause undefined behavior.
+///
+/// To maintain backwards compatibility the attribute can be used without trampoline parameter (`#[exception]`),
+/// which sets the trampoline to true.
+///
+/// ## Default handler
+///
+/// `#[exception] unsafe fn DefaultHandler(..` sets the *default* handler. All exceptions which have
+/// not been assigned a handler will be serviced by this handler. This handler must have signature
+/// `unsafe fn(irqn: i16) [-> !]`. `irqn` is the IRQ number (See CMSIS); `irqn` will be a negative
+/// number when the handler is servicing a core exception; `irqn` will be a positive number when the
+/// handler is servicing a device specific exception (interrupt).
+///
+/// ## Other handlers
+///
+/// `#[exception] fn Name(..` overrides the default handler for the exception with the given `Name`.
+/// These handlers must have signature `[unsafe] fn() [-> !]`. When overriding these other exception
+/// it's possible to add state to them by declaring `static mut` variables at the beginning of the
+/// body of the function. These variables will be safe to access from the function body.
+///
+/// # Properties
+///
+/// Exception handlers can only be called by the hardware. Other parts of the program can't refer to
+/// the exception handlers, much less invoke them as if they were functions.
+///
+/// `static mut` variables declared within an exception handler are safe to access and can be used
+/// to preserve state across invocations of the handler. The compiler can't prove this is safe so
+/// the attribute will help by making a transformation to the source code: for this reason a
+/// variable like `static mut FOO: u32` will become `let FOO: &mut u32;`.
+///
+/// # Safety
+///
+/// It is not generally safe to register handlers for non-maskable interrupts. On Cortex-M,
+/// `HardFault` is non-maskable (at least in general), and there is an explicitly non-maskable
+/// interrupt `NonMaskableInt`.
+///
+/// The reason for that is that non-maskable interrupts will preempt any currently running function,
+/// even if that function executes within a critical section. Thus, if it was safe to define NMI
+/// handlers, critical sections wouldn't work safely anymore.
+///
+/// This also means that defining a `DefaultHandler` must be unsafe, as that will catch
+/// `NonMaskableInt` and `HardFault` if no handlers for those are defined.
+///
+/// The safety requirements on those handlers is as follows: The handler must not access any data
+/// that is protected via a critical section and shared with other interrupts that may be preempted
+/// by the NMI while holding the critical section. As long as this requirement is fulfilled, it is
+/// safe to handle NMIs.
+///
+/// # Examples
+///
+/// - Setting the default handler
+///
+/// ```
+/// use cortex_m_rt::exception;
+///
+/// #[exception]
+/// unsafe fn DefaultHandler(irqn: i16) {
+///     println!("IRQn = {}", irqn);
+/// }
+///
+/// # fn main() {}
+/// ```
+///
+/// - Overriding the `SysTick` handler
+///
+/// ```
+/// use cortex_m_rt::exception;
+///
+/// #[exception]
+/// fn SysTick() {
+///     static mut COUNT: i32 = 0;
+///
+///     // `COUNT` is safe to access and has type `&mut i32`
+///     *COUNT += 1;
+///
+///     println!("{}", COUNT);
+/// }
+///
+/// # fn main() {}
+/// ```
+pub use macros::exception;
+
+/// Attribute to mark which function will be called at the beginning of the reset handler.
+///
+/// **IMPORTANT**: This attribute can appear at most *once* in the dependency graph.
+///
+/// The function must have the signature of `unsafe fn()`.
+///
+/// # Safety
+///
+/// The function will be called before memory is initialized, as soon as possible after reset. Any
+/// access of memory, including any static variables, will result in undefined behavior.
+///
+/// **Warning**: Due to [rvalue static promotion][rfc1414] static variables may be accessed whenever
+/// taking a reference to a constant. This means that even trivial expressions such as `&1` in the
+/// `#[pre_init]` function *or any code called by it* will cause **immediate undefined behavior**.
+///
+/// Users are advised to only use the `#[pre_init]` feature when absolutely necessary as these
+/// constraints make safe usage difficult.
+///
+/// # Examples
+///
+/// ```
+/// # use cortex_m_rt::pre_init;
+/// #[pre_init]
+/// unsafe fn before_main() {
+///     // do something here
+/// }
+///
+/// # fn main() {}
+/// ```
+///
+/// [rfc1414]: https://github.com/rust-lang/rfcs/blob/master/text/1414-rvalue_static_promotion.md
+pub use macros::pre_init;
+
+// We export this static with an informative name so that if an application attempts to link
+// two copies of cortex-m-rt together, linking will fail. We also declare a links key in
+// Cargo.toml which is the more modern way to solve the same problem, but we have to keep
+// __ONCE__ around to prevent linking with versions before the links key was added.
+#[export_name = "error: cortex-m-rt appears more than once in the dependency graph"]
+#[doc(hidden)]
+pub static __ONCE__: () = ();
+
+/// Registers stacked (pushed onto the stack) during an exception.
+#[derive(Clone, Copy)]
+#[repr(C)]
+#[allow(dead_code)]
+pub struct ExceptionFrame {
+    r0: u32,
+    r1: u32,
+    r2: u32,
+    r3: u32,
+    r12: u32,
+    lr: u32,
+    pc: u32,
+    xpsr: u32,
+}
+
+impl ExceptionFrame {
+    /// Returns the value of (general purpose) register 0.
+    #[inline(always)]
+    pub fn r0(&self) -> u32 {
+        self.r0
+    }
+
+    /// Returns the value of (general purpose) register 1.
+    #[inline(always)]
+    pub fn r1(&self) -> u32 {
+        self.r1
+    }
+
+    /// Returns the value of (general purpose) register 2.
+    #[inline(always)]
+    pub fn r2(&self) -> u32 {
+        self.r2
+    }
+
+    /// Returns the value of (general purpose) register 3.
+    #[inline(always)]
+    pub fn r3(&self) -> u32 {
+        self.r3
+    }
+
+    /// Returns the value of (general purpose) register 12.
+    #[inline(always)]
+    pub fn r12(&self) -> u32 {
+        self.r12
+    }
+
+    /// Returns the value of the Link Register.
+    #[inline(always)]
+    pub fn lr(&self) -> u32 {
+        self.lr
+    }
+
+    /// Returns the value of the Program Counter.
+    #[inline(always)]
+    pub fn pc(&self) -> u32 {
+        self.pc
+    }
+
+    /// Returns the value of the Program Status Register.
+    #[inline(always)]
+    pub fn xpsr(&self) -> u32 {
+        self.xpsr
+    }
+
+    /// Sets the stacked value of (general purpose) register 0.
+    ///
+    /// # Safety
+    ///
+    /// This affects the `r0` register of the preempted code, which must not rely on it getting
+    /// restored to its previous value.
+    #[inline(always)]
+    pub unsafe fn set_r0(&mut self, value: u32) {
+        self.r0 = value;
+    }
+
+    /// Sets the stacked value of (general purpose) register 1.
+    ///
+    /// # Safety
+    ///
+    /// This affects the `r1` register of the preempted code, which must not rely on it getting
+    /// restored to its previous value.
+    #[inline(always)]
+    pub unsafe fn set_r1(&mut self, value: u32) {
+        self.r1 = value;
+    }
+
+    /// Sets the stacked value of (general purpose) register 2.
+    ///
+    /// # Safety
+    ///
+    /// This affects the `r2` register of the preempted code, which must not rely on it getting
+    /// restored to its previous value.
+    #[inline(always)]
+    pub unsafe fn set_r2(&mut self, value: u32) {
+        self.r2 = value;
+    }
+
+    /// Sets the stacked value of (general purpose) register 3.
+    ///
+    /// # Safety
+    ///
+    /// This affects the `r3` register of the preempted code, which must not rely on it getting
+    /// restored to its previous value.
+    #[inline(always)]
+    pub unsafe fn set_r3(&mut self, value: u32) {
+        self.r3 = value;
+    }
+
+    /// Sets the stacked value of (general purpose) register 12.
+    ///
+    /// # Safety
+    ///
+    /// This affects the `r12` register of the preempted code, which must not rely on it getting
+    /// restored to its previous value.
+    #[inline(always)]
+    pub unsafe fn set_r12(&mut self, value: u32) {
+        self.r12 = value;
+    }
+
+    /// Sets the stacked value of the Link Register.
+    ///
+    /// # Safety
+    ///
+    /// This affects the `lr` register of the preempted code, which must not rely on it getting
+    /// restored to its previous value.
+    #[inline(always)]
+    pub unsafe fn set_lr(&mut self, value: u32) {
+        self.lr = value;
+    }
+
+    /// Sets the stacked value of the Program Counter.
+    ///
+    /// # Safety
+    ///
+    /// This affects the `pc` register of the preempted code, which must not rely on it getting
+    /// restored to its previous value.
+    #[inline(always)]
+    pub unsafe fn set_pc(&mut self, value: u32) {
+        self.pc = value;
+    }
+
+    /// Sets the stacked value of the Program Status Register.
+    ///
+    /// # Safety
+    ///
+    /// This affects the `xPSR` registers (`IPSR`, `APSR`, and `EPSR`) of the preempted code, which
+    /// must not rely on them getting restored to their previous value.
+    #[inline(always)]
+    pub unsafe fn set_xpsr(&mut self, value: u32) {
+        self.xpsr = value;
+    }
+}
+
+impl fmt::Debug for ExceptionFrame {
+    fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
+        struct Hex(u32);
+        impl fmt::Debug for Hex {
+            fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
+                write!(f, "0x{:08x}", self.0)
+            }
+        }
+        f.debug_struct("ExceptionFrame")
+            .field("r0", &Hex(self.r0))
+            .field("r1", &Hex(self.r1))
+            .field("r2", &Hex(self.r2))
+            .field("r3", &Hex(self.r3))
+            .field("r12", &Hex(self.r12))
+            .field("lr", &Hex(self.lr))
+            .field("pc", &Hex(self.pc))
+            .field("xpsr", &Hex(self.xpsr))
+            .finish()
+    }
+}
+
+/// Returns a pointer to the start of the heap
+///
+/// The returned pointer is guaranteed to be 4-byte aligned.
+#[inline]
+pub fn heap_start() -> *mut u32 {
+    extern "C" {
+        static mut __sheap: u32;
+    }
+
+    #[allow(unused_unsafe)] // no longer unsafe since rust 1.82.0
+    unsafe {
+        core::ptr::addr_of_mut!(__sheap)
+    }
+}
+
+// Entry point is Reset.
+#[doc(hidden)]
+#[cfg_attr(cortex_m, link_section = ".vector_table.reset_vector")]
+#[no_mangle]
+pub static __RESET_VECTOR: unsafe extern "C" fn() -> ! = Reset;
+
+#[doc(hidden)]
+#[cfg_attr(cortex_m, link_section = ".HardFault.default")]
+#[no_mangle]
+pub unsafe extern "C" fn HardFault_() -> ! {
+    #[allow(clippy::empty_loop)]
+    loop {}
+}
+
+#[doc(hidden)]
+#[no_mangle]
+pub unsafe extern "C" fn DefaultHandler_() -> ! {
+    #[allow(clippy::empty_loop)]
+    loop {}
+}
+
+#[doc(hidden)]
+#[no_mangle]
+pub unsafe extern "C" fn DefaultPreInit() {}
+
+/* Exceptions */
+#[doc(hidden)]
+pub enum Exception {
+    NonMaskableInt,
+
+    // Not overridable
+    // HardFault,
+    #[cfg(not(armv6m))]
+    MemoryManagement,
+
+    #[cfg(not(armv6m))]
+    BusFault,
+
+    #[cfg(not(armv6m))]
+    UsageFault,
+
+    #[cfg(armv8m)]
+    SecureFault,
+
+    SVCall,
+
+    #[cfg(not(armv6m))]
+    DebugMonitor,
+
+    PendSV,
+
+    SysTick,
+}
+
+#[doc(hidden)]
+pub use self::Exception as exception;
+
+extern "C" {
+    fn Reset() -> !;
+
+    fn NonMaskableInt();
+
+    fn HardFault();
+
+    #[cfg(not(armv6m))]
+    fn MemoryManagement();
+
+    #[cfg(not(armv6m))]
+    fn BusFault();
+
+    #[cfg(not(armv6m))]
+    fn UsageFault();
+
+    #[cfg(armv8m)]
+    fn SecureFault();
+
+    fn SVCall();
+
+    #[cfg(not(armv6m))]
+    fn DebugMonitor();
+
+    fn PendSV();
+
+    fn SysTick();
+}
+
+#[doc(hidden)]
+#[repr(C)]
+pub union Vector {
+    handler: unsafe extern "C" fn(),
+    reserved: usize,
+}
+
+#[doc(hidden)]
+#[cfg_attr(cortex_m, link_section = ".vector_table.exceptions")]
+#[no_mangle]
+pub static __EXCEPTIONS: [Vector; 14] = [
+    // Exception 2: Non Maskable Interrupt.
+    Vector {
+        handler: NonMaskableInt,
+    },
+    // Exception 3: Hard Fault Interrupt.
+    Vector { handler: HardFault },
+    // Exception 4: Memory Management Interrupt [not on Cortex-M0 variants].
+    #[cfg(not(armv6m))]
+    Vector {
+        handler: MemoryManagement,
+    },
+    #[cfg(armv6m)]
+    Vector { reserved: 0 },
+    // Exception 5: Bus Fault Interrupt [not on Cortex-M0 variants].
+    #[cfg(not(armv6m))]
+    Vector { handler: BusFault },
+    #[cfg(armv6m)]
+    Vector { reserved: 0 },
+    // Exception 6: Usage Fault Interrupt [not on Cortex-M0 variants].
+    #[cfg(not(armv6m))]
+    Vector {
+        handler: UsageFault,
+    },
+    #[cfg(armv6m)]
+    Vector { reserved: 0 },
+    // Exception 7: Secure Fault Interrupt [only on Armv8-M].
+    #[cfg(armv8m)]
+    Vector {
+        handler: SecureFault,
+    },
+    #[cfg(not(armv8m))]
+    Vector { reserved: 0 },
+    // 8-10: Reserved
+    Vector { reserved: 0 },
+    Vector { reserved: 0 },
+    Vector { reserved: 0 },
+    // Exception 11: SV Call Interrupt.
+    Vector { handler: SVCall },
+    // Exception 12: Debug Monitor Interrupt [not on Cortex-M0 variants].
+    #[cfg(not(armv6m))]
+    Vector {
+        handler: DebugMonitor,
+    },
+    #[cfg(armv6m)]
+    Vector { reserved: 0 },
+    // 13: Reserved
+    Vector { reserved: 0 },
+    // Exception 14: Pend SV Interrupt [not on Cortex-M0 variants].
+    Vector { handler: PendSV },
+    // Exception 15: System Tick Interrupt.
+    Vector { handler: SysTick },
+];
+
+// If we are not targeting a specific device we bind all the potential device specific interrupts
+// to the default handler
+#[cfg(all(any(not(feature = "device"), test), not(armv6m), not(armv8m)))]
+#[doc(hidden)]
+#[cfg_attr(cortex_m, link_section = ".vector_table.interrupts")]
+#[no_mangle]
+pub static __INTERRUPTS: [unsafe extern "C" fn(); 240] = [{
+    extern "C" {
+        fn DefaultHandler();
+    }
+
+    DefaultHandler
+}; 240];
+
+// ARMv8-M can have up to 496 device specific interrupts
+#[cfg(all(not(feature = "device"), armv8m))]
+#[doc(hidden)]
+#[cfg_attr(cortex_m, link_section = ".vector_table.interrupts")]
+#[no_mangle]
+pub static __INTERRUPTS: [unsafe extern "C" fn(); 496] = [{
+    extern "C" {
+        fn DefaultHandler();
+    }
+
+    DefaultHandler
+}; 496];
+
+// ARMv6-M can only have a maximum of 32 device specific interrupts
+#[cfg(all(not(feature = "device"), armv6m))]
+#[doc(hidden)]
+#[link_section = ".vector_table.interrupts"]
+#[no_mangle]
+pub static __INTERRUPTS: [unsafe extern "C" fn(); 32] = [{
+    extern "C" {
+        fn DefaultHandler();
+    }
+
+    DefaultHandler
+}; 32];

### external/vendor/cortex-m-rt/tests/README.md
@@ -0,0 +1,7 @@
+# How to run
+
+To run the compile tests, use the following command on the root of the project:
+
+```
+cargo test --package cortex-m-rt --test compiletest --features device
+```

### external/vendor/cortex-m-rt/tests/compile-fail/default-handler-bad-signature-1.rs
@@ -0,0 +1,16 @@
+#![no_main]
+#![no_std]
+
+extern crate cortex_m_rt;
+extern crate panic_halt;
+
+use cortex_m_rt::{entry, exception};
+
+#[entry]
+fn foo() -> ! {
+    loop {}
+}
+
+#[exception]
+unsafe fn DefaultHandler(_irqn: i16, undef: u32) {}
+//~^ ERROR `DefaultHandler` must have signature `unsafe fn(i16) [-> !]`

### external/vendor/cortex-m-rt/tests/compile-fail/default-handler-bad-signature-2.rs
@@ -0,0 +1,18 @@
+#![no_main]
+#![no_std]
+
+extern crate cortex_m_rt;
+extern crate panic_halt;
+
+use cortex_m_rt::{entry, exception};
+
+#[entry]
+fn foo() -> ! {
+    loop {}
+}
+
+#[exception]
+unsafe fn DefaultHandler(_irqn: i16) -> u32 {
+    //~^ ERROR `DefaultHandler` must have signature `unsafe fn(i16) [-> !]`
+    0
+}

### external/vendor/cortex-m-rt/tests/compile-fail/default-handler-hidden.rs
@@ -0,0 +1,22 @@
+// ignore-test :sadface: it's not possible to prevent this user error at compile time
+// see rust-lang/rust#53975 for details
+
+#![no_main]
+#![no_std]
+
+extern crate cortex_m_rt;
+extern crate panic_halt;
+
+use cortex_m_rt::{entry, exception};
+
+#[entry]
+fn foo() -> ! {
+    loop {}
+}
+
+mod hidden {
+    use cortex_m_rt::exception;
+
+    #[exception]
+    unsafe fn DefaultHandler(_irqn: i16) {}
+}

### external/vendor/cortex-m-rt/tests/compile-fail/default-handler-twice.rs
@@ -0,0 +1,22 @@
+#![no_main]
+#![no_std]
+
+extern crate cortex_m_rt;
+extern crate panic_halt;
+
+use cortex_m_rt::{entry, exception};
+
+#[entry]
+fn foo() -> ! {
+    loop {}
+}
+
+#[exception]
+unsafe fn DefaultHandler(_irqn: i16) {}
+
+pub mod reachable {
+    use cortex_m_rt::exception;
+
+    #[exception] //~ ERROR symbol `DefaultHandler` is already defined
+    unsafe fn DefaultHandler(_irqn: i16) {}
+}

### external/vendor/cortex-m-rt/tests/compile-fail/duplicate-static.rs
@@ -0,0 +1,32 @@
+#![no_main]
+#![no_std]
+
+extern crate cortex_m_rt;
+extern crate panic_halt;
+
+use cortex_m_rt::{entry, exception, interrupt};
+
+#[allow(non_camel_case_types)]
+enum interrupt {
+    UART0,
+}
+
+#[entry]
+fn foo() -> ! {
+    static mut X: u32 = 0;
+    static mut X: i32 = 0; //~ ERROR the name `X` is defined multiple times
+
+    loop {}
+}
+
+#[exception]
+fn SVCall() {
+    static mut X: u32 = 0;
+    static mut X: i32 = 0; //~ ERROR the name `X` is defined multiple times
+}
+
+#[interrupt]
+fn UART0() {
+    static mut X: u32 = 0;
+    static mut X: i32 = 0; //~ ERROR the name `X` is defined multiple times
+}

### external/vendor/cortex-m-rt/tests/compile-fail/entry-args.rs
@@ -0,0 +1,12 @@
+#![no_main]
+#![no_std]
+
+extern crate cortex_m_rt;
+extern crate panic_halt;
+
+use cortex_m_rt::entry;
+
+#[entry(foo)] //~ ERROR This attribute accepts no arguments
+fn foo() -> ! {
+    loop {}
+}

### external/vendor/cortex-m-rt/tests/compile-fail/entry-bad-signature-1.rs
@@ -0,0 +1,11 @@
+#![no_main]
+#![no_std]
+
+extern crate cortex_m_rt;
+extern crate panic_halt;
+
+use cortex_m_rt::entry;
+
+#[entry]
+fn foo() {}
+//~^ ERROR `#[entry]` function must have signature `[unsafe] fn() -> !`

### external/vendor/cortex-m-rt/tests/compile-fail/entry-bad-signature-2.rs
@@ -0,0 +1,11 @@
+#![no_main]
+#![no_std]
+
+extern crate cortex_m_rt;
+extern crate panic_halt;
+
+use cortex_m_rt::entry;
+
+#[entry]
+fn foo(undef: i32) -> ! {}
+//~^ ERROR `#[entry]` function must have signature `[unsafe] fn() -> !`

### external/vendor/cortex-m-rt/tests/compile-fail/entry-bad-signature-3.rs
@@ -0,0 +1,13 @@
+#![no_main]
+#![no_std]
+
+extern crate cortex_m_rt;
+extern crate panic_halt;
+
+use cortex_m_rt::entry;
+
+#[entry]
+extern "C" fn foo() -> ! {
+    //~^ ERROR `#[entry]` function must have signature `[unsafe] fn() -> !`
+    loop {}
+}

### external/vendor/cortex-m-rt/tests/compile-fail/entry-hidden.rs
@@ -0,0 +1,19 @@
+// ignore-test :sadface: it's not possible to prevent this user error at compile time
+// see rust-lang/rust#53975 for details
+
+#![no_main]
+#![no_std]
+
+extern crate cortex_m_rt;
+extern crate panic_halt;
+
+mod hidden {
+    use cortex_m_rt::entry;
+
+    // this function needs to be "reachable" (all modules between it and the crate root must be
+    // `pub`) or linking will fail
+    #[entry]
+    fn foo() -> ! { //~ ERROR function is never used
+        loop {}
+    }
+}

### external/vendor/cortex-m-rt/tests/compile-fail/entry-soundness.rs
@@ -0,0 +1,26 @@
+#![no_main]
+#![no_std]
+
+extern crate cortex_m_rt;
+extern crate panic_halt;
+
+use cortex_m_rt::{entry, exception};
+
+#[entry]
+fn foo() -> ! {
+    static mut COUNT: u64 = 0;
+
+    loop {
+        if *COUNT % 2 == 0 {
+            *COUNT += 1;
+        } else {
+            *COUNT *= 2;
+        }
+    }
+}
+
+#[exception]
+fn SysTick() {
+    // If this was allowed it would lead to a data race as `SysTick` can preempt `foo`
+    foo(); //~ ERROR cannot find function `foo` in this scope
+}

### external/vendor/cortex-m-rt/tests/compile-fail/entry-twice.rs
@@ -0,0 +1,17 @@
+#![no_main]
+#![no_std]
+
+extern crate cortex_m_rt;
+extern crate panic_halt;
+
+use cortex_m_rt::entry;
+
+#[entry]
+fn foo() -> ! {
+    loop {}
+}
+
+#[entry] //~ ERROR symbol `main` is already defined
+fn bar() -> ! {
+    loop {}
+}

### external/vendor/cortex-m-rt/tests/compile-fail/exception-args.rs
@@ -0,0 +1,15 @@
+#![no_main]
+#![no_std]
+
+extern crate cortex_m_rt;
+extern crate panic_halt;
+
+use cortex_m_rt::{entry, exception};
+
+#[entry]
+fn foo() -> ! {
+    loop {}
+}
+
+#[exception(SysTick)] //~ ERROR This attribute accepts no arguments
+fn SysTick() {}

### external/vendor/cortex-m-rt/tests/compile-fail/exception-bad-signature-1.rs
@@ -0,0 +1,16 @@
+#![no_main]
+#![no_std]
+
+extern crate cortex_m_rt;
+extern crate panic_halt;
+
+use cortex_m_rt::{entry, exception};
+
+#[entry]
+fn foo() -> ! {
+    loop {}
+}
+
+#[exception]
+fn SysTick(undef: u32) {}
+//~^ ERROR `#[exception]` handlers other than `DefaultHandler` and `HardFault` must have signature `[unsafe] fn() [-> !]`

### external/vendor/cortex-m-rt/tests/compile-fail/exception-bad-signature-2.rs
@@ -0,0 +1,18 @@
+#![no_main]
+#![no_std]
+
+extern crate cortex_m_rt;
+extern crate panic_halt;
+
+use cortex_m_rt::{entry, exception};
+
+#[entry]
+fn foo() -> ! {
+    loop {}
+}
+
+#[exception]
+fn SysTick() -> u32 {
+    //~^ ERROR `#[exception]` handlers other than `DefaultHandler` and `HardFault` must have signature `[unsafe] fn() [-> !]`
+    0
+}

### external/vendor/cortex-m-rt/tests/compile-fail/exception-hidden.rs
@@ -0,0 +1,22 @@
+// ignore-test :sadface: it's not possible to prevent this user error at compile time
+// see rust-lang/rust#53975 for details
+
+#![no_main]
+#![no_std]
+
+extern crate cortex_m_rt;
+extern crate panic_halt;
+
+use cortex_m_rt::{entry, exception};
+
+#[entry]
+fn foo() -> ! {
+    loop {}
+}
+
+mod hidden {
+    use cortex_m_rt::exception;
+
+    #[exception]
+    fn SysTick() {}
+}

### external/vendor/cortex-m-rt/tests/compile-fail/exception-nmi-unsafe.rs
@@ -0,0 +1,24 @@
+#![no_main]
+#![no_std]
+
+extern crate cortex_m_rt;
+extern crate panic_halt;
+
+use cortex_m_rt::{entry, exception};
+
+#[entry]
+fn foo() -> ! {
+    loop {}
+}
+
+#[exception]
+fn DefaultHandler(_irq: i16) {}
+//~^ ERROR defining a `DefaultHandler` is unsafe and requires an `unsafe fn`
+
+#[exception]
+fn HardFault() {}
+//~^ ERROR defining a `HardFault` handler is unsafe and requires an `unsafe fn`
+
+#[exception]
+fn NonMaskableInt() {}
+//~^ ERROR defining a `NonMaskableInt` handler is unsafe and requires an `unsafe fn`

### external/vendor/cortex-m-rt/tests/compile-fail/exception-soundness.rs
@@ -0,0 +1,29 @@
+#![no_main]
+#![no_std]
+
+extern crate cortex_m_rt;
+extern crate panic_halt;
+
+use cortex_m_rt::{entry, exception};
+
+#[entry]
+fn foo() -> ! {
+    loop {}
+}
+
+#[exception]
+fn SysTick() {
+    static mut COUNT: u64 = 0;
+
+    if *COUNT % 2 == 0 {
+        *COUNT += 1;
+    } else {
+        *COUNT *= 2;
+    }
+}
+
+#[exception]
+fn SVCall() {
+    // If this was allowed it would lead to a data race as `SVCall` could preempt `SysTick`
+    SysTick(); //~ ERROR cannot find function, tuple struct or tuple variant `SysTick` in this scope [E0425]
+}

### external/vendor/cortex-m-rt/tests/compile-fail/exception-twice.rs
@@ -0,0 +1,22 @@
+#![no_main]
+#![no_std]
+
+extern crate cortex_m_rt;
+extern crate panic_halt;
+
+use cortex_m_rt::{entry, exception};
+
+#[entry]
+fn foo() -> ! {
+    loop {}
+}
+
+#[exception]
+fn SysTick() {}
+
+pub mod reachable {
+    use cortex_m_rt::exception;
+
+    #[exception] //~ ERROR symbol `SysTick` is already defined
+    fn SysTick() {}
+}

### external/vendor/cortex-m-rt/tests/compile-fail/exception-v8only.rs
@@ -0,0 +1,16 @@
+#![no_main]
+#![no_std]
+
+extern crate cortex_m_rt;
+extern crate panic_halt;
+
+use cortex_m_rt::{entry, exception};
+
+#[entry]
+fn foo() -> ! {
+    loop {}
+}
+
+#[exception]
+fn SecureFault() {}
+//~^ ERROR no variant or associated item named `SecureFault`

### external/vendor/cortex-m-rt/tests/compile-fail/hard-fault-bad-signature-1.rs
@@ -0,0 +1,18 @@
+#![no_main]
+#![no_std]
+
+extern crate cortex_m_rt;
+extern crate panic_halt;
+
+use cortex_m_rt::{entry, exception, ExceptionFrame};
+
+#[entry]
+fn foo() -> ! {
+    loop {}
+}
+
+#[exception]
+unsafe fn HardFault(_ef: &ExceptionFrame, undef: u32) -> ! {
+    //~^ ERROR `HardFault` handler must have signature `unsafe fn(&ExceptionFrame) -> !`
+    loop {}
+}

### external/vendor/cortex-m-rt/tests/compile-fail/hard-fault-bad-signature-2.rs
@@ -0,0 +1,18 @@
+#![no_main]
+#![no_std]
+
+extern crate cortex_m_rt;
+extern crate panic_halt;
+
+use cortex_m_rt::{entry, exception, ExceptionFrame};
+
+#[entry]
+fn foo() -> ! {
+    loop {}
+}
+
+#[exception(trampoline = true)]
+unsafe fn HardFault() -> ! {
+    //~^ ERROR `HardFault` handler must have signature `unsafe fn(&ExceptionFrame) -> !`
+    loop {}
+}

### external/vendor/cortex-m-rt/tests/compile-fail/hard-fault-bad-signature-3.rs
@@ -0,0 +1,18 @@
+#![no_main]
+#![no_std]
+
+extern crate cortex_m_rt;
+extern crate panic_halt;
+
+use cortex_m_rt::{entry, exception, ExceptionFrame};
+
+#[entry]
+fn foo() -> ! {
+    loop {}
+}
+
+#[exception(trampoline = false)]
+unsafe fn HardFault(_ef: &ExceptionFrame) -> ! {
+    //~^ ERROR `HardFault` handler must have signature `unsafe fn() -> !`
+    loop {}
+}

### external/vendor/cortex-m-rt/tests/compile-fail/hard-fault-hidden.rs
@@ -0,0 +1,24 @@
+// ignore-test :sadface: it's not possible to prevent this user error at compile time
+// see rust-lang/rust#53975 for details
+
+#![no_main]
+#![no_std]
+
+extern crate cortex_m_rt;
+extern crate panic_halt;
+
+use cortex_m_rt::{entry, exception, ExceptionFrame};
+
+#[entry]
+fn foo() -> ! {
+    loop {}
+}
+
+mod hidden {
+    use cortex_m_rt::{exception, ExceptionFrame};
+
+    #[exception]
+    fn HardFault(_ef: &ExceptionFrame) -> ! {
+        loop {}
+    }
+}

### external/vendor/cortex-m-rt/tests/compile-fail/hard-fault-twice-mixed-trampoline.rs
@@ -0,0 +1,26 @@
+#![no_main]
+#![no_std]
+
+extern crate cortex_m_rt;
+extern crate panic_halt;
+
+use cortex_m_rt::{entry, exception, ExceptionFrame};
+
+#[entry]
+fn foo() -> ! {
+    loop {}
+}
+
+#[exception(trampoline = false)]
+unsafe fn HardFault() -> ! {
+    loop {}
+}
+
+pub mod reachable {
+    use cortex_m_rt::{exception, ExceptionFrame};
+
+    #[exception] //~ ERROR symbol `_HardFault` is already defined
+    unsafe fn HardFault(_ef: &ExceptionFrame) -> ! {
+        loop {}
+    }
+}

### external/vendor/cortex-m-rt/tests/compile-fail/hard-fault-twice.rs
@@ -0,0 +1,26 @@
+#![no_main]
+#![no_std]
+
+extern crate cortex_m_rt;
+extern crate panic_halt;
+
+use cortex_m_rt::{entry, exception, ExceptionFrame};
+
+#[entry]
+fn foo() -> ! {
+    loop {}
+}
+
+#[exception]
+unsafe fn HardFault(_ef: &ExceptionFrame) -> ! {
+    loop {}
+}
+
+pub mod reachable {
+    use cortex_m_rt::{exception, ExceptionFrame};
+
+    #[exception] //~ ERROR symbol `_HardFault` is already defined
+    unsafe fn HardFault(_ef: &ExceptionFrame) -> ! {
+        loop {}
+    }
+}

### external/vendor/cortex-m-rt/tests/compile-fail/interrupt-args.rs
@@ -0,0 +1,20 @@
+#![no_main]
+#![no_std]
+
+extern crate cortex_m_rt;
+extern crate panic_halt;
+
+use cortex_m_rt::{entry, interrupt};
+
+#[entry]
+fn foo() -> ! {
+    loop {}
+}
+
+#[allow(non_camel_case_types)]
+enum interrupt {
+    USART1,
+}
+
+#[interrupt(true)] //~ ERROR This attribute accepts no arguments
+fn USART1() {}

### external/vendor/cortex-m-rt/tests/compile-fail/interrupt-bad-signature-1.rs
@@ -0,0 +1,21 @@
+#![no_main]
+#![no_std]
+
+extern crate cortex_m_rt;
+extern crate panic_halt;
+
+use cortex_m_rt::{entry, interrupt};
+
+#[entry]
+fn foo() -> ! {
+    loop {}
+}
+
+#[allow(non_camel_case_types)]
+enum interrupt {
+    USART1,
+}
+
+#[interrupt]
+fn USART1(undef: i32) {}
+//~^ ERROR `#[interrupt]` handlers must have signature `[unsafe] fn() [-> !]`

### external/vendor/cortex-m-rt/tests/compile-fail/interrupt-bad-signature-2.rs
@@ -0,0 +1,23 @@
+#![no_main]
+#![no_std]
+
+extern crate cortex_m_rt;
+extern crate panic_halt;
+
+use cortex_m_rt::{entry, interrupt};
+
+#[entry]
+fn foo() -> ! {
+    loop {}
+}
+
+#[allow(non_camel_case_types)]
+enum interrupt {
+    USART1,
+}
+
+#[interrupt]
+fn USART1() -> i32 {
+    //~^ ERROR `#[interrupt]` handlers must have signature `[unsafe] fn() [-> !]`
+    0
+}

### external/vendor/cortex-m-rt/tests/compile-fail/interrupt-invalid.rs
@@ -0,0 +1,22 @@
+#![no_main]
+#![no_std]
+
+extern crate cortex_m_rt;
+extern crate panic_halt;
+
+use cortex_m_rt::{entry, interrupt};
+
+#[entry]
+fn entry() -> ! {
+    loop {}
+}
+
+#[allow(non_camel_case_types)]
+enum interrupt {
+    USART1,
+}
+
+// NOTE this looks a bit better when using a device crate:
+// "no variant named `foo` found for type `stm32f30x::Interrupt` in the current scope"
+#[interrupt]
+fn foo() {} //~ ERROR no variant or associated item named `foo` found for enum `interrupt` in the current scope [E0599]

### external/vendor/cortex-m-rt/tests/compile-fail/interrupt-not-reexported.rs
@@ -0,0 +1,15 @@
+#![no_main]
+#![no_std]
+
+extern crate cortex_m_rt;
+extern crate panic_halt;
+
+use cortex_m_rt::{entry, interrupt};
+
+#[entry]
+fn foo() -> ! {
+    loop {}
+}
+
+#[interrupt] //~ ERROR failed to resolve: use of undeclared crate or module `interrupt`
+fn USART1() {}

### external/vendor/cortex-m-rt/tests/compile-fail/interrupt-soundness.rs
@@ -0,0 +1,34 @@
+#![no_main]
+#![no_std]
+
+extern crate cortex_m_rt;
+extern crate panic_halt;
+
+use cortex_m_rt::{entry, interrupt};
+
+#[entry]
+fn foo() -> ! {
+    loop {}
+}
+
+#[allow(non_camel_case_types)]
+enum interrupt {
+    USART1,
+    USART2,
+}
+
+#[interrupt]
+fn USART1() {
+    static mut COUNT: u64 = 0;
+
+    if *COUNT % 2 == 0 {
+        *COUNT += 1;
+    } else {
+        *COUNT *= 2;
+    }
+}
+
+#[interrupt]
+fn USART2() {
+    USART1(); //~ ERROR cannot find function, tuple struct or tuple variant `USART1` in this scope [E0425]
+}

### external/vendor/cortex-m-rt/tests/compile-fail/interrupt-twice.rs
@@ -0,0 +1,31 @@
+#![allow(non_camel_case_types)]
+#![no_main]
+#![no_std]
+
+extern crate cortex_m_rt;
+extern crate panic_halt;
+
+use cortex_m_rt::{entry, interrupt};
+
+#[entry]
+fn foo() -> ! {
+    loop {}
+}
+
+enum interrupt {
+    USART1,
+}
+
+#[interrupt]
+fn USART1() {}
+
+pub mod reachable {
+    use cortex_m_rt::interrupt;
+
+    enum interrupt {
+        USART1,
+    }
+
+    #[interrupt] //~ ERROR symbol `USART1` is already defined
+    fn USART1() {}
+}

### external/vendor/cortex-m-rt/tests/compile-fail/non-static-resource.rs
@@ -0,0 +1,44 @@
+//! Tests that no `&'static mut` to static mutable resources can be obtained, which would be
+//! unsound.
+//!
+//! Regression test for https://github.com/rust-embedded/cortex-m-rt/issues/212
+
+#![no_std]
+#![no_main]
+
+extern crate cortex_m_rt;
+extern crate panic_halt;
+
+use cortex_m_rt::{entry, exception, interrupt, ExceptionFrame};
+
+#[allow(non_camel_case_types)]
+enum interrupt {
+    UART0,
+}
+
+#[exception]
+fn SVCall() {
+    static mut STAT: u8 = 0;
+
+    let _stat: &'static mut u8 = STAT;
+    //~^ ERROR lifetime may not live long enough
+}
+
+#[interrupt]
+fn UART0() {
+    static mut STAT: u8 = 0;
+
+    let _stat: &'static mut u8 = STAT;
+    //~^ ERROR lifetime may not live long enough
+}
+
+#[entry]
+fn you_died_of_dis_entry() -> ! {
+    static mut STAT: u8 = 0;
+
+    // Allowed. This is sound for the entry point since it is only ever called once, and it makes
+    // resources far more useful.
+    let _stat: &'static mut u8 = STAT;
+
+    loop {}
+}

### external/vendor/cortex-m-rt/tests/compile-fail/pre-init-args.rs
@@ -0,0 +1,15 @@
+#![no_main]
+#![no_std]
+
+extern crate cortex_m_rt;
+extern crate panic_halt;
+
+use cortex_m_rt::{entry, pre_init};
+
+#[pre_init(foo)] //~ ERROR This attribute accepts no arguments
+unsafe fn foo() {}
+
+#[entry]
+fn baz() -> ! {
+    loop {}
+}

### external/vendor/cortex-m-rt/tests/compile-fail/pre-init-bad-signature-1.rs
@@ -0,0 +1,16 @@
+#![no_main]
+#![no_std]
+
+extern crate cortex_m_rt;
+extern crate panic_halt;
+
+use cortex_m_rt::{entry, pre_init};
+
+#[pre_init]
+fn foo() {}
+//~^ ERROR `#[pre_init]` function must have signature `unsafe fn()`
+
+#[entry]
+fn bar() -> ! {
+    loop {}
+}

### external/vendor/cortex-m-rt/tests/compile-fail/pre-init-bad-signature-2.rs
@@ -0,0 +1,16 @@
+#![no_main]
+#![no_std]
+
+extern crate cortex_m_rt;
+extern crate panic_halt;
+
+use cortex_m_rt::{entry, pre_init};
+
+#[pre_init]
+unsafe fn foo(undef: i32) {}
+//~^ ERROR `#[pre_init]` function must have signature `unsafe fn()`
+
+#[entry]
+fn bar() -> ! {
+    loop {}
+}

### external/vendor/cortex-m-rt/tests/compile-fail/pre-init-hidden.rs
@@ -0,0 +1,23 @@
+// ignore-test :sadface: it's not possible to prevent this user error at compile time
+// see rust-lang/rust#53975 for details
+
+#![no_main]
+#![no_std]
+
+extern crate cortex_m_rt;
+extern crate panic_halt;
+
+mod hidden {
+    use cortex_m_rt::pre_init;
+
+    // this function needs to be "reachable" (all modules between it and the crate root must be
+    // `pub`) or the function will be ignored
+    #[entry]
+    unsafe fn pre_init() {} //~ ERROR function is never used
+}
+
+#[entry]
+fn foo() -> ! {
+    //~ ERROR function is never used
+    loop {}
+}

### external/vendor/cortex-m-rt/tests/compile-fail/pre-init-twice.rs
@@ -0,0 +1,18 @@
+#![no_main]
+#![no_std]
+
+extern crate cortex_m_rt;
+extern crate panic_halt;
+
+use cortex_m_rt::{entry, pre_init};
+
+#[pre_init]
+unsafe fn foo() {}
+
+#[pre_init] //~ ERROR symbol `__pre_init` is already defined
+unsafe fn bar() {}
+
+#[entry]
+fn baz() -> ! {
+    loop {}
+}

### external/vendor/cortex-m-rt/tests/compile-fail/unsafe-init-static.rs
@@ -0,0 +1,45 @@
+//! Makes sure that the expansion of the attributes doesn't put the resource initializer in an
+//! implicit `unsafe` block.
+
+#![no_main]
+#![no_std]
+
+extern crate cortex_m_rt;
+extern crate panic_halt;
+
+use cortex_m_rt::{entry, exception, interrupt};
+
+#[allow(non_camel_case_types)]
+enum interrupt {
+    UART0,
+}
+
+const unsafe fn init() -> u32 { 0 }
+
+#[entry]
+fn foo() -> ! {
+    static mut X: u32 = init();  //~ ERROR requires unsafe
+
+    loop {}
+}
+
+#[exception]
+fn SVCall() {
+    static mut X: u32 = init();  //~ ERROR requires unsafe
+}
+
+#[exception]
+unsafe fn DefaultHandler(_irq: i16) {
+    static mut X: u32 = init();  //~ ERROR requires unsafe
+}
+
+#[exception]
+unsafe fn HardFault(_frame: &cortex_m_rt::ExceptionFrame) -> ! {
+    static mut X: u32 = init();  //~ ERROR requires unsafe
+    loop {}
+}
+
+#[interrupt]
+fn UART0() {
+    static mut X: u32 = init();  //~ ERROR requires unsafe
+}

### external/vendor/cortex-m-rt/tests/compile-fail/whitelist-1.rs
@@ -0,0 +1,32 @@
+#![no_main]
+#![no_std]
+
+extern crate cortex_m_rt;
+extern crate panic_halt;
+
+use cortex_m_rt::{entry, exception, interrupt};
+
+#[inline] //~ ERROR this attribute is not allowed on a cortex-m-rt entry point
+#[entry]
+fn foo() -> ! {
+    loop {}
+}
+
+#[inline] //~ ERROR this attribute is not allowed on an exception handler controlled by cortex-m-rt
+#[exception]
+fn SysTick() {}
+
+#[allow(non_camel_case_types)]
+enum interrupt {
+    USART1,
+    USART2,
+}
+
+#[inline] //~ ERROR this attribute is not allowed on an interrupt handler controlled by cortex-m-rt
+#[interrupt]
+fn USART1() {}
+
+#[cfg(feature = "device")]
+#[cfg_attr(feature = "device", inline)] //~ ERROR this attribute is not allowed on an interrupt handler controlled by cortex-m-rt
+#[interrupt]
+fn USART2() {}

### external/vendor/cortex-m-rt/tests/compile-fail/whitelist-2.rs
@@ -0,0 +1,32 @@
+#![no_main]
+#![no_std]
+
+extern crate cortex_m_rt;
+extern crate panic_halt;
+
+use cortex_m_rt::{entry, exception, interrupt};
+
+#[export_name = "not_allowed"] //~ ERROR this attribute is not allowed on a cortex-m-rt entry point
+#[entry]
+fn foo() -> ! {
+    loop {}
+}
+
+#[export_name = "not_allowed"] //~ ERROR this attribute is not allowed on an exception handler controlled by cortex-m-rt
+#[exception]
+fn SysTick() {}
+
+#[allow(non_camel_case_types)]
+enum interrupt {
+    USART1,
+    USART2,
+}
+
+#[export_name = "not_allowed"] //~ ERROR this attribute is not allowed on an interrupt handler controlled by cortex-m-rt
+#[interrupt]
+fn USART1() {}
+
+#[cfg(feature = "device")]
+#[cfg_attr(feature = "device", export_name = "not_allowed")] //~ ERROR this attribute is not allowed on an interrupt handler controlled by cortex-m-rt
+#[interrupt]
+fn USART2() {}

### external/vendor/cortex-m-rt/tests/compile-fail/whitelist-3.rs
@@ -0,0 +1,32 @@
+#![no_main]
+#![no_std]
+
+extern crate cortex_m_rt;
+extern crate panic_halt;
+
+use cortex_m_rt::{entry, exception, interrupt};
+
+#[no_mangle] //~ ERROR this attribute is not allowed on a cortex-m-rt entry point
+#[entry]
+fn foo() -> ! {
+    loop {}
+}
+
+#[no_mangle] //~ ERROR this attribute is not allowed on an exception handler controlled by cortex-m-rt
+#[exception]
+fn SysTick() {}
+
+#[allow(non_camel_case_types)]
+enum interrupt {
+    USART1,
+    USART2,
+}
+
+#[no_mangle] //~ ERROR this attribute is not allowed on an interrupt handler controlled by cortex-m-rt
+#[interrupt]
+fn USART1() {}
+
+#[cfg(feature = "device")]
+#[cfg_attr(feature = "device", no_mangle)] //~ ERROR this attribute is not allowed on an interrupt handler controlled by cortex-m-rt
+#[interrupt]
+fn USART2() {}

### external/vendor/cortex-m-rt/tests/compile-fail/whitelist-4.rs
@@ -0,0 +1,32 @@
+#![no_main]
+#![no_std]
+
+extern crate cortex_m_rt;
+extern crate panic_halt;
+
+use cortex_m_rt::{entry, exception, interrupt};
+
+#[must_use] //~ ERROR this attribute is not allowed on a cortex-m-rt entry point
+#[entry]
+fn foo() -> ! {
+    loop {}
+}
+
+#[must_use] //~ ERROR this attribute is not allowed on an exception handler controlled by cortex-m-rt
+#[exception]
+fn SysTick() {}
+
+#[allow(non_camel_case_types)]
+enum interrupt {
+    USART1,
+    USART2,
+}
+
+#[must_use] //~ ERROR this attribute is not allowed on an interrupt handler controlled by cortex-m-rt
+#[interrupt]
+fn USART1() {}
+
+#[cfg(feature = "device")]
+#[cfg_attr(feature = "device", must_use)] //~ ERROR this attribute is not allowed on an interrupt handler controlled by cortex-m-rt
+#[interrupt]
+fn USART2() {}

### external/vendor/cortex-m-rt/tests/compile-fail/whitelist-double-attr.rs
@@ -0,0 +1,13 @@
+#![no_main]
+#![no_std]
+
+extern crate cortex_m_rt;
+extern crate panic_halt;
+
+use cortex_m_rt::{entry, exception};
+
+#[exception]
+#[entry] //~ ERROR this attribute is not allowed on an exception handler
+fn SVCall() -> ! {
+    loop {}
+}

### external/vendor/cortex-m-rt/tests/compiletest.rs
@@ -0,0 +1,22 @@
+extern crate compiletest_rs as compiletest;
+
+use std::path::PathBuf;
+
+fn run_mode(mode: &'static str) {
+    let mut config = compiletest::Config::default();
+
+    config.mode = mode.parse().expect("Invalid mode");
+    config.src_base = PathBuf::from(format!("tests/{}", mode));
+    config.target_rustcflags = Some(
+        "-L ../target/debug -L ../target/debug/deps -C panic=abort --cfg feature=\"device\""
+            .to_owned(),
+    );
+    config.clean_rmeta(); // If your tests import the parent crate, this helps with E0464
+
+    compiletest::run_tests(&config);
+}
+
+#[test]
+fn compile_test() {
+    run_mode("compile-fail");
+}

### external/vendor/stm32u5/.cargo-checksum.json
[binary or diff unavailable]

### external/vendor/stm32u5/Cargo.lock
@@ -0,0 +1,259 @@
+# This file is automatically @generated by Cargo.
+# It is not intended for manual editing.
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+
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+ "cortex-m-rt",
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+ "portable-atomic",
+ "vcell",
+]
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+dependencies = [
+ "vcell",
+]

### external/vendor/stm32u5/Cargo.toml
@@ -0,0 +1,101 @@
+# THIS FILE IS AUTOMATICALLY GENERATED BY CARGO
+#
+# When uploading crates to the registry Cargo will automatically
+# "normalize" Cargo.toml files for maximal compatibility
+# with all versions of Cargo and also rewrite `path` dependencies
+# to registry (e.g., crates.io) dependencies.
+#
+# If you are reading this file be aware that the original Cargo.toml
+# will likely look very different (and much more reasonable).
+# See Cargo.toml.orig for the original contents.
+
+[package]
+edition = "2021"
+rust-version = "1.65"
+name = "stm32u5"
+version = "0.16.0"
+authors = [
+    "Adam Greig <adam@adamgreig.com>",
+    "stm32-rs Contributors",
+]
+build = "build.rs"
+autolib = false
+autobins = false
+autoexamples = false
+autotests = false
+autobenches = false
+description = "Device support crates for STM32U5 devices"
+readme = "README.md"
+keywords = [
+    "stm32",
+    "svd2rust",
+    "no_std",
+    "embedded",
+]
+categories = [
+    "embedded",
+    "no-std",
+]
+license = "MIT/Apache-2.0"
+repository = "https://github.com/stm32-rs/stm32-rs"
+
+[package.metadata.docs.rs]
+default-target = "thumbv8m.main-none-eabi"
+features = [
+    "atomics",
+    "critical-section",
+    "defmt",
+    "rt",
+    "stm32u535",
+    "stm32u545",
+    "stm32u575",
+    "stm32u585",
+    "stm32u595",
+    "stm32u5a5",
+    "stm32u599",
+    "stm32u5a9",
+]
+targets = []
+
+[features]
+atomics = ["dep:portable-atomic"]
+default = [
+    "critical-section",
+    "rt",
+]
+rt = ["cortex-m-rt/device"]
+stm32u535 = []
+stm32u545 = []
+stm32u575 = []
+stm32u585 = []
+stm32u595 = []
+stm32u599 = []
+stm32u5a5 = []
+stm32u5a9 = []
+
+[lib]
+name = "stm32u5"
+path = "src/lib.rs"
+
+[dependencies.cortex-m]
+version = "0.7.7"
+
+[dependencies.cortex-m-rt]
+version = "0.7.5"
+optional = true
+
+[dependencies.critical-section]
+version = "1.0"
+optional = true
+
+[dependencies.defmt]
+version = "1"
+optional = true
+
+[dependencies.portable-atomic]
+version = "1"
+optional = true
+default-features = false
+
+[dependencies.vcell]
+version = "0.1.3"

### external/vendor/stm32u5/Cargo.toml.orig
@@ -0,0 +1,38 @@
+[package]
+edition = "2021"
+name = "stm32u5"
+version = "0.16.0"
+authors = ["Adam Greig <adam@adamgreig.com>", "stm32-rs Contributors"]
+description = "Device support crates for STM32U5 devices"
+repository = "https://github.com/stm32-rs/stm32-rs"
+readme = "README.md"
+keywords = ["stm32", "svd2rust", "no_std", "embedded"]
+categories = ["embedded", "no-std"]
+license = "MIT/Apache-2.0"
+rust-version = "1.65"
+
+[dependencies]
+critical-section = { version = "1.0", optional = true }
+cortex-m = "0.7.7"
+cortex-m-rt = { version = "0.7.5", optional = true }
+defmt = { version = "1", optional = true }
+vcell = "0.1.3"
+portable-atomic = { version = "1", default-features = false, optional = true }
+
+[package.metadata.docs.rs]
+features = ['atomics', 'critical-section', 'defmt', 'rt', 'stm32u535', 'stm32u545', 'stm32u575', 'stm32u585', 'stm32u595', 'stm32u5a5', 'stm32u599', 'stm32u5a9']
+default-target = "thumbv8m.main-none-eabi"
+targets = []
+
+[features]
+default = ["critical-section", "rt"]
+rt = ["cortex-m-rt/device"]
+atomics = ["dep:portable-atomic"]
+stm32u535 = []
+stm32u545 = []
+stm32u575 = []
+stm32u585 = []
+stm32u595 = []
+stm32u599 = []
+stm32u5a5 = []
+stm32u5a9 = []

### external/vendor/stm32u5/README.md
@@ -0,0 +1,49 @@
+# stm32u5
+This crate provides an autogenerated API for access to STM32U5 peripherals.
+The API is generated using [svd2rust] with patched svd files containing
+extensive type-safe support. For more information please see the [main repo].
+
+Refer to the [documentation] for full details.
+
+[svd2rust]: https://github.com/rust-embedded/svd2rust
+[main repo]: https://github.com/stm32-rs/stm32-rs
+[documentation]: https://docs.rs/stm32u5/latest/stm32u5/
+
+## Usage
+Each device supported by this crate is behind a feature gate so that you only
+compile the device(s) you want. To use, in your Cargo.toml:
+
+```toml
+[dependencies.stm32u5]
+version = "0.16.0"
+features = ["stm32u535"]
+```
+
+The `rt` feature is enabled by default and brings in support for `cortex-m-rt`.
+To disable, specify `default-features = false` in `Cargo.toml`.
+
+In your code:
+
+```rust
+use stm32u5::stm32u535;
+
+let mut peripherals = stm32u535::Peripherals::take().unwrap();
+let gpioa = &peripherals.GPIOA;
+gpioa.odr.modify(|_, w| w.odr0().set_bit());
+```
+
+For full details on the autogenerated API, please see:
+https://docs.rs/svd2rust/0.36.1/svd2rust/#peripheral-api
+
+## Supported Devices
+
+| Module | Devices | Links |
+|:------:|:-------:|:-----:|
+| stm32u535 | STM32U535 | [RM0456](https://www.st.com/resource/en/reference_manual/rm0456-stm32u5-series-armbased-32bit-mcus-stmicroelectronics.pdf), [st.com](https://www.st.com/en/microcontrollers-microprocessors/stm32u535-545.html) |
+| stm32u545 | STM32U545 | [RM0456](https://www.st.com/resource/en/reference_manual/rm0456-stm32u5-series-armbased-32bit-mcus-stmicroelectronics.pdf), [st.com](https://www.st.com/en/microcontrollers-microprocessors/stm32u535-545.html) |
+| stm32u575 | STM32U575 | [RM0456](https://www.st.com/resource/en/reference_manual/rm0456-stm32u5-series-armbased-32bit-mcus-stmicroelectronics.pdf), [st.com](https://www.st.com/en/microcontrollers-microprocessors/stm32u575-585.html) |
+| stm32u585 | STM32U585 | [RM0456](https://www.st.com/resource/en/reference_manual/rm0456-stm32u5-series-armbased-32bit-mcus-stmicroelectronics.pdf), [st.com](https://www.st.com/en/microcontrollers-microprocessors/stm32u575-585.html) |
+| stm32u595 | STM32U595 | [RM0456](https://www.st.com/resource/en/reference_manual/rm0456-stm32u5-series-armbased-32bit-mcus-stmicroelectronics.pdf), [st.com](https://www.st.com/en/microcontrollers-microprocessors/stm32u595-5a5.html) |
+| stm32u599 | STM32U599 | [RM0456](https://www.st.com/resource/en/reference_manual/rm0456-stm32u5-series-armbased-32bit-mcus-stmicroelectronics.pdf), [st.com](https://www.st.com/en/microcontrollers-microprocessors/stm32u599-5a9.html) |
+| stm32u5a5 | STM32U5a5 | [RM0456](https://www.st.com/resource/en/reference_manual/rm0456-stm32u5-series-armbased-32bit-mcus-stmicroelectronics.pdf), [st.com](https://www.st.com/en/microcontrollers-microprocessors/stm32u595-5a5.html) |
+| stm32u5a9 | STM32U5a9 | [RM0456](https://www.st.com/resource/en/reference_manual/rm0456-stm32u5-series-armbased-32bit-mcus-stmicroelectronics.pdf), [st.com](https://www.st.com/en/microcontrollers-microprocessors/stm32u599-5a9.html) |

### external/vendor/stm32u5/build.rs
@@ -0,0 +1,24 @@
+use std::env;
+use std::fs;
+use std::path::PathBuf;
+fn main() {
+    if env::var_os("CARGO_FEATURE_RT").is_some() {
+        let out = &PathBuf::from(env::var_os("OUT_DIR").unwrap());
+        println!("cargo:rustc-link-search={}", out.display());
+        let devices = ["stm32u535", "stm32u545", "stm32u575", "stm32u585", "stm32u595", "stm32u599", "stm32u5a5", "stm32u5a9"];
+        let mut device_file = None;
+        for &d in &devices {
+            if env::var_os(&format!("CARGO_FEATURE_{}", d.to_uppercase())).is_some() {
+                device_file = Some(format!("src/{d}/device.x"));
+                break;
+            }
+        }
+        if let Some(device_file) = device_file {
+            fs::copy(&device_file, out.join("device.x")).unwrap();
+            println!("cargo:rerun-if-changed={device_file}");
+        } else {
+            panic!("No device features selected. Avaliable device features are: {devices:?}");
+        }
+    }
+    println!("cargo:rerun-if-changed=build.rs");
+}

### external/vendor/stm32u5/src/generic.rs
@@ -0,0 +1,1058 @@
+use core::marker;
+
+/// Generic peripheral accessor
+pub struct Periph<RB, const A: usize> {
+    _marker: marker::PhantomData<RB>,
+}
+
+unsafe impl<RB, const A: usize> Send for Periph<RB, A> {}
+
+impl<RB, const A: usize> Periph<RB, A> {
+    ///Pointer to the register block
+    pub const PTR: *const RB = A as *const _;
+
+    ///Return the pointer to the register block
+    #[inline(always)]
+    pub const fn ptr() -> *const RB {
+        Self::PTR
+    }
+
+    /// Steal an instance of this peripheral
+    ///
+    /// # Safety
+    ///
+    /// Ensure that the new instance of the peripheral cannot be used in a way
+    /// that may race with any existing instances, for example by only
+    /// accessing read-only or write-only registers, or by consuming the
+    /// original peripheral and using critical sections to coordinate
+    /// access between multiple new instances.
+    ///
+    /// Additionally, other software such as HALs may rely on only one
+    /// peripheral instance existing to ensure memory safety; ensure
+    /// no stolen instances are passed to such software.
+    pub unsafe fn steal() -> Self {
+        Self {
+            _marker: marker::PhantomData,
+        }
+    }
+}
+
+impl<RB, const A: usize> core::ops::Deref for Periph<RB, A> {
+    type Target = RB;
+
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        unsafe { &*Self::PTR }
+    }
+}
+
+/// Raw register type (`u8`, `u16`, `u32`, ...)
+pub trait RawReg:
+    Copy
+    + From<bool>
+    + core::ops::BitOr<Output = Self>
+    + core::ops::BitAnd<Output = Self>
+    + core::ops::BitOrAssign
+    + core::ops::BitAndAssign
+    + core::ops::Not<Output = Self>
+    + core::ops::Shl<u8, Output = Self>
+{
+    /// Mask for bits of width `WI`
+    fn mask<const WI: u8>() -> Self;
+    /// `0`
+    const ZERO: Self;
+    /// `1`
+    const ONE: Self;
+}
+
+macro_rules! raw_reg {
+    ($U:ty, $size:literal, $mask:ident) => {
+        impl RawReg for $U {
+            #[inline(always)]
+            fn mask<const WI: u8>() -> Self {
+                $mask::<WI>()
+            }
+            const ZERO: Self = 0;
+            const ONE: Self = 1;
+        }
+        const fn $mask<const WI: u8>() -> $U {
+            <$U>::MAX >> ($size - WI)
+        }
+        impl FieldSpec for $U {
+            type Ux = $U;
+        }
+    };
+}
+
+raw_reg!(u8, 8, mask_u8);
+raw_reg!(u16, 16, mask_u16);
+raw_reg!(u32, 32, mask_u32);
+raw_reg!(u64, 64, mask_u64);
+
+/// Raw register type
+pub trait RegisterSpec {
+    /// Raw register type (`u8`, `u16`, `u32`, ...).
+    type Ux: RawReg;
+}
+
+/// Raw field type
+pub trait FieldSpec: Sized {
+    /// Raw field type (`u8`, `u16`, `u32`, ...).
+    type Ux: Copy + core::fmt::Debug + PartialEq + From<Self>;
+}
+
+/// Marker for fields with fixed values
+pub trait IsEnum: FieldSpec {}
+
+/// Trait implemented by readable registers to enable the `read` method.
+///
+/// Registers marked with `Writable` can be also be `modify`'ed.
+pub trait Readable: RegisterSpec {}
+
+/// Trait implemented by writeable registers.
+///
+/// This enables the  `write`, `write_with_zero` and `reset` methods.
+///
+/// Registers marked with `Readable` can be also be `modify`'ed.
+pub trait Writable: RegisterSpec {
+    /// Is it safe to write any bits to register
+    type Safety;
+
+    /// Specifies the register bits that are not changed if you pass `1` and are changed if you pass `0`
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = Self::Ux::ZERO;
+
+    /// Specifies the register bits that are not changed if you pass `0` and are changed if you pass `1`
+    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = Self::Ux::ZERO;
+}
+
+/// Reset value of the register.
+///
+/// This value is the initial value for the `write` method. It can also be directly written to the
+/// register by using the `reset` method.
+pub trait Resettable: RegisterSpec {
+    /// Reset value of the register.
+    const RESET_VALUE: Self::Ux = Self::Ux::ZERO;
+
+    /// Reset value of the register.
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        Self::RESET_VALUE
+    }
+}
+
+#[doc(hidden)]
+pub mod raw {
+    use super::{marker, BitM, FieldSpec, RegisterSpec, Unsafe, Writable};
+
+    pub struct R<REG: RegisterSpec> {
+        pub(crate) bits: REG::Ux,
+        pub(super) _reg: marker::PhantomData<REG>,
+    }
+
+    pub struct W<REG: RegisterSpec> {
+        ///Writable bits
+        pub(crate) bits: REG::Ux,
+        pub(super) _reg: marker::PhantomData<REG>,
+    }
+
+    pub struct FieldReader<FI = u8>
+    where
+        FI: FieldSpec,
+    {
+        pub(crate) bits: FI::Ux,
+        _reg: marker::PhantomData<FI>,
+    }
+
+    impl<FI: FieldSpec> FieldReader<FI> {
+        /// Creates a new instance of the reader.
+        #[allow(unused)]
+        #[inline(always)]
+        pub(crate) const fn new(bits: FI::Ux) -> Self {
+            Self {
+                bits,
+                _reg: marker::PhantomData,
+            }
+        }
+    }
+
+    pub struct BitReader<FI = bool> {
+        pub(crate) bits: bool,
+        _reg: marker::PhantomData<FI>,
+    }
+
+    impl<FI> BitReader<FI> {
+        /// Creates a new instance of the reader.
+        #[allow(unused)]
+        #[inline(always)]
+        pub(crate) const fn new(bits: bool) -> Self {
+            Self {
+                bits,
+                _reg: marker::PhantomData,
+            }
+        }
+    }
+
+    #[must_use = "after creating `FieldWriter` you need to call field value setting method"]
+    pub struct FieldWriter<'a, REG, const WI: u8, FI = u8, Safety = Unsafe>
+    where
+        REG: Writable + RegisterSpec,
+        FI: FieldSpec,
+    {
+        pub(crate) w: &'a mut W<REG>,
+        pub(crate) o: u8,
+        _field: marker::PhantomData<(FI, Safety)>,
+    }
+
+    impl<'a, REG, const WI: u8, FI, Safety> FieldWriter<'a, REG, WI, FI, Safety>
+    where
+        REG: Writable + RegisterSpec,
+        FI: FieldSpec,
+    {
+        /// Creates a new instance of the writer
+        #[allow(unused)]
+        #[inline(always)]
+        pub(crate) fn new(w: &'a mut W<REG>, o: u8) -> Self {
+            Self {
+                w,
+                o,
+                _field: marker::PhantomData,
+            }
+        }
+    }
+
+    #[must_use = "after creating `BitWriter` you need to call bit setting method"]
+    pub struct BitWriter<'a, REG, FI = bool, M = BitM>
+    where
+        REG: Writable + RegisterSpec,
+        bool: From<FI>,
+    {
+        pub(crate) w: &'a mut W<REG>,
+        pub(crate) o: u8,
+        _field: marker::PhantomData<(FI, M)>,
+    }
+
+    impl<'a, REG, FI, M> BitWriter<'a, REG, FI, M>
+    where
+        REG: Writable + RegisterSpec,
+        bool: From<FI>,
+    {
+        /// Creates a new instance of the writer
+        #[allow(unused)]
+        #[inline(always)]
+        pub(crate) fn new(w: &'a mut W<REG>, o: u8) -> Self {
+            Self {
+                w,
+                o,
+                _field: marker::PhantomData,
+            }
+        }
+    }
+}
+
+/// Register reader.
+///
+/// Result of the `read` methods of registers. Also used as a closure argument in the `modify`
+/// method.
+pub type R<REG> = raw::R<REG>;
+
+impl<REG: RegisterSpec> R<REG> {
+    /// Reads raw bits from register.
+    #[inline(always)]
+    pub const fn bits(&self) -> REG::Ux {
+        self.bits
+    }
+}
+
+impl<REG: RegisterSpec, FI> PartialEq<FI> for R<REG>
+where
+    REG::Ux: PartialEq,
+    FI: Copy,
+    REG::Ux: From<FI>,
+{
+    #[inline(always)]
+    fn eq(&self, other: &FI) -> bool {
+        self.bits.eq(&REG::Ux::from(*other))
+    }
+}
+
+/// Register writer.
+///
+/// Used as an argument to the closures in the `write` and `modify` methods of the register.
+pub type W<REG> = raw::W<REG>;
+
+impl<REG: Writable> W<REG> {
+    /// Writes raw bits to the register.
+    ///
+    /// # Safety
+    ///
+    /// Passing incorrect value can cause undefined behaviour. See reference manual
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: REG::Ux) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+}
+impl<REG> W<REG>
+where
+    REG: Writable<Safety = Safe>,
+{
+    /// Writes raw bits to the register.
+    #[inline(always)]
+    pub fn set(&mut self, bits: REG::Ux) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+}
+
+/// Field reader.
+///
+/// Result of the `read` methods of fields.
+pub type FieldReader<FI = u8> = raw::FieldReader<FI>;
+
+/// Bit-wise field reader
+pub type BitReader<FI = bool> = raw::BitReader<FI>;
+
+impl<FI: FieldSpec> FieldReader<FI> {
+    /// Reads raw bits from field.
+    #[inline(always)]
+    pub const fn bits(&self) -> FI::Ux {
+        self.bits
+    }
+}
+
+impl<FI: FieldSpec> core::fmt::Debug for FieldReader<FI> {
+    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
+        core::fmt::Debug::fmt(&self.bits, f)
+    }
+}
+
+impl<FI> PartialEq<FI> for FieldReader<FI>
+where
+    FI: FieldSpec + Copy,
+{
+    #[inline(always)]
+    fn eq(&self, other: &FI) -> bool {
+        self.bits.eq(&FI::Ux::from(*other))
+    }
+}
+
+impl<FI> PartialEq<FI> for BitReader<FI>
+where
+    FI: Copy,
+    bool: From<FI>,
+{
+    #[inline(always)]
+    fn eq(&self, other: &FI) -> bool {
+        self.bits.eq(&bool::from(*other))
+    }
+}
+
+impl<FI> BitReader<FI> {
+    /// Value of the field as raw bits.
+    #[inline(always)]
+    pub const fn bit(&self) -> bool {
+        self.bits
+    }
+    /// Returns `true` if the bit is clear (0).
+    #[inline(always)]
+    pub const fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    /// Returns `true` if the bit is set (1).
+    #[inline(always)]
+    pub const fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+
+impl<FI> core::fmt::Debug for BitReader<FI> {
+    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
+        core::fmt::Debug::fmt(&self.bits, f)
+    }
+}
+
+/// Marker for register/field writers which can take any value of specified width
+pub struct Safe;
+/// You should check that value is allowed to pass to register/field writer marked with this
+pub struct Unsafe;
+/// Marker for field writers are safe to write in specified inclusive range
+pub struct Range<const MIN: u64, const MAX: u64>;
+/// Marker for field writers are safe to write in specified inclusive range
+pub struct RangeFrom<const MIN: u64>;
+/// Marker for field writers are safe to write in specified inclusive range
+pub struct RangeTo<const MAX: u64>;
+
+/// Write field Proxy
+pub type FieldWriter<'a, REG, const WI: u8, FI = u8, Safety = Unsafe> =
+    raw::FieldWriter<'a, REG, WI, FI, Safety>;
+
+impl<REG, const WI: u8, FI, Safety> FieldWriter<'_, REG, WI, FI, Safety>
+where
+    REG: Writable + RegisterSpec,
+    FI: FieldSpec,
+{
+    /// Field width
+    pub const WIDTH: u8 = WI;
+
+    /// Field width
+    #[inline(always)]
+    pub const fn width(&self) -> u8 {
+        WI
+    }
+
+    /// Field offset
+    #[inline(always)]
+    pub const fn offset(&self) -> u8 {
+        self.o
+    }
+}
+
+impl<'a, REG, const WI: u8, FI, Safety> FieldWriter<'a, REG, WI, FI, Safety>
+where
+    REG: Writable + RegisterSpec,
+    FI: FieldSpec,
+    REG::Ux: From<FI::Ux>,
+{
+    /// Writes raw bits to the field
+    ///
+    /// # Safety
+    ///
+    /// Passing incorrect value can cause undefined behaviour. See reference manual
+    #[inline(always)]
+    pub unsafe fn bits(self, value: FI::Ux) -> &'a mut W<REG> {
+        self.w.bits &= !(REG::Ux::mask::<WI>() << self.o);
+        self.w.bits |= (REG::Ux::from(value) & REG::Ux::mask::<WI>()) << self.o;
+        self.w
+    }
+}
+
+impl<'a, REG, const WI: u8, FI> FieldWriter<'a, REG, WI, FI, Safe>
+where
+    REG: Writable + RegisterSpec,
+    FI: FieldSpec,
+    REG::Ux: From<FI::Ux>,
+{
+    /// Writes raw bits to the field
+    #[inline(always)]
+    pub fn set(self, value: FI::Ux) -> &'a mut W<REG> {
+        unsafe { self.bits(value) }
+    }
+}
+
+impl<'a, REG, const WI: u8, FI, const MIN: u64, const MAX: u64>
+    FieldWriter<'a, REG, WI, FI, Range<MIN, MAX>>
+where
+    REG: Writable + RegisterSpec,
+    FI: FieldSpec,
+    REG::Ux: From<FI::Ux>,
+    u64: From<FI::Ux>,
+{
+    /// Writes raw bits to the field
+    #[inline(always)]
+    pub fn set(self, value: FI::Ux) -> &'a mut W<REG> {
+        {
+            let value = u64::from(value);
+            assert!(value >= MIN && value <= MAX);
+        }
+        unsafe { self.bits(value) }
+    }
+}
+
+impl<'a, REG, const WI: u8, FI, const MIN: u64> FieldWriter<'a, REG, WI, FI, RangeFrom<MIN>>
+where
+    REG: Writable + RegisterSpec,
+    FI: FieldSpec,
+    REG::Ux: From<FI::Ux>,
+    u64: From<FI::Ux>,
+{
+    /// Writes raw bits to the field
+    #[inline(always)]
+    pub fn set(self, value: FI::Ux) -> &'a mut W<REG> {
+        {
+            let value = u64::from(value);
+            assert!(value >= MIN);
+        }
+        unsafe { self.bits(value) }
+    }
+}
+
+impl<'a, REG, const WI: u8, FI, const MAX: u64> FieldWriter<'a, REG, WI, FI, RangeTo<MAX>>
+where
+    REG: Writable + RegisterSpec,
+    FI: FieldSpec,
+    REG::Ux: From<FI::Ux>,
+    u64: From<FI::Ux>,
+{
+    /// Writes raw bits to the field
+    #[inline(always)]
+    pub fn set(self, value: FI::Ux) -> &'a mut W<REG> {
+        {
+            let value = u64::from(value);
+            assert!(value <= MAX);
+        }
+        unsafe { self.bits(value) }
+    }
+}
+
+impl<'a, REG, const WI: u8, FI, Safety> FieldWriter<'a, REG, WI, FI, Safety>
+where
+    REG: Writable + RegisterSpec,
+    FI: IsEnum,
+    REG::Ux: From<FI::Ux>,
+{
+    /// Writes `variant` to the field
+    #[inline(always)]
+    pub fn variant(self, variant: FI) -> &'a mut W<REG> {
+        unsafe { self.bits(FI::Ux::from(variant)) }
+    }
+}
+
+macro_rules! bit_proxy {
+    ($writer:ident, $mwv:ident) => {
+        #[doc(hidden)]
+        pub struct $mwv;
+
+        /// Bit-wise write field proxy
+        pub type $writer<'a, REG, FI = bool> = raw::BitWriter<'a, REG, FI, $mwv>;
+
+        impl<'a, REG, FI> $writer<'a, REG, FI>
+        where
+            REG: Writable + RegisterSpec,
+            bool: From<FI>,
+        {
+            /// Field width
+            pub const WIDTH: u8 = 1;
+
+            /// Field width
+            #[inline(always)]
+            pub const fn width(&self) -> u8 {
+                Self::WIDTH
+            }
+
+            /// Field offset
+            #[inline(always)]
+            pub const fn offset(&self) -> u8 {
+                self.o
+            }
+
+            /// Writes bit to the field
+            #[inline(always)]
+            pub fn bit(self, value: bool) -> &'a mut W<REG> {
+                self.w.bits &= !(REG::Ux::ONE << self.o);
+                self.w.bits |= (REG::Ux::from(value) & REG::Ux::ONE) << self.o;
+                self.w
+            }
+            /// Writes `variant` to the field
+            #[inline(always)]
+            pub fn variant(self, variant: FI) -> &'a mut W<REG> {
+                self.bit(bool::from(variant))
+            }
+        }
+    };
+}
+
+bit_proxy!(BitWriter, BitM);
+bit_proxy!(BitWriter1S, Bit1S);
+bit_proxy!(BitWriter0C, Bit0C);
+bit_proxy!(BitWriter1C, Bit1C);
+bit_proxy!(BitWriter0S, Bit0S);
+bit_proxy!(BitWriter1T, Bit1T);
+bit_proxy!(BitWriter0T, Bit0T);
+
+impl<'a, REG, FI> BitWriter<'a, REG, FI>
+where
+    REG: Writable + RegisterSpec,
+    bool: From<FI>,
+{
+    /// Sets the field bit
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W<REG> {
+        self.w.bits |= REG::Ux::ONE << self.o;
+        self.w
+    }
+    /// Clears the field bit
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W<REG> {
+        self.w.bits &= !(REG::Ux::ONE << self.o);
+        self.w
+    }
+}
+
+impl<'a, REG, FI> BitWriter1S<'a, REG, FI>
+where
+    REG: Writable + RegisterSpec,
+    bool: From<FI>,
+{
+    /// Sets the field bit
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W<REG> {
+        self.w.bits |= REG::Ux::ONE << self.o;
+        self.w
+    }
+}
+
+impl<'a, REG, FI> BitWriter0C<'a, REG, FI>
+where
+    REG: Writable + RegisterSpec,
+    bool: From<FI>,
+{
+    /// Clears the field bit
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W<REG> {
+        self.w.bits &= !(REG::Ux::ONE << self.o);
+        self.w
+    }
+}
+
+impl<'a, REG, FI> BitWriter1C<'a, REG, FI>
+where
+    REG: Writable + RegisterSpec,
+    bool: From<FI>,
+{
+    ///Clears the field bit by passing one
+    #[inline(always)]
+    pub fn clear_bit_by_one(self) -> &'a mut W<REG> {
+        self.w.bits |= REG::Ux::ONE << self.o;
+        self.w
+    }
+}
+
+impl<'a, REG, FI> BitWriter0S<'a, REG, FI>
+where
+    REG: Writable + RegisterSpec,
+    bool: From<FI>,
+{
+    ///Sets the field bit by passing zero
+    #[inline(always)]
+    pub fn set_bit_by_zero(self) -> &'a mut W<REG> {
+        self.w.bits &= !(REG::Ux::ONE << self.o);
+        self.w
+    }
+}
+
+impl<'a, REG, FI> BitWriter1T<'a, REG, FI>
+where
+    REG: Writable + RegisterSpec,
+    bool: From<FI>,
+{
+    ///Toggle the field bit by passing one
+    #[inline(always)]
+    pub fn toggle_bit(self) -> &'a mut W<REG> {
+        self.w.bits |= REG::Ux::ONE << self.o;
+        self.w
+    }
+}
+
+impl<'a, REG, FI> BitWriter0T<'a, REG, FI>
+where
+    REG: Writable + RegisterSpec,
+    bool: From<FI>,
+{
+    ///Toggle the field bit by passing zero
+    #[inline(always)]
+    pub fn toggle_bit(self) -> &'a mut W<REG> {
+        self.w.bits &= !(REG::Ux::ONE << self.o);
+        self.w
+    }
+}
+
+/// This structure provides volatile access to registers.
+#[repr(transparent)]
+pub struct Reg<REG: RegisterSpec> {
+    register: vcell::VolatileCell<REG::Ux>,
+    _marker: marker::PhantomData<REG>,
+}
+
+unsafe impl<REG: RegisterSpec> Send for Reg<REG> where REG::Ux: Send {}
+
+impl<REG: RegisterSpec> Reg<REG> {
+    /// Returns the underlying memory address of register.
+    ///
+    /// ```ignore
+    /// let reg_ptr = periph.reg.as_ptr();
+    /// ```
+    #[inline(always)]
+    pub fn as_ptr(&self) -> *mut REG::Ux {
+        self.register.as_ptr()
+    }
+}
+
+impl<REG: Readable> Reg<REG> {
+    /// Reads the contents of a `Readable` register.
+    ///
+    /// You can read the raw contents of a register by using `bits`:
+    /// ```ignore
+    /// let bits = periph.reg.read().bits();
+    /// ```
+    /// or get the content of a particular field of a register:
+    /// ```ignore
+    /// let reader = periph.reg.read();
+    /// let bits = reader.field1().bits();
+    /// let flag = reader.field2().bit_is_set();
+    /// ```
+    #[inline(always)]
+    pub fn read(&self) -> R<REG> {
+        R {
+            bits: self.register.get(),
+            _reg: marker::PhantomData,
+        }
+    }
+}
+
+impl<REG: Resettable + Writable> Reg<REG> {
+    /// Writes the reset value to `Writable` register.
+    ///
+    /// Resets the register to its initial state.
+    #[inline(always)]
+    pub fn reset(&self) {
+        self.register.set(REG::RESET_VALUE)
+    }
+
+    /// Writes bits to a `Writable` register.
+    ///
+    /// You can write raw bits into a register:
+    /// ```ignore
+    /// periph.reg.write(|w| unsafe { w.bits(rawbits) });
+    /// ```
+    /// or write only the fields you need:
+    /// ```ignore
+    /// periph.reg.write(|w| w
+    ///     .field1().bits(newfield1bits)
+    ///     .field2().set_bit()
+    ///     .field3().variant(VARIANT)
+    /// );
+    /// ```
+    /// or an alternative way of saying the same:
+    /// ```ignore
+    /// periph.reg.write(|w| {
+    ///     w.field1().bits(newfield1bits);
+    ///     w.field2().set_bit();
+    ///     w.field3().variant(VARIANT)
+    /// });
+    /// ```
+    /// In the latter case, other fields will be set to their reset value.
+    #[inline(always)]
+    pub fn write<F>(&self, f: F) -> REG::Ux
+    where
+        F: FnOnce(&mut W<REG>) -> &mut W<REG>,
+    {
+        let value = f(&mut W {
+            bits: REG::RESET_VALUE & !REG::ONE_TO_MODIFY_FIELDS_BITMAP
+                | REG::ZERO_TO_MODIFY_FIELDS_BITMAP,
+            _reg: marker::PhantomData,
+        })
+        .bits;
+        self.register.set(value);
+        value
+    }
+
+    /// Writes bits to a `Writable` register and produce a value.
+    ///
+    /// You can write raw bits into a register:
+    /// ```ignore
+    /// periph.reg.write_and(|w| unsafe { w.bits(rawbits); });
+    /// ```
+    /// or write only the fields you need:
+    /// ```ignore
+    /// periph.reg.write_and(|w| {
+    ///     w.field1().bits(newfield1bits)
+    ///         .field2().set_bit()
+    ///         .field3().variant(VARIANT);
+    /// });
+    /// ```
+    /// or an alternative way of saying the same:
+    /// ```ignore
+    /// periph.reg.write_and(|w| {
+    ///     w.field1().bits(newfield1bits);
+    ///     w.field2().set_bit();
+    ///     w.field3().variant(VARIANT);
+    /// });
+    /// ```
+    /// In the latter case, other fields will be set to their reset value.
+    ///
+    /// Values can be returned from the closure:
+    /// ```ignore
+    /// let state = periph.reg.write_and(|w| State::set(w.field1()));
+    /// ```
+    #[inline(always)]
+    pub fn from_write<F, T>(&self, f: F) -> T
+    where
+        F: FnOnce(&mut W<REG>) -> T,
+    {
+        let mut writer = W {
+            bits: REG::RESET_VALUE & !REG::ONE_TO_MODIFY_FIELDS_BITMAP
+                | REG::ZERO_TO_MODIFY_FIELDS_BITMAP,
+            _reg: marker::PhantomData,
+        };
+        let result = f(&mut writer);
+
+        self.register.set(writer.bits);
+
+        result
+    }
+}
+
+impl<REG: Writable> Reg<REG> {
+    /// Writes 0 to a `Writable` register.
+    ///
+    /// Similar to `write`, but unused bits will contain 0.
+    ///
+    /// # Safety
+    ///
+    /// Unsafe to use with registers which don't allow to write 0.
+    #[inline(always)]
+    pub unsafe fn write_with_zero<F>(&self, f: F) -> REG::Ux
+    where
+        F: FnOnce(&mut W<REG>) -> &mut W<REG>,
+    {
+        let value = f(&mut W {
+            bits: REG::Ux::ZERO,
+            _reg: marker::PhantomData,
+        })
+        .bits;
+        self.register.set(value);
+        value
+    }
+
+    /// Writes 0 to a `Writable` register and produces a value.
+    ///
+    /// Similar to `write`, but unused bits will contain 0.
+    ///
+    /// # Safety
+    ///
+    /// Unsafe to use with registers which don't allow to write 0.
+    #[inline(always)]
+    pub unsafe fn from_write_with_zero<F, T>(&self, f: F) -> T
+    where
+        F: FnOnce(&mut W<REG>) -> T,
+    {
+        let mut writer = W {
+            bits: REG::Ux::ZERO,
+            _reg: marker::PhantomData,
+        };
+
+        let result = f(&mut writer);
+
+        self.register.set(writer.bits);
+
+        result
+    }
+}
+
+impl<REG: Readable + Writable> Reg<REG> {
+    /// Modifies the contents of the register by reading and then writing it.
+    ///
+    /// E.g. to do a read-modify-write sequence to change parts of a register:
+    /// ```ignore
+    /// periph.reg.modify(|r, w| unsafe { w.bits(
+    ///    r.bits() | 3
+    /// ) });
+    /// ```
+    /// or
+    /// ```ignore
+    /// periph.reg.modify(|_, w| w
+    ///     .field1().bits(newfield1bits)
+    ///     .field2().set_bit()
+    ///     .field3().variant(VARIANT)
+    /// );
+    /// ```
+    /// or an alternative way of saying the same:
+    /// ```ignore
+    /// periph.reg.modify(|_, w| {
+    ///     w.field1().bits(newfield1bits);
+    ///     w.field2().set_bit();
+    ///     w.field3().variant(VARIANT)
+    /// });
+    /// ```
+    /// Other fields will have the value they had before the call to `modify`.
+    #[inline(always)]
+    pub fn modify<F>(&self, f: F) -> REG::Ux
+    where
+        for<'w> F: FnOnce(&R<REG>, &'w mut W<REG>) -> &'w mut W<REG>,
+    {
+        let bits = self.register.get();
+        let value = f(
+            &R {
+                bits,
+                _reg: marker::PhantomData,
+            },
+            &mut W {
+                bits: bits & !REG::ONE_TO_MODIFY_FIELDS_BITMAP | REG::ZERO_TO_MODIFY_FIELDS_BITMAP,
+                _reg: marker::PhantomData,
+            },
+        )
+        .bits;
+        self.register.set(value);
+        value
+    }
+
+    /// Modifies the contents of the register by reading and then writing it
+    /// and produces a value.
+    ///
+    /// E.g. to do a read-modify-write sequence to change parts of a register:
+    /// ```ignore
+    /// let bits = periph.reg.modify(|r, w| {
+    ///     let new_bits = r.bits() | 3;
+    ///     unsafe {
+    ///         w.bits(new_bits);
+    ///     }
+    ///
+    ///     new_bits
+    /// });
+    /// ```
+    /// or
+    /// ```ignore
+    /// periph.reg.modify(|_, w| {
+    ///     w.field1().bits(newfield1bits)
+    ///         .field2().set_bit()
+    ///         .field3().variant(VARIANT);
+    /// });
+    /// ```
+    /// or an alternative way of saying the same:
+    /// ```ignore
+    /// periph.reg.modify(|_, w| {
+    ///     w.field1().bits(newfield1bits);
+    ///     w.field2().set_bit();
+    ///     w.field3().variant(VARIANT);
+    /// });
+    /// ```
+    /// Other fields will have the value they had before the call to `modify`.
+    #[inline(always)]
+    pub fn from_modify<F, T>(&self, f: F) -> T
+    where
+        for<'w> F: FnOnce(&R<REG>, &'w mut W<REG>) -> T,
+    {
+        let bits = self.register.get();
+
+        let mut writer = W {
+            bits: bits & !REG::ONE_TO_MODIFY_FIELDS_BITMAP | REG::ZERO_TO_MODIFY_FIELDS_BITMAP,
+            _reg: marker::PhantomData,
+        };
+
+        let result = f(
+            &R {
+                bits,
+                _reg: marker::PhantomData,
+            },
+            &mut writer,
+        );
+
+        self.register.set(writer.bits);
+
+        result
+    }
+}
+
+impl<REG: Readable> core::fmt::Debug for crate::generic::Reg<REG>
+where
+    R<REG>: core::fmt::Debug,
+{
+    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
+        core::fmt::Debug::fmt(&self.read(), f)
+    }
+}
+
+#[cfg(feature = "atomics")]
+
+mod atomic {
+    use super::*;
+    use portable_atomic::Ordering;
+
+    pub trait AtomicOperations {
+        unsafe fn atomic_or(ptr: *mut Self, val: Self);
+        unsafe fn atomic_and(ptr: *mut Self, val: Self);
+        unsafe fn atomic_xor(ptr: *mut Self, val: Self);
+    }
+
+    macro_rules! impl_atomics {
+        ($U:ty, $Atomic:ty) => {
+            impl AtomicOperations for $U {
+                unsafe fn atomic_or(ptr: *mut Self, val: Self) {
+                    (*(ptr as *const $Atomic)).or(val, Ordering::SeqCst);
+                }
+
+                unsafe fn atomic_and(ptr: *mut Self, val: Self) {
+                    (*(ptr as *const $Atomic)).and(val, Ordering::SeqCst);
+                }
+
+                unsafe fn atomic_xor(ptr: *mut Self, val: Self) {
+                    (*(ptr as *const $Atomic)).xor(val, Ordering::SeqCst);
+                }
+            }
+        };
+    }
+
+    impl_atomics!(u8, portable_atomic::AtomicU8);
+    impl_atomics!(u16, portable_atomic::AtomicU16);
+
+    // Exclude 16-bit archs from 32-bit atomics
+    #[cfg(not(target_pointer_width = "16"))]
+    impl_atomics!(u32, portable_atomic::AtomicU32);
+
+    // Enable 64-bit atomics for 64-bit RISCV
+    #[cfg(any(target_pointer_width = "64", target_has_atomic = "64"))]
+    impl_atomics!(u64, portable_atomic::AtomicU64);
+
+    impl<REG: Readable + Writable> Reg<REG>
+    where
+        REG::Ux: AtomicOperations,
+    {
+        /// Set high every bit in the register that was set in the write proxy. Leave other bits
+        /// untouched. The write is done in a single atomic instruction.
+        ///
+        /// # Safety
+        ///
+        /// The resultant bit pattern may not be valid for the register.
+        #[inline(always)]
+        pub unsafe fn set_bits<F>(&self, f: F)
+        where
+            F: FnOnce(&mut W<REG>) -> &mut W<REG>,
+        {
+            let bits = f(&mut W {
+                bits: REG::Ux::ZERO,
+                _reg: marker::PhantomData,
+            })
+            .bits;
+            REG::Ux::atomic_or(self.register.as_ptr(), bits);
+        }
+
+        /// Clear every bit in the register that was cleared in the write proxy. Leave other bits
+        /// untouched. The write is done in a single atomic instruction.
+        ///
+        /// # Safety
+        ///
+        /// The resultant bit pattern may not be valid for the register.
+        #[inline(always)]
+        pub unsafe fn clear_bits<F>(&self, f: F)
+        where
+            F: FnOnce(&mut W<REG>) -> &mut W<REG>,
+        {
+            let bits = f(&mut W {
+                bits: !REG::Ux::ZERO,
+                _reg: marker::PhantomData,
+            })
+            .bits;
+            REG::Ux::atomic_and(self.register.as_ptr(), bits);
+        }
+
+        /// Toggle every bit in the register that was set in the write proxy. Leave other bits
+        /// untouched. The write is done in a single atomic instruction.
+        ///
+        /// # Safety
+        ///
+        /// The resultant bit pattern may not be valid for the register.
+        #[inline(always)]
+        pub unsafe fn toggle_bits<F>(&self, f: F)
+        where
+            F: FnOnce(&mut W<REG>) -> &mut W<REG>,
+        {
+            let bits = f(&mut W {
+                bits: REG::Ux::ZERO,
+                _reg: marker::PhantomData,
+            })
+            .bits;
+            REG::Ux::atomic_xor(self.register.as_ptr(), bits);
+        }
+    }
+}
+

### external/vendor/stm32u5/src/lib.rs
@@ -0,0 +1,49 @@
+//! Peripheral access API for STM32U5 microcontrollers
+//! (generated using [svd2rust](https://github.com/rust-embedded/svd2rust)
+//! 0.36.1)
+//!
+//! You can find an overview of the API here:
+//! [svd2rust/#peripheral-api](https://docs.rs/svd2rust/0.36.1/svd2rust/#peripheral-api)
+//!
+//! For more details see the README here:
+//! [stm32-rs](https://github.com/stm32-rs/stm32-rs)
+//!
+//! This crate supports all STM32U5 devices; for the complete list please
+//! see:
+//! [stm32u5](https://crates.io/crates/stm32u5)
+//!
+//! Due to doc build limitations, not all devices may be shown on docs.rs;
+//! a representative few have been selected instead. For a complete list of
+//! available registers and fields see: [stm32-rs Device Coverage](https://stm32-rs.github.io/stm32-rs/)
+
+#![allow(non_camel_case_types)]
+#![allow(non_snake_case)]
+#![no_std]
+
+mod generic;
+pub use self::generic::*;
+
+#[cfg(feature = "stm32u535")]
+pub mod stm32u535;
+
+#[cfg(feature = "stm32u545")]
+pub mod stm32u545;
+
+#[cfg(feature = "stm32u575")]
+pub mod stm32u575;
+
+#[cfg(feature = "stm32u585")]
+pub mod stm32u585;
+
+#[cfg(feature = "stm32u595")]
+pub mod stm32u595;
+
+#[cfg(feature = "stm32u599")]
+pub mod stm32u599;
+
+#[cfg(feature = "stm32u5a5")]
+pub mod stm32u5a5;
+
+#[cfg(feature = "stm32u5a9")]
+pub mod stm32u5a9;
+

### external/vendor/stm32u5/src/stm32u535/adc1.rs
@@ -0,0 +1,516 @@
+#[repr(C)]
+#[derive(Debug)]
+///Register block
+pub struct RegisterBlock {
+    isr: ISR,
+    ier: IER,
+    cr: CR,
+    cfgr1: CFGR1,
+    cfgr2: CFGR2,
+    smpr1: SMPR1,
+    smpr2: SMPR2,
+    pcsel: PCSEL,
+    _reserved8: [u8; 0x10],
+    sqr1: SQR1,
+    sqr2: SQR2,
+    sqr3: SQR3,
+    sqr4: SQR4,
+    dr: DR,
+    _reserved13: [u8; 0x08],
+    jsqr: JSQR,
+    _reserved14: [u8; 0x10],
+    ofr: [OFR; 4],
+    gcomp: GCOMP,
+    _reserved16: [u8; 0x0c],
+    jdr: [JDR; 4],
+    _reserved17: [u8; 0x10],
+    awd2cr: AWD2CR,
+    awd3cr: AWD3CR,
+    ltr1: LTR1,
+    htr1: HTR1,
+    ltr2: LTR2,
+    htr2: HTR2,
+    ltr3: LTR3,
+    htr3: HTR3,
+    difsel: DIFSEL,
+    calfact: CALFACT,
+    calfact2: CALFACT2,
+}
+impl RegisterBlock {
+    ///0x00 - ADC interrupt and status register
+    #[inline(always)]
+    pub const fn isr(&self) -> &ISR {
+        &self.isr
+    }
+    ///0x04 - ADC interrupt enable register
+    #[inline(always)]
+    pub const fn ier(&self) -> &IER {
+        &self.ier
+    }
+    ///0x08 - ADC control register
+    #[inline(always)]
+    pub const fn cr(&self) -> &CR {
+        &self.cr
+    }
+    ///0x0c - ADC configuration register
+    #[inline(always)]
+    pub const fn cfgr1(&self) -> &CFGR1 {
+        &self.cfgr1
+    }
+    ///0x10 - ADC configuration register 2
+    #[inline(always)]
+    pub const fn cfgr2(&self) -> &CFGR2 {
+        &self.cfgr2
+    }
+    ///0x14 - ADC sample time register 1
+    #[inline(always)]
+    pub const fn smpr1(&self) -> &SMPR1 {
+        &self.smpr1
+    }
+    ///0x18 - ADC sample time register 2
+    #[inline(always)]
+    pub const fn smpr2(&self) -> &SMPR2 {
+        &self.smpr2
+    }
+    ///0x1c - ADC channel preselection register
+    #[inline(always)]
+    pub const fn pcsel(&self) -> &PCSEL {
+        &self.pcsel
+    }
+    ///0x30 - ADC regular sequence register 1
+    #[inline(always)]
+    pub const fn sqr1(&self) -> &SQR1 {
+        &self.sqr1
+    }
+    ///0x34 - ADC regular sequence register 2
+    #[inline(always)]
+    pub const fn sqr2(&self) -> &SQR2 {
+        &self.sqr2
+    }
+    ///0x38 - ADC regular sequence register 3
+    #[inline(always)]
+    pub const fn sqr3(&self) -> &SQR3 {
+        &self.sqr3
+    }
+    ///0x3c - ADC regular sequence register 4
+    #[inline(always)]
+    pub const fn sqr4(&self) -> &SQR4 {
+        &self.sqr4
+    }
+    ///0x40 - ADC regular Data Register
+    #[inline(always)]
+    pub const fn dr(&self) -> &DR {
+        &self.dr
+    }
+    ///0x4c - ADC injected sequence register
+    #[inline(always)]
+    pub const fn jsqr(&self) -> &JSQR {
+        &self.jsqr
+    }
+    ///0x60..0x70 - ADC offset register
+    ///
+    ///<div class="warning">`n` is the index of register in the array. `n == 0` corresponds to `OFR1` register.</div>
+    #[inline(always)]
+    pub const fn ofr(&self, n: usize) -> &OFR {
+        &self.ofr[n]
+    }
+    ///Iterator for array of:
+    ///0x60..0x70 - ADC offset register
+    #[inline(always)]
+    pub fn ofr_iter(&self) -> impl Iterator<Item = &OFR> {
+        self.ofr.iter()
+    }
+    ///0x60 - ADC offset register
+    #[inline(always)]
+    pub const fn ofr1(&self) -> &OFR {
+        self.ofr(0)
+    }
+    ///0x64 - ADC offset register
+    #[inline(always)]
+    pub const fn ofr2(&self) -> &OFR {
+        self.ofr(1)
+    }
+    ///0x68 - ADC offset register
+    #[inline(always)]
+    pub const fn ofr3(&self) -> &OFR {
+        self.ofr(2)
+    }
+    ///0x6c - ADC offset register
+    #[inline(always)]
+    pub const fn ofr4(&self) -> &OFR {
+        self.ofr(3)
+    }
+    ///0x70 - ADC gain compensation register
+    #[inline(always)]
+    pub const fn gcomp(&self) -> &GCOMP {
+        &self.gcomp
+    }
+    ///0x80..0x90 - ADC injected data register
+    ///
+    ///<div class="warning">`n` is the index of register in the array. `n == 0` corresponds to `JDR1` register.</div>
+    #[inline(always)]
+    pub const fn jdr(&self, n: usize) -> &JDR {
+        &self.jdr[n]
+    }
+    ///Iterator for array of:
+    ///0x80..0x90 - ADC injected data register
+    #[inline(always)]
+    pub fn jdr_iter(&self) -> impl Iterator<Item = &JDR> {
+        self.jdr.iter()
+    }
+    ///0x80 - ADC injected data register
+    #[inline(always)]
+    pub const fn jdr1(&self) -> &JDR {
+        self.jdr(0)
+    }
+    ///0x84 - ADC injected data register
+    #[inline(always)]
+    pub const fn jdr2(&self) -> &JDR {
+        self.jdr(1)
+    }
+    ///0x88 - ADC injected data register
+    #[inline(always)]
+    pub const fn jdr3(&self) -> &JDR {
+        self.jdr(2)
+    }
+    ///0x8c - ADC injected data register
+    #[inline(always)]
+    pub const fn jdr4(&self) -> &JDR {
+        self.jdr(3)
+    }
+    ///0xa0 - ADC analog watchdog 2 configuration register
+    #[inline(always)]
+    pub const fn awd2cr(&self) -> &AWD2CR {
+        &self.awd2cr
+    }
+    ///0xa4 - ADC analog watchdog 3 configuration register
+    #[inline(always)]
+    pub const fn awd3cr(&self) -> &AWD3CR {
+        &self.awd3cr
+    }
+    ///0xa8 - ADC watchdog threshold register 1
+    #[inline(always)]
+    pub const fn ltr1(&self) -> &LTR1 {
+        &self.ltr1
+    }
+    ///0xac - ADC watchdog threshold register 1
+    #[inline(always)]
+    pub const fn htr1(&self) -> &HTR1 {
+        &self.htr1
+    }
+    ///0xb0 - ADC watchdog lower threshold register 2
+    #[inline(always)]
+    pub const fn ltr2(&self) -> &LTR2 {
+        &self.ltr2
+    }
+    ///0xb4 - ADC watchdog higher threshold register 2
+    #[inline(always)]
+    pub const fn htr2(&self) -> &HTR2 {
+        &self.htr2
+    }
+    ///0xb8 - ADC watchdog lower threshold register 3
+    #[inline(always)]
+    pub const fn ltr3(&self) -> &LTR3 {
+        &self.ltr3
+    }
+    ///0xbc - ADC watchdog higher threshold register 3
+    #[inline(always)]
+    pub const fn htr3(&self) -> &HTR3 {
+        &self.htr3
+    }
+    ///0xc0 - ADC differential mode selection register
+    #[inline(always)]
+    pub const fn difsel(&self) -> &DIFSEL {
+        &self.difsel
+    }
+    ///0xc4 - ADC user control register
+    #[inline(always)]
+    pub const fn calfact(&self) -> &CALFACT {
+        &self.calfact
+    }
+    ///0xc8 - ADC calibration factor register
+    #[inline(always)]
+    pub const fn calfact2(&self) -> &CALFACT2 {
+        &self.calfact2
+    }
+}
+/**ISR (rw) register accessor: ADC interrupt and status register
+
+You can [`read`](crate::Reg::read) this register and get [`isr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`isr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
+
+See register [structure](https://stm32-rs.github.io/stm32-rs/STM32U535.html#ADC1:ISR)
+
+For information about available fields see [`mod@isr`] module*/
+pub type ISR = crate::Reg<isr::ISRrs>;
+///ADC interrupt and status register
+pub mod isr;
+/**IER (rw) register accessor: ADC interrupt enable register
+
+You can [`read`](crate::Reg::read) this register and get [`ier::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ier::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
+
+See register [structure](https://stm32-rs.github.io/stm32-rs/STM32U535.html#ADC1:IER)
+
+For information about available fields see [`mod@ier`] module*/
+pub type IER = crate::Reg<ier::IERrs>;
+///ADC interrupt enable register
+pub mod ier;
+/**CR (rw) register accessor: ADC control register
+
+You can [`read`](crate::Reg::read) this register and get [`cr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
+
+See register [structure](https://stm32-rs.github.io/stm32-rs/STM32U535.html#ADC1:CR)
+
+For information about available fields see [`mod@cr`] module*/
+pub type CR = crate::Reg<cr::CRrs>;
+///ADC control register
+pub mod cr;
+/**CFGR1 (rw) register accessor: ADC configuration register
+
+You can [`read`](crate::Reg::read) this register and get [`cfgr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfgr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
+
+See register [structure](https://stm32-rs.github.io/stm32-rs/STM32U535.html#ADC1:CFGR1)
+
+For information about available fields see [`mod@cfgr1`] module*/
+pub type CFGR1 = crate::Reg<cfgr1::CFGR1rs>;
+///ADC configuration register
+pub mod cfgr1;
+/**CFGR2 (rw) register accessor: ADC configuration register 2
+
+You can [`read`](crate::Reg::read) this register and get [`cfgr2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfgr2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
+
+See register [structure](https://stm32-rs.github.io/stm32-rs/STM32U535.html#ADC1:CFGR2)
+
+For information about available fields see [`mod@cfgr2`] module*/
+pub type CFGR2 = crate::Reg<cfgr2::CFGR2rs>;
+///ADC configuration register 2
+pub mod cfgr2;
+/**SMPR1 (rw) register accessor: ADC sample time register 1
+
+You can [`read`](crate::Reg::read) this register and get [`smpr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`smpr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
+
+See register [structure](https://stm32-rs.github.io/stm32-rs/STM32U535.html#ADC1:SMPR1)
+
+For information about available fields see [`mod@smpr1`] module*/
+pub type SMPR1 = crate::Reg<smpr1::SMPR1rs>;
+///ADC sample time register 1
+pub mod smpr1;
+/**SMPR2 (rw) register accessor: ADC sample time register 2
+
+You can [`read`](crate::Reg::read) this register and get [`smpr2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`smpr2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
+
+See register [structure](https://stm32-rs.github.io/stm32-rs/STM32U535.html#ADC1:SMPR2)
+
+For information about available fields see [`mod@smpr2`] module*/
+pub type SMPR2 = crate::Reg<smpr2::SMPR2rs>;
+///ADC sample time register 2
+pub mod smpr2;
+/**PCSEL (rw) register accessor: ADC channel preselection register
+
+You can [`read`](crate::Reg::read) this register and get [`pcsel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcsel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
+
+See register [structure](https://stm32-rs.github.io/stm32-rs/STM32U535.html#ADC1:PCSEL)
+
+For information about available fields see [`mod@pcsel`] module*/
+pub type PCSEL = crate::Reg<pcsel::PCSELrs>;
+///ADC channel preselection register
+pub mod pcsel;
+/**SQR1 (rw) register accessor: ADC regular sequence register 1
+
+You can [`read`](crate::Reg::read) this register and get [`sqr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sqr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
+
+See register [structure](https://stm32-rs.github.io/stm32-rs/STM32U535.html#ADC1:SQR1)
+
+For information about available fields see [`mod@sqr1`] module*/
+pub type SQR1 = crate::Reg<sqr1::SQR1rs>;
+///ADC regular sequence register 1
+pub mod sqr1;
+/**SQR2 (rw) register accessor: ADC regular sequence register 2
+
+You can [`read`](crate::Reg::read) this register and get [`sqr2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sqr2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
+
+See register [structure](https://stm32-rs.github.io/stm32-rs/STM32U535.html#ADC1:SQR2)
+
+For information about available fields see [`mod@sqr2`] module*/
+pub type SQR2 = crate::Reg<sqr2::SQR2rs>;
+///ADC regular sequence register 2
+pub mod sqr2;
+/**SQR3 (rw) register accessor: ADC regular sequence register 3
+
+You can [`read`](crate::Reg::read) this register and get [`sqr3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sqr3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
+
+See register [structure](https://stm32-rs.github.io/stm32-rs/STM32U535.html#ADC1:SQR3)
+
+For information about available fields see [`mod@sqr3`] module*/
+pub type SQR3 = crate::Reg<sqr3::SQR3rs>;
+///ADC regular sequence register 3
+pub mod sqr3;
+/**SQR4 (rw) register accessor: ADC regular sequence register 4
+
+You can [`read`](crate::Reg::read) this register and get [`sqr4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sqr4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
+
+See register [structure](https://stm32-rs.github.io/stm32-rs/STM32U535.html#ADC1:SQR4)
+
+For information about available fields see [`mod@sqr4`] module*/
+pub type SQR4 = crate::Reg<sqr4::SQR4rs>;
+///ADC regular sequence register 4
+pub mod sqr4;
+/**DR (r) register accessor: ADC regular Data Register
+
+You can [`read`](crate::Reg::read) this register and get [`dr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
+
+See register [structure](https://stm32-rs.github.io/stm32-rs/STM32U535.html#ADC1:DR)
+
+For information about available fields see [`mod@dr`] module*/
+pub type DR = crate::Reg<dr::DRrs>;
+///ADC regular Data Register
+pub mod dr;
+/**JSQR (rw) register accessor: ADC injected sequence register
+
+You can [`read`](crate::Reg::read) this register and get [`jsqr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`jsqr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
+
+See register [structure](https://stm32-rs.github.io/stm32-rs/STM32U535.html#ADC1:JSQR)
+
+For information about available fields see [`mod@jsqr`] module*/
+pub type JSQR = crate::Reg<jsqr::JSQRrs>;
+///ADC injected sequence register
+pub mod jsqr;
+/**OFR (rw) register accessor: ADC offset register
+
+You can [`read`](crate::Reg::read) this register and get [`ofr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ofr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
+
+See register [structure](https://stm32-rs.github.io/stm32-rs/STM32U535.html#ADC1:OFR[1])
+
+For information about available fields see [`mod@ofr`] module*/
+pub type OFR = crate::Reg<ofr::OFRrs>;
+///ADC offset register
+pub mod ofr;
+/**GCOMP (rw) register accessor: ADC gain compensation register
+
+You can [`read`](crate::Reg::read) this register and get [`gcomp::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gcomp::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
+
+See register [structure](https://stm32-rs.github.io/stm32-rs/STM32U535.html#ADC1:GCOMP)
+
+For information about available fields see [`mod@gcomp`] module*/
+pub type GCOMP = crate::Reg<gcomp::GCOMPrs>;
+///ADC gain compensation register
+pub mod gcomp;
+/**JDR (r) register accessor: ADC injected data register
+
+You can [`read`](crate::Reg::read) this register and get [`jdr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
+
+See register [structure](https://stm32-rs.github.io/stm32-rs/STM32U535.html#ADC1:JDR[1])
+
+For information about available fields see [`mod@jdr`] module*/
+pub type JDR = crate::Reg<jdr::JDRrs>;
+///ADC injected data register
+pub mod jdr;
+/**AWD2CR (rw) register accessor: ADC analog watchdog 2 configuration register
+
+You can [`read`](crate::Reg::read) this register and get [`awd2cr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`awd2cr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
+
+See register [structure](https://stm32-rs.github.io/stm32-rs/STM32U535.html#ADC1:AWD2CR)
+
+For information about available fields see [`mod@awd2cr`] module*/
+pub type AWD2CR = crate::Reg<awd2cr::AWD2CRrs>;
+///ADC analog watchdog 2 configuration register
+pub mod awd2cr;
+/**AWD3CR (rw) register accessor: ADC analog watchdog 3 configuration register
+
+You can [`read`](crate::Reg::read) this register and get [`awd3cr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`awd3cr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
+
+See register [structure](https://stm32-rs.github.io/stm32-rs/STM32U535.html#ADC1:AWD3CR)
+
+For information about available fields see [`mod@awd3cr`] module*/
+pub type AWD3CR = crate::Reg<awd3cr::AWD3CRrs>;
+///ADC analog watchdog 3 configuration register
+pub mod awd3cr;
+/**LTR1 (rw) register accessor: ADC watchdog threshold register 1
+
+You can [`read`](crate::Reg::read) this register and get [`ltr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ltr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
+
+See register [structure](https://stm32-rs.github.io/stm32-rs/STM32U535.html#ADC1:LTR1)
+
+For information about available fields see [`mod@ltr1`] module*/
+pub type LTR1 = crate::Reg<ltr1::LTR1rs>;
+///ADC watchdog threshold register 1
+pub mod ltr1;
+/**HTR1 (rw) register accessor: ADC watchdog threshold register 1
+
+You can [`read`](crate::Reg::read) this register and get [`htr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`htr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
+
+See register [structure](https://stm32-rs.github.io/stm32-rs/STM32U535.html#ADC1:HTR1)
+
+For information about available fields see [`mod@htr1`] module*/
+pub type HTR1 = crate::Reg<htr1::HTR1rs>;
+///ADC watchdog threshold register 1
+pub mod htr1;
+/**LTR2 (rw) register accessor: ADC watchdog lower threshold register 2
+
+You can [`read`](crate::Reg::read) this register and get [`ltr2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ltr2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
+
+See register [structure](https://stm32-rs.github.io/stm32-rs/STM32U535.html#ADC1:LTR2)
+
+For information about available fields see [`mod@ltr2`] module*/
+pub type LTR2 = crate::Reg<ltr2::LTR2rs>;
+///ADC watchdog lower threshold register 2
+pub mod ltr2;
+/**HTR2 (rw) register accessor: ADC watchdog higher threshold register 2
+
+You can [`read`](crate::Reg::read) this register and get [`htr2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`htr2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
+
+See register [structure](https://stm32-rs.github.io/stm32-rs/STM32U535.html#ADC1:HTR2)
+
+For information about available fields see [`mod@htr2`] module*/
+pub type HTR2 = crate::Reg<htr2::HTR2rs>;
+///ADC watchdog higher threshold register 2
+pub mod htr2;
+/**LTR3 (rw) register accessor: ADC watchdog lower threshold register 3
+
+You can [`read`](crate::Reg::read) this register and get [`ltr3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ltr3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
+
+See register [structure](https://stm32-rs.github.io/stm32-rs/STM32U535.html#ADC1:LTR3)
+
+For information about available fields see [`mod@ltr3`] module*/
+pub type LTR3 = crate::Reg<ltr3::LTR3rs>;
+///ADC watchdog lower threshold register 3
+pub mod ltr3;
+/**HTR3 (rw) register accessor: ADC watchdog higher threshold register 3
+
+You can [`read`](crate::Reg::read) this register and get [`htr3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`htr3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
+
+See register [structure](https://stm32-rs.github.io/stm32-rs/STM32U535.html#ADC1:HTR3)
+
+For information about available fields see [`mod@htr3`] module*/
+pub type HTR3 = crate::Reg<htr3::HTR3rs>;
+///ADC watchdog higher threshold register 3
+pub mod htr3;
+/**DIFSEL (rw) register accessor: ADC differential mode selection register
+
+You can [`read`](crate::Reg::read) this register and get [`difsel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`difsel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
+
+See register [structure](https://stm32-rs.github.io/stm32-rs/STM32U535.html#ADC1:DIFSEL)
+
+For information about available fields see [`mod@difsel`] module*/
+pub type DIFSEL = crate::Reg<difsel::DIFSELrs>;
+///ADC differential mode selection register
+pub mod difsel;
+/**CALFACT (rw) register accessor: ADC user control register
+
+You can [`read`](crate::Reg::read) this register and get [`calfact::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`calfact::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
+
+See register [structure](https://stm32-rs.github.io/stm32-rs/STM32U535.html#ADC1:CALFACT)
+
+For information about available fields see [`mod@calfact`] module*/
+pub type CALFACT = crate::Reg<calfact::CALFACTrs>;
+///ADC user control register
+pub mod calfact;
+/**CALFACT2 (rw) register accessor: ADC calibration factor register
+
+You can [`read`](crate::Reg::read) this register and get [`calfact2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`calfact2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
+
+See register [structure](https://stm32-rs.github.io/stm32-rs/STM32U535.html#ADC1:CALFACT2)
+
+For information about available fields see [`mod@calfact2`] module*/
+pub type CALFACT2 = crate::Reg<calfact2::CALFACT2rs>;
+///ADC calibration factor register
+pub mod calfact2;

### external/vendor/stm32u5/src/stm32u535/adc1/awd2cr.rs
@@ -0,0 +1,331 @@
+///Register `AWD2CR` reader
+pub type R = crate::R<AWD2CRrs>;
+///Register `AWD2CR` writer
+pub type W = crate::W<AWD2CRrs>;
+/**AWD2CH
+
+Value on reset: 0*/
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub enum AWD2CH {
+    ///0: ADC analog input channel x is not monitored by AWDy
+    Disabled = 0,
+    ///1: ADC analog input channel x is monitored by AWDy
+    Enabled = 1,
+}
+impl From<AWD2CH> for bool {
+    #[inline(always)]
+    fn from(variant: AWD2CH) -> Self {
+        variant as u8 != 0
+    }
+}
+///Field `AWD2CH(0-19)` reader - AWD2CH
+pub type AWD2CH_R = crate::BitReader<AWD2CH>;
+impl AWD2CH_R {
+    ///Get enumerated values variant
+    #[inline(always)]
+    pub const fn variant(&self) -> AWD2CH {
+        match self.bits {
+            false => AWD2CH::Disabled,
+            true => AWD2CH::Enabled,
+        }
+    }
+    ///ADC analog input channel x is not monitored by AWDy
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == AWD2CH::Disabled
+    }
+    ///ADC analog input channel x is monitored by AWDy
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == AWD2CH::Enabled
+    }
+}
+///Field `AWD2CH(0-19)` writer - AWD2CH
+pub type AWD2CH_W<'a, REG> = crate::BitWriter<'a, REG, AWD2CH>;
+impl<'a, REG> AWD2CH_W<'a, REG>
+where
+    REG: crate::Writable + crate::RegisterSpec,
+{
+    ///ADC analog input channel x is not monitored by AWDy
+    #[inline(always)]
+    pub fn disabled(self) -> &'a mut crate::W<REG> {
+        self.variant(AWD2CH::Disabled)
+    }
+    ///ADC analog input channel x is monitored by AWDy
+    #[inline(always)]
+    pub fn enabled(self) -> &'a mut crate::W<REG> {
+        self.variant(AWD2CH::Enabled)
+    }
+}
+impl R {
+    ///AWD2CH
+    ///
+    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `AWD2CH0` field.</div>
+    #[inline(always)]
+    pub fn awd2ch(&self, n: u8) -> AWD2CH_R {
+        #[allow(clippy::no_effect)]
+        [(); 20][n as usize];
+        AWD2CH_R::new(((self.bits >> n) & 1) != 0)
+    }
+    ///Iterator for array of:
+    ///AWD2CH
+    #[inline(always)]
+    pub fn awd2ch_iter(&self) -> impl Iterator<Item = AWD2CH_R> + '_ {
+        (0..20).map(move |n| AWD2CH_R::new(((self.bits >> n) & 1) != 0))
+    }
+    ///Bit 0 - AWD2CH
+    #[inline(always)]
+    pub fn awd2ch0(&self) -> AWD2CH_R {
+        AWD2CH_R::new((self.bits & 1) != 0)
+    }
+    ///Bit 1 - AWD2CH
+    #[inline(always)]
+    pub fn awd2ch1(&self) -> AWD2CH_R {
+        AWD2CH_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    ///Bit 2 - AWD2CH
+    #[inline(always)]
+    pub fn awd2ch2(&self) -> AWD2CH_R {
+        AWD2CH_R::new(((self.bits >> 2) & 1) != 0)
+    }
+    ///Bit 3 - AWD2CH
+    #[inline(always)]
+    pub fn awd2ch3(&self) -> AWD2CH_R {
+        AWD2CH_R::new(((self.bits >> 3) & 1) != 0)
+    }
+    ///Bit 4 - AWD2CH
+    #[inline(always)]
+    pub fn awd2ch4(&self) -> AWD2CH_R {
+        AWD2CH_R::new(((self.bits >> 4) & 1) != 0)
+    }
+    ///Bit 5 - AWD2CH
+    #[inline(always)]
+    pub fn awd2ch5(&self) -> AWD2CH_R {
+        AWD2CH_R::new(((self.bits >> 5) & 1) != 0)
+    }
+    ///Bit 6 - AWD2CH
+    #[inline(always)]
+    pub fn awd2ch6(&self) -> AWD2CH_R {
+        AWD2CH_R::new(((self.bits >> 6) & 1) != 0)
+    }
+    ///Bit 7 - AWD2CH
+    #[inline(always)]
+    pub fn awd2ch7(&self) -> AWD2CH_R {
+        AWD2CH_R::new(((self.bits >> 7) & 1) != 0)
+    }
+    ///Bit 8 - AWD2CH
+    #[inline(always)]
+    pub fn awd2ch8(&self) -> AWD2CH_R {
+        AWD2CH_R::new(((self.bits >> 8) & 1) != 0)
+    }
+    ///Bit 9 - AWD2CH
+    #[inline(always)]
+    pub fn awd2ch9(&self) -> AWD2CH_R {
+        AWD2CH_R::new(((self.bits >> 9) & 1) != 0)
+    }
+    ///Bit 10 - AWD2CH
+    #[inline(always)]
+    pub fn awd2ch10(&self) -> AWD2CH_R {
+        AWD2CH_R::new(((self.bits >> 10) & 1) != 0)
+    }
+    ///Bit 11 - AWD2CH
+    #[inline(always)]
+    pub fn awd2ch11(&self) -> AWD2CH_R {
+        AWD2CH_R::new(((self.bits >> 11) & 1) != 0)
+    }
+    ///Bit 12 - AWD2CH
+    #[inline(always)]
+    pub fn awd2ch12(&self) -> AWD2CH_R {
+        AWD2CH_R::new(((self.bits >> 12) & 1) != 0)
+    }
+    ///Bit 13 - AWD2CH
+    #[inline(always)]
+    pub fn awd2ch13(&self) -> AWD2CH_R {
+        AWD2CH_R::new(((self.bits >> 13) & 1) != 0)
+    }
+    ///Bit 14 - AWD2CH
+    #[inline(always)]
+    pub fn awd2ch14(&self) -> AWD2CH_R {
+        AWD2CH_R::new(((self.bits >> 14) & 1) != 0)
+    }
+    ///Bit 15 - AWD2CH
+    #[inline(always)]
+    pub fn awd2ch15(&self) -> AWD2CH_R {
+        AWD2CH_R::new(((self.bits >> 15) & 1) != 0)
+    }
+    ///Bit 16 - AWD2CH
+    #[inline(always)]
+    pub fn awd2ch16(&self) -> AWD2CH_R {
+        AWD2CH_R::new(((self.bits >> 16) & 1) != 0)
+    }
+    ///Bit 17 - AWD2CH
+    #[inline(always)]
+    pub fn awd2ch17(&self) -> AWD2CH_R {
+        AWD2CH_R::new(((self.bits >> 17) & 1) != 0)
+    }
+    ///Bit 18 - AWD2CH
+    #[inline(always)]
+    pub fn awd2ch18(&self) -> AWD2CH_R {
+        AWD2CH_R::new(((self.bits >> 18) & 1) != 0)
+    }
+    ///Bit 19 - AWD2CH
+    #[inline(always)]
+    pub fn awd2ch19(&self) -> AWD2CH_R {
+        AWD2CH_R::new(((self.bits >> 19) & 1) != 0)
+    }
+}
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("AWD2CR")
+            .field("awd2ch0", &self.awd2ch0())
+            .field("awd2ch1", &self.awd2ch1())
+            .field("awd2ch2", &self.awd2ch2())
+            .field("awd2ch3", &self.awd2ch3())
+            .field("awd2ch4", &self.awd2ch4())
+            .field("awd2ch5", &self.awd2ch5())
+            .field("awd2ch6", &self.awd2ch6())
+            .field("awd2ch7", &self.awd2ch7())
+            .field("awd2ch8", &self.awd2ch8())
+            .field("awd2ch9", &self.awd2ch9())
+            .field("awd2ch10", &self.awd2ch10())
+            .field("awd2ch11", &self.awd2ch11())
+            .field("awd2ch12", &self.awd2ch12())
+            .field("awd2ch13", &self.awd2ch13())
+            .field("awd2ch14", &self.awd2ch14())
+            .field("awd2ch15", &self.awd2ch15())
+            .field("awd2ch16", &self.awd2ch16())
+            .field("awd2ch17", &self.awd2ch17())
+            .field("awd2ch18", &self.awd2ch18())
+            .field("awd2ch19", &self.awd2ch19())
+            .finish()
+    }
+}
+impl W {
+    ///AWD2CH
+    ///
+    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `AWD2CH0` field.</div>
+    #[inline(always)]
+    pub fn awd2ch(&mut self, n: u8) -> AWD2CH_W<AWD2CRrs> {
+        #[allow(clippy::no_effect)]
+        [(); 20][n as usize];
+        AWD2CH_W::new(self, n)
+    }
+    ///Bit 0 - AWD2CH
+    #[inline(always)]
+    pub fn awd2ch0(&mut self) -> AWD2CH_W<AWD2CRrs> {
+        AWD2CH_W::new(self, 0)
+    }
+    ///Bit 1 - AWD2CH
+    #[inline(always)]
+    pub fn awd2ch1(&mut self) -> AWD2CH_W<AWD2CRrs> {
+        AWD2CH_W::new(self, 1)
+    }
+    ///Bit 2 - AWD2CH
+    #[inline(always)]
+    pub fn awd2ch2(&mut self) -> AWD2CH_W<AWD2CRrs> {
+        AWD2CH_W::new(self, 2)
+    }
+    ///Bit 3 - AWD2CH
+    #[inline(always)]
+    pub fn awd2ch3(&mut self) -> AWD2CH_W<AWD2CRrs> {
+        AWD2CH_W::new(self, 3)
+    }
+    ///Bit 4 - AWD2CH
+    #[inline(always)]
+    pub fn awd2ch4(&mut self) -> AWD2CH_W<AWD2CRrs> {
+        AWD2CH_W::new(self, 4)
+    }
+    ///Bit 5 - AWD2CH
+    #[inline(always)]
+    pub fn awd2ch5(&mut self) -> AWD2CH_W<AWD2CRrs> {
+        AWD2CH_W::new(self, 5)
+    }
+    ///Bit 6 - AWD2CH
+    #[inline(always)]
+    pub fn awd2ch6(&mut self) -> AWD2CH_W<AWD2CRrs> {
+        AWD2CH_W::new(self, 6)
+    }
+    ///Bit 7 - AWD2CH
+    #[inline(always)]
+    pub fn awd2ch7(&mut self) -> AWD2CH_W<AWD2CRrs> {
+        AWD2CH_W::new(self, 7)
+    }
+    ///Bit 8 - AWD2CH
+    #[inline(always)]
+    pub fn awd2ch8(&mut self) -> AWD2CH_W<AWD2CRrs> {
+        AWD2CH_W::new(self, 8)
+    }
+    ///Bit 9 - AWD2CH
+    #[inline(always)]
+    pub fn awd2ch9(&mut self) -> AWD2CH_W<AWD2CRrs> {
+        AWD2CH_W::new(self, 9)
+    }
+    ///Bit 10 - AWD2CH
+    #[inline(always)]
+    pub fn awd2ch10(&mut self) -> AWD2CH_W<AWD2CRrs> {
+        AWD2CH_W::new(self, 10)
+    }
+    ///Bit 11 - AWD2CH
+    #[inline(always)]
+    pub fn awd2ch11(&mut self) -> AWD2CH_W<AWD2CRrs> {
+        AWD2CH_W::new(self, 11)
+    }
+    ///Bit 12 - AWD2CH
+    #[inline(always)]
+    pub fn awd2ch12(&mut self) -> AWD2CH_W<AWD2CRrs> {
+        AWD2CH_W::new(self, 12)
+    }
+    ///Bit 13 - AWD2CH
+    #[inline(always)]
+    pub fn awd2ch13(&mut self) -> AWD2CH_W<AWD2CRrs> {
+        AWD2CH_W::new(self, 13)
+    }
+    ///Bit 14 - AWD2CH
+    #[inline(always)]
+    pub fn awd2ch14(&mut self) -> AWD2CH_W<AWD2CRrs> {
+        AWD2CH_W::new(self, 14)
+    }
+    ///Bit 15 - AWD2CH
+    #[inline(always)]
+    pub fn awd2ch15(&mut self) -> AWD2CH_W<AWD2CRrs> {
+        AWD2CH_W::new(self, 15)
+    }
+    ///Bit 16 - AWD2CH
+    #[inline(always)]
+    pub fn awd2ch16(&mut self) -> AWD2CH_W<AWD2CRrs> {
+        AWD2CH_W::new(self, 16)
+    }
+    ///Bit 17 - AWD2CH
+    #[inline(always)]
+    pub fn awd2ch17(&mut self) -> AWD2CH_W<AWD2CRrs> {
+        AWD2CH_W::new(self, 17)
+    }
+    ///Bit 18 - AWD2CH
+    #[inline(always)]
+    pub fn awd2ch18(&mut self) -> AWD2CH_W<AWD2CRrs> {
+        AWD2CH_W::new(self, 18)
+    }
+    ///Bit 19 - AWD2CH
+    #[inline(always)]
+    pub fn awd2ch19(&mut self) -> AWD2CH_W<AWD2CRrs> {
+        AWD2CH_W::new(self, 19)
+    }
+}
+/**ADC analog watchdog 2 configuration register
+
+You can [`read`](crate::Reg::read) this register and get [`awd2cr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`awd2cr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
+
+See register [structure](https://stm32-rs.github.io/stm32-rs/STM32U535.html#ADC1:AWD2CR)*/
+pub struct AWD2CRrs;
+impl crate::RegisterSpec for AWD2CRrs {
+    type Ux = u32;
+}
+///`read()` method returns [`awd2cr::R`](R) reader structure
+impl crate::Readable for AWD2CRrs {}
+///`write(|w| ..)` method takes [`awd2cr::W`](W) writer structure
+impl crate::Writable for AWD2CRrs {
+    type Safety = crate::Unsafe;
+}
+///`reset()` method sets AWD2CR to value 0
+impl crate::Resettable for AWD2CRrs {}

### external/vendor/stm32u5/src/stm32u535/adc1/awd3cr.rs
@@ -0,0 +1,331 @@
+///Register `AWD3CR` reader
+pub type R = crate::R<AWD3CRrs>;
+///Register `AWD3CR` writer
+pub type W = crate::W<AWD3CRrs>;
+/**AWD3CH
+
+Value on reset: 0*/
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub enum AWD3CH {
+    ///0: ADC analog input channel x is not monitored by AWDy
+    Disabled = 0,
+    ///1: ADC analog input channel x is monitored by AWDy
+    Enabled = 1,
+}
+impl From<AWD3CH> for bool {
+    #[inline(always)]
+    fn from(variant: AWD3CH) -> Self {
+        variant as u8 != 0
+    }
+}
+///Field `AWD3CH(0-19)` reader - AWD3CH
+pub type AWD3CH_R = crate::BitReader<AWD3CH>;
+impl AWD3CH_R {
+    ///Get enumerated values variant
+    #[inline(always)]
+    pub const fn variant(&self) -> AWD3CH {
+        match self.bits {
+            false => AWD3CH::Disabled,
+            true => AWD3CH::Enabled,
+        }
+    }
+    ///ADC analog input channel x is not monitored by AWDy
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == AWD3CH::Disabled
+    }
+    ///ADC analog input channel x is monitored by AWDy
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == AWD3CH::Enabled
+    }
+}
+///Field `AWD3CH(0-19)` writer - AWD3CH
+pub type AWD3CH_W<'a, REG> = crate::BitWriter<'a, REG, AWD3CH>;
+impl<'a, REG> AWD3CH_W<'a, REG>
+where
+    REG: crate::Writable + crate::RegisterSpec,
+{
+    ///ADC analog input channel x is not monitored by AWDy
+    #[inline(always)]
+    pub fn disabled(self) -> &'a mut crate::W<REG> {
+        self.variant(AWD3CH::Disabled)
+    }
+    ///ADC analog input channel x is monitored by AWDy
+    #[inline(always)]
+    pub fn enabled(self) -> &'a mut crate::W<REG> {
+        self.variant(AWD3CH::Enabled)
+    }
+}
+impl R {
+    ///AWD3CH
+    ///
+    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `AWD3CH0` field.</div>
+    #[inline(always)]
+    pub fn awd3ch(&self, n: u8) -> AWD3CH_R {
+        #[allow(clippy::no_effect)]
+        [(); 20][n as usize];
+        AWD3CH_R::new(((self.bits >> n) & 1) != 0)
+    }
+    ///Iterator for array of:
+    ///AWD3CH
+    #[inline(always)]
+    pub fn awd3ch_iter(&self) -> impl Iterator<Item = AWD3CH_R> + '_ {
+        (0..20).map(move |n| AWD3CH_R::new(((self.bits >> n) & 1) != 0))
+    }
+    ///Bit 0 - AWD3CH
+    #[inline(always)]
+    pub fn awd3ch0(&self) -> AWD3CH_R {
+        AWD3CH_R::new((self.bits & 1) != 0)
+    }
+    ///Bit 1 - AWD3CH
+    #[inline(always)]
+    pub fn awd3ch1(&self) -> AWD3CH_R {
+        AWD3CH_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    ///Bit 2 - AWD3CH
+    #[inline(always)]
+    pub fn awd3ch2(&self) -> AWD3CH_R {
+        AWD3CH_R::new(((self.bits >> 2) & 1) != 0)
+    }
+    ///Bit 3 - AWD3CH
+    #[inline(always)]
+    pub fn awd3ch3(&self) -> AWD3CH_R {
+        AWD3CH_R::new(((self.bits >> 3) & 1) != 0)
+    }
+    ///Bit 4 - AWD3CH
+    #[inline(always)]
+    pub fn awd3ch4(&self) -> AWD3CH_R {
+        AWD3CH_R::new(((self.bits >> 4) & 1) != 0)
+    }
+    ///Bit 5 - AWD3CH
+    #[inline(always)]
+    pub fn awd3ch5(&self) -> AWD3CH_R {
+        AWD3CH_R::new(((self.bits >> 5) & 1) != 0)
+    }
+    ///Bit 6 - AWD3CH
+    #[inline(always)]
+    pub fn awd3ch6(&self) -> AWD3CH_R {
+        AWD3CH_R::new(((self.bits >> 6) & 1) != 0)
+    }
+    ///Bit 7 - AWD3CH
+    #[inline(always)]
+    pub fn awd3ch7(&self) -> AWD3CH_R {
+        AWD3CH_R::new(((self.bits >> 7) & 1) != 0)
+    }
+    ///Bit 8 - AWD3CH
+    #[inline(always)]
+    pub fn awd3ch8(&self) -> AWD3CH_R {
+        AWD3CH_R::new(((self.bits >> 8) & 1) != 0)
+    }
+    ///Bit 9 - AWD3CH
+    #[inline(always)]
+    pub fn awd3ch9(&self) -> AWD3CH_R {
+        AWD3CH_R::new(((self.bits >> 9) & 1) != 0)
+    }
+    ///Bit 10 - AWD3CH
+    #[inline(always)]
+    pub fn awd3ch10(&self) -> AWD3CH_R {
+        AWD3CH_R::new(((self.bits >> 10) & 1) != 0)
+    }
+    ///Bit 11 - AWD3CH
+    #[inline(always)]
+    pub fn awd3ch11(&self) -> AWD3CH_R {
+        AWD3CH_R::new(((self.bits >> 11) & 1) != 0)
+    }
+    ///Bit 12 - AWD3CH
+    #[inline(always)]
+    pub fn awd3ch12(&self) -> AWD3CH_R {
+        AWD3CH_R::new(((self.bits >> 12) & 1) != 0)
+    }
+    ///Bit 13 - AWD3CH
+    #[inline(always)]
+    pub fn awd3ch13(&self) -> AWD3CH_R {
+        AWD3CH_R::new(((self.bits >> 13) & 1) != 0)
+    }
+    ///Bit 14 - AWD3CH
+    #[inline(always)]
+    pub fn awd3ch14(&self) -> AWD3CH_R {
+        AWD3CH_R::new(((self.bits >> 14) & 1) != 0)
+    }
+    ///Bit 15 - AWD3CH
+    #[inline(always)]
+    pub fn awd3ch15(&self) -> AWD3CH_R {
+        AWD3CH_R::new(((self.bits >> 15) & 1) != 0)
+    }
+    ///Bit 16 - AWD3CH
+    #[inline(always)]
+    pub fn awd3ch16(&self) -> AWD3CH_R {
+        AWD3CH_R::new(((self.bits >> 16) & 1) != 0)
+    }
+    ///Bit 17 - AWD3CH
+    #[inline(always)]
+    pub fn awd3ch17(&self) -> AWD3CH_R {
+        AWD3CH_R::new(((self.bits >> 17) & 1) != 0)
+    }
+    ///Bit 18 - AWD3CH
+    #[inline(always)]
+    pub fn awd3ch18(&self) -> AWD3CH_R {
+        AWD3CH_R::new(((self.bits >> 18) & 1) != 0)
+    }
+    ///Bit 19 - AWD3CH
+    #[inline(always)]
+    pub fn awd3ch19(&self) -> AWD3CH_R {
+        AWD3CH_R::new(((self.bits >> 19) & 1) != 0)
+    }
+}
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("AWD3CR")
+            .field("awd3ch0", &self.awd3ch0())
+            .field("awd3ch1", &self.awd3ch1())
+            .field("awd3ch2", &self.awd3ch2())
+            .field("awd3ch3", &self.awd3ch3())
+            .field("awd3ch4", &self.awd3ch4())
+            .field("awd3ch5", &self.awd3ch5())
+            .field("awd3ch6", &self.awd3ch6())
+            .field("awd3ch7", &self.awd3ch7())
+            .field("awd3ch8", &self.awd3ch8())
+            .field("awd3ch9", &self.awd3ch9())
+            .field("awd3ch10", &self.awd3ch10())
+            .field("awd3ch11", &self.awd3ch11())
+            .field("awd3ch12", &self.awd3ch12())
+            .field("awd3ch13", &self.awd3ch13())
+            .field("awd3ch14", &self.awd3ch14())
+            .field("awd3ch15", &self.awd3ch15())
+            .field("awd3ch16", &self.awd3ch16())
+            .field("awd3ch17", &self.awd3ch17())
+            .field("awd3ch18", &self.awd3ch18())
+            .field("awd3ch19", &self.awd3ch19())
+            .finish()
+    }
+}
+impl W {
+    ///AWD3CH
+    ///
+    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `AWD3CH0` field.</div>
+    #[inline(always)]
+    pub fn awd3ch(&mut self, n: u8) -> AWD3CH_W<AWD3CRrs> {
+        #[allow(clippy::no_effect)]
+        [(); 20][n as usize];
+        AWD3CH_W::new(self, n)
+    }
+    ///Bit 0 - AWD3CH
+    #[inline(always)]
+    pub fn awd3ch0(&mut self) -> AWD3CH_W<AWD3CRrs> {
+        AWD3CH_W::new(self, 0)
+    }
+    ///Bit 1 - AWD3CH
+    #[inline(always)]
+    pub fn awd3ch1(&mut self) -> AWD3CH_W<AWD3CRrs> {
+        AWD3CH_W::new(self, 1)
+    }
+    ///Bit 2 - AWD3CH
+    #[inline(always)]
+    pub fn awd3ch2(&mut self) -> AWD3CH_W<AWD3CRrs> {
+        AWD3CH_W::new(self, 2)
+    }
+    ///Bit 3 - AWD3CH
+    #[inline(always)]
+    pub fn awd3ch3(&mut self) -> AWD3CH_W<AWD3CRrs> {
+        AWD3CH_W::new(self, 3)
+    }
+    ///Bit 4 - AWD3CH
+    #[inline(always)]
+    pub fn awd3ch4(&mut self) -> AWD3CH_W<AWD3CRrs> {
+        AWD3CH_W::new(self, 4)
+    }
+    ///Bit 5 - AWD3CH
+    #[inline(always)]
+    pub fn awd3ch5(&mut self) -> AWD3CH_W<AWD3CRrs> {
+        AWD3CH_W::new(self, 5)
+    }
+    ///Bit 6 - AWD3CH
+    #[inline(always)]
+    pub fn awd3ch6(&mut self) -> AWD3CH_W<AWD3CRrs> {
+        AWD3CH_W::new(self, 6)
+    }
+    ///Bit 7 - AWD3CH
+    #[inline(always)]
+    pub fn awd3ch7(&mut self) -> AWD3CH_W<AWD3CRrs> {
+        AWD3CH_W::new(self, 7)
+    }
+    ///Bit 8 - AWD3CH
+    #[inline(always)]
+    pub fn awd3ch8(&mut self) -> AWD3CH_W<AWD3CRrs> {
+        AWD3CH_W::new(self, 8)
+    }
+    ///Bit 9 - AWD3CH
+    #[inline(always)]
+    pub fn awd3ch9(&mut self) -> AWD3CH_W<AWD3CRrs> {
+        AWD3CH_W::new(self, 9)
+    }
+    ///Bit 10 - AWD3CH
+    #[inline(always)]
+    pub fn awd3ch10(&mut self) -> AWD3CH_W<AWD3CRrs> {
+        AWD3CH_W::new(self, 10)
+    }
+    ///Bit 11 - AWD3CH
+    #[inline(always)]
+    pub fn awd3ch11(&mut self) -> AWD3CH_W<AWD3CRrs> {
+        AWD3CH_W::new(self, 11)
+    }
+    ///Bit 12 - AWD3CH
+    #[inline(always)]
+    pub fn awd3ch12(&mut self) -> AWD3CH_W<AWD3CRrs> {
+        AWD3CH_W::new(self, 12)
+    }
+    ///Bit 13 - AWD3CH
+    #[inline(always)]
+    pub fn awd3ch13(&mut self) -> AWD3CH_W<AWD3CRrs> {
+        AWD3CH_W::new(self, 13)
+    }
+    ///Bit 14 - AWD3CH
+    #[inline(always)]
+    pub fn awd3ch14(&mut self) -> AWD3CH_W<AWD3CRrs> {
+        AWD3CH_W::new(self, 14)
+    }
+    ///Bit 15 - AWD3CH
+    #[inline(always)]
+    pub fn awd3ch15(&mut self) -> AWD3CH_W<AWD3CRrs> {
+        AWD3CH_W::new(self, 15)
+    }
+    ///Bit 16 - AWD3CH
+    #[inline(always)]
+    pub fn awd3ch16(&mut self) -> AWD3CH_W<AWD3CRrs> {
+        AWD3CH_W::new(self, 16)
+    }
+    ///Bit 17 - AWD3CH
+    #[inline(always)]
+    pub fn awd3ch17(&mut self) -> AWD3CH_W<AWD3CRrs> {
+        AWD3CH_W::new(self, 17)
+    }
+    ///Bit 18 - AWD3CH
+    #[inline(always)]
+    pub fn awd3ch18(&mut self) -> AWD3CH_W<AWD3CRrs> {
+        AWD3CH_W::new(self, 18)
+    }
+    ///Bit 19 - AWD3CH
+    #[inline(always)]
+    pub fn awd3ch19(&mut self) -> AWD3CH_W<AWD3CRrs> {
+        AWD3CH_W::new(self, 19)
+    }
+}
+/**ADC analog watchdog 3 configuration register
+
+You can [`read`](crate::Reg::read) this register and get [`awd3cr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`awd3cr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
+
+See register [structure](https://stm32-rs.github.io/stm32-rs/STM32U535.html#ADC1:AWD3CR)*/
+pub struct AWD3CRrs;
+impl crate::RegisterSpec for AWD3CRrs {
+    type Ux = u32;
+}
+///`read()` method returns [`awd3cr::R`](R) reader structure
+impl crate::Readable for AWD3CRrs {}
+///`write(|w| ..)` method takes [`awd3cr::W`](W) writer structure
+impl crate::Writable for AWD3CRrs {
+    type Safety = crate::Unsafe;
+}
+///`reset()` method sets AWD3CR to value 0
+impl crate::Resettable for AWD3CRrs {}

### external/vendor/stm32u5/src/stm32u535/adc1/calfact.rs
@@ -0,0 +1,226 @@
+///Register `CALFACT` reader
+pub type R = crate::R<CALFACTrs>;
+///Register `CALFACT` writer
+pub type W = crate::W<CALFACTrs>;
+///Field `I_APB_ADDR` reader - I_APB_ADDR
+pub type I_APB_ADDR_R = crate::FieldReader;
+///Field `I_APB_DATA` reader - I_APB_DATA
+pub type I_APB_DATA_R = crate::FieldReader;
+/**VALIDITY
+
+Value on reset: 0*/
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub enum VALIDITYR {
+    ///0: Operation still in progress
+    InProgress = 0,
+    ///1: Operation complete
+    Complete = 1,
+}
+impl From<VALIDITYR> for bool {
+    #[inline(always)]
+    fn from(variant: VALIDITYR) -> Self {
+        variant as u8 != 0
+    }
+}
+///Field `VALIDITY` reader - VALIDITY
+pub type VALIDITY_R = crate::BitReader<VALIDITYR>;
+impl VALIDITY_R {
+    ///Get enumerated values variant
+    #[inline(always)]
+    pub const fn variant(&self) -> VALIDITYR {
+        match self.bits {
+            false => VALIDITYR::InProgress,
+            true => VALIDITYR::Complete,
+        }
+    }
+    ///Operation still in progress
+    #[inline(always)]
+    pub fn is_in_progress(&self) -> bool {
+        *self == VALIDITYR::InProgress
+    }
+    ///Operation complete
+    #[inline(always)]
+    pub fn is_complete(&self) -> bool {
+        *self == VALIDITYR::Complete
+    }
+}
+/**LATCH_COEF
+
+Value on reset: 0*/
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub enum LATCH_COEF {
+    ///0: No effect
+    NoEffect = 0,
+    ///1: Calibration factor latched in the analog block on LATCH_COEF bit transition from 0 to 1. Prior to latching the calibration factor, CALFACT\[31:0\] bits must be programmed with the content of CALINDEX\[3:0\] bits.
+    Latch = 1,
+}
+impl From<LATCH_COEF> for bool {
+    #[inline(always)]
+    fn from(variant: LATCH_COEF) -> Self {
+        variant as u8 != 0
+    }
+}
+///Field `LATCH_COEF` reader - LATCH_COEF
+pub type LATCH_COEF_R = crate::BitReader<LATCH_COEF>;
+impl LATCH_COEF_R {
+    ///Get enumerated values variant
+    #[inline(always)]
+    pub const fn variant(&self) -> LATCH_COEF {
+        match self.bits {
+            false => LATCH_COEF::NoEffect,
+            true => LATCH_COEF::Latch,
+        }
+    }
+    ///No effect
+    #[inline(always)]
+    pub fn is_no_effect(&self) -> bool {
+        *self == LATCH_COEF::NoEffect
+    }
+    ///Calibration factor latched in the analog block on LATCH_COEF bit transition from 0 to 1. Prior to latching the calibration factor, CALFACT\[31:0\] bits must be programmed with the content of CALINDEX\[3:0\] bits.
+    #[inline(always)]
+    pub fn is_latch(&self) -> bool {
+        *self == LATCH_COEF::Latch
+    }
+}
+///Field `LATCH_COEF` writer - LATCH_COEF
+pub type LATCH_COEF_W<'a, REG> = crate::BitWriter<'a, REG, LATCH_COEF>;
+impl<'a, REG> LATCH_COEF_W<'a, REG>
+where
+    REG: crate::Writable + crate::RegisterSpec,
+{
+    ///No effect
+    #[inline(always)]
+    pub fn no_effect(self) -> &'a mut crate::W<REG> {
+        self.variant(LATCH_COEF::NoEffect)
+    }
+    ///Calibration factor latched in the analog block on LATCH_COEF bit transition from 0 to 1. Prior to latching the calibration factor, CALFACT\[31:0\] bits must be programmed with the content of CALINDEX\[3:0\] bits.
+    #[inline(always)]
+    pub fn latch(self) -> &'a mut crate::W<REG> {
+        self.variant(LATCH_COEF::Latch)
+    }
+}
+/**CAPTURE_COEF
+
+Value on reset: 0*/
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub enum CAPTURE_COEF {
+    ///0: Calibration factor not captured
+    Disabled = 0,
+    ///1: Calibration factor available in CALFACT\[31:0\] bits, the calibration factor index being defined by CALINDEX\[3:0\] bits
+    Enabled = 1,
+}
+impl From<CAPTURE_COEF> for bool {
+    #[inline(always)]
+    fn from(variant: CAPTURE_COEF) -> Self {
+        variant as u8 != 0
+    }
+}
+///Field `CAPTURE_COEF` reader - CAPTURE_COEF
+pub type CAPTURE_COEF_R = crate::BitReader<CAPTURE_COEF>;
+impl CAPTURE_COEF_R {
+    ///Get enumerated values variant
+    #[inline(always)]
+    pub const fn variant(&self) -> CAPTURE_COEF {
+        match self.bits {
+            false => CAPTURE_COEF::Disabled,
+            true => CAPTURE_COEF::Enabled,
+        }
+    }
+    ///Calibration factor not captured
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == CAPTURE_COEF::Disabled
+    }
+    ///Calibration factor available in CALFACT\[31:0\] bits, the calibration factor index being defined by CALINDEX\[3:0\] bits
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == CAPTURE_COEF::Enabled
+    }
+}
+///Field `CAPTURE_COEF` writer - CAPTURE_COEF
+pub type CAPTURE_COEF_W<'a, REG> = crate::BitWriter<'a, REG, CAPTURE_COEF>;
+impl<'a, REG> CAPTURE_COEF_W<'a, REG>
+where
+    REG: crate::Writable + crate::RegisterSpec,
+{
+    ///Calibration factor not captured
+    #[inline(always)]
+    pub fn disabled(self) -> &'a mut crate::W<REG> {
+        self.variant(CAPTURE_COEF::Disabled)
+    }
+    ///Calibration factor available in CALFACT\[31:0\] bits, the calibration factor index being defined by CALINDEX\[3:0\] bits
+    #[inline(always)]
+    pub fn enabled(self) -> &'a mut crate::W<REG> {
+        self.variant(CAPTURE_COEF::Enabled)
+    }
+}
+impl R {
+    ///Bits 0:7 - I_APB_ADDR
+    #[inline(always)]
+    pub fn i_apb_addr(&self) -> I_APB_ADDR_R {
+        I_APB_ADDR_R::new((self.bits & 0xff) as u8)
+    }
+    ///Bits 8:15 - I_APB_DATA
+    #[inline(always)]
+    pub fn i_apb_data(&self) -> I_APB_DATA_R {
+        I_APB_DATA_R::new(((self.bits >> 8) & 0xff) as u8)
+    }
+    ///Bit 16 - VALIDITY
+    #[inline(always)]
+    pub fn validity(&self) -> VALIDITY_R {
+        VALIDITY_R::new(((self.bits >> 16) & 1) != 0)
+    }
+    ///Bit 24 - LATCH_COEF
+    #[inline(always)]
+    pub fn latch_coef(&self) -> LATCH_COEF_R {
+        LATCH_COEF_R::new(((self.bits >> 24) & 1) != 0)
+    }
+    ///Bit 25 - CAPTURE_COEF
+    #[inline(always)]
+    pub fn capture_coef(&self) -> CAPTURE_COEF_R {
+        CAPTURE_COEF_R::new(((self.bits >> 25) & 1) != 0)
+    }
+}
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CALFACT")
+            .field("capture_coef", &self.capture_coef())
+            .field("latch_coef", &self.latch_coef())
+            .field("validity", &self.validity())
+            .field("i_apb_data", &self.i_apb_data())
+            .field("i_apb_addr", &self.i_apb_addr())
+            .finish()
+    }
+}
+impl W {
+    ///Bit 24 - LATCH_COEF
+    #[inline(always)]
+    pub fn latch_coef(&mut self) -> LATCH_COEF_W<CALFACTrs> {
+        LATCH_COEF_W::new(self, 24)
+    }
+    ///Bit 25 - CAPTURE_COEF
+    #[inline(always)]
+    pub fn capture_coef(&mut self) -> CAPTURE_COEF_W<CALFACTrs> {
+        CAPTURE_COEF_W::new(self, 25)
+    }
+}
+/**ADC user control register
+
+You can [`read`](crate::Reg::read) this register and get [`calfact::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`calfact::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
+
+See register [structure](https://stm32-rs.github.io/stm32-rs/STM32U535.html#ADC1:CALFACT)*/
+pub struct CALFACTrs;
+impl crate::RegisterSpec for CALFACTrs {
+    type Ux = u32;
+}
+///`read()` method returns [`calfact::R`](R) reader structure
+impl crate::Readable for CALFACTrs {}
+///`write(|w| ..)` method takes [`calfact::W`](W) writer structure
+impl crate::Writable for CALFACTrs {
+    type Safety = crate::Unsafe;
+}
+///`reset()` method sets CALFACT to value 0
+impl crate::Resettable for CALFACTrs {}

### external/vendor/stm32u5/src/stm32u535/adc1/calfact2.rs
@@ -0,0 +1,46 @@
+///Register `CALFACT2` reader
+pub type R = crate::R<CALFACT2rs>;
+///Register `CALFACT2` writer
+pub type W = crate::W<CALFACT2rs>;
+///Field `CALFACT` reader - CALFACT
+pub type CALFACT_R = crate::FieldReader<u32>;
+///Field `CALFACT` writer - CALFACT
+pub type CALFACT_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32, crate::Safe>;
+impl R {
+    ///Bits 0:31 - CALFACT
+    #[inline(always)]
+    pub fn calfact(&self) -> CALFACT_R {
+        CALFACT_R::new(self.bits)
+    }
+}
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CALFACT2")
+            .field("calfact", &self.calfact())
+            .finish()
+    }
+}
+impl W {
+    ///Bits 0:31 - CALFACT
+    #[inline(always)]
+    pub fn calfact(&mut self) -> CALFACT_W<CALFACT2rs> {
+        CALFACT_W::new(self, 0)
+    }
+}
+/**ADC calibration factor register
+
+You can [`read`](crate::Reg::read) this register and get [`calfact2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`calfact2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
+
+See register [structure](https://stm32-rs.github.io/stm32-rs/STM32U535.html#ADC1:CALFACT2)*/
+pub struct CALFACT2rs;
+impl crate::RegisterSpec for CALFACT2rs {
+    type Ux = u32;
+}
+///`read()` method returns [`calfact2::R`](R) reader structure
+impl crate::Readable for CALFACT2rs {}
+///`write(|w| ..)` method takes [`calfact2::W`](W) writer structure
+impl crate::Writable for CALFACT2rs {
+    type Safety = crate::Safe;
+}
+///`reset()` method sets CALFACT2 to value 0
+impl crate::Resettable for CALFACT2rs {}

### external/vendor/stm32u5/src/stm32u535/adc1/cfgr1.rs
@@ -0,0 +1,1424 @@
+///Register `CFGR1` reader
+pub type R = crate::R<CFGR1rs>;
+///Register `CFGR1` writer
+pub type W = crate::W<CFGR1rs>;
+/**DMNGT
+
+Value on reset: 0*/
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+#[repr(u8)]
+pub enum DMNGT {
+    ///0: Store output data in DR only
+    Dr = 0,
+    ///1: DMA One Shot Mode selected
+    DmaOneShot = 1,
+    ///2: DFSDM mode selected
+    Dfsdm = 2,
+    ///3: DMA Circular Mode selected
+    DmaCircular = 3,
+}
+impl From<DMNGT> for u8 {
+    #[inline(always)]
+    fn from(variant: DMNGT) -> Self {
+        variant as _
+    }
+}
+impl crate::FieldSpec for DMNGT {
+    type Ux = u8;
+}
+impl crate::IsEnum for DMNGT {}
+///Field `DMNGT` reader - DMNGT
+pub type DMNGT_R = crate::FieldReader<DMNGT>;
+impl DMNGT_R {
+    ///Get enumerated values variant
+    #[inline(always)]
+    pub const fn variant(&self) -> DMNGT {
+        match self.bits {
+            0 => DMNGT::Dr,
+            1 => DMNGT::DmaOneShot,
+            2 => DMNGT::Dfsdm,
+            3 => DMNGT::DmaCircular,
+            _ => unreachable!(),
+        }
+    }
+    ///Store output data in DR only
+    #[inline(always)]
+    pub fn is_dr(&self) -> bool {
+        *self == DMNGT::Dr
+    }
+    ///DMA One Shot Mode selected
+    #[inline(always)]
+    pub fn is_dma_one_shot(&self) -> bool {
+        *self == DMNGT::DmaOneShot
+    }
+    ///DFSDM mode selected
+    #[inline(always)]
+    pub fn is_dfsdm(&self) -> bool {
+        *self == DMNGT::Dfsdm
+    }
+    ///DMA Circular Mode selected
+    #[inline(always)]
+    pub fn is_dma_circular(&self) -> bool {
+        *self == DMNGT::DmaCircular
+    }
+}
+///Field `DMNGT` writer - DMNGT
+pub type DMNGT_W<'a, REG> = crate::FieldWriter<'a, REG, 2, DMNGT, crate::Safe>;
+impl<'a, REG> DMNGT_W<'a, REG>
+where
+    REG: crate::Writable + crate::RegisterSpec,
+    REG::Ux: From<u8>,
+{
+    ///Store output data in DR only
+    #[inline(always)]
+    pub fn dr(self) -> &'a mut crate::W<REG> {
+        self.variant(DMNGT::Dr)
+    }
+    ///DMA One Shot Mode selected
+    #[inline(always)]
+    pub fn dma_one_shot(self) -> &'a mut crate::W<REG> {
+        self.variant(DMNGT::DmaOneShot)
+    }
+    ///DFSDM mode selected
+    #[inline(always)]
+    pub fn dfsdm(self) -> &'a mut crate::W<REG> {
+        self.variant(DMNGT::Dfsdm)
+    }
+    ///DMA Circular Mode selected
+    #[inline(always)]
+    pub fn dma_circular(self) -> &'a mut crate::W<REG> {
+        self.variant(DMNGT::DmaCircular)
+    }
+}
+/**RES
+
+Value on reset: 0*/
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+#[repr(u8)]
+pub enum RES {
+    ///0: 14 bits
+    FourteenBit = 0,
+    ///1: 12 bits
+    TwelveBit = 1,
+    ///2: 10 bits
+    TenBit = 2,
+    ///3: 8 bits
+    EightBit = 3,
+}
+impl From<RES> for u8 {
+    #[inline(always)]
+    fn from(variant: RES) -> Self {
+        variant as _
+    }
+}
+impl crate::FieldSpec for RES {
+    type Ux = u8;
+}
+impl crate::IsEnum for RES {}
+///Field `RES` reader - RES
+pub type RES_R = crate::FieldReader<RES>;
+impl RES_R {
+    ///Get enumerated values variant
+    #[inline(always)]
+    pub const fn variant(&self) -> RES {
+        match self.bits {
+            0 => RES::FourteenBit,
+            1 => RES::TwelveBit,
+            2 => RES::TenBit,
+            3 => RES::EightBit,
+            _ => unreachable!(),
+        }
+    }
+    ///14 bits
+    #[inline(always)]
+    pub fn is_fourteen_bit(&self) -> bool {
+        *self == RES::FourteenBit
+    }
+    ///12 bits
+    #[inline(always)]
+    pub fn is_twelve_bit(&self) -> bool {
+        *self == RES::TwelveBit
+    }
+    ///10 bits
+    #[inline(always)]
+    pub fn is_ten_bit(&self) -> bool {
+        *self == RES::TenBit
+    }
+    ///8 bits
+    #[inline(always)]
+    pub fn is_eight_bit(&self) -> bool {
+        *self == RES::EightBit
+    }
+}
+///Field `RES` writer - RES
+pub type RES_W<'a, REG> = crate::FieldWriter<'a, REG, 2, RES, crate::Safe>;
+impl<'a, REG> RES_W<'a, REG>
+where
+    REG: crate::Writable + crate::RegisterSpec,
+    REG::Ux: From<u8>,
+{
+    ///14 bits
+    #[inline(always)]
+    pub fn fourteen_bit(self) -> &'a mut crate::W<REG> {
+        self.variant(RES::FourteenBit)
+    }
+    ///12 bits
+    #[inline(always)]
+    pub fn twelve_bit(self) -> &'a mut crate::W<REG> {
+        self.variant(RES::TwelveBit)
+    }
+    ///10 bits
+    #[inline(always)]
+    pub fn ten_bit(self) -> &'a mut crate::W<REG> {
+        self.variant(RES::TenBit)
+    }
+    ///8 bits
+    #[inline(always)]
+    pub fn eight_bit(self) -> &'a mut crate::W<REG> {
+        self.variant(RES::EightBit)
+    }
+}
+/**EXTSEL
+
+Value on reset: 0*/
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+#[repr(u8)]
+pub enum EXTSEL {
+    ///0: tim1_oc1
+    Tim1Oc1 = 0,
+    ///1: tim1_oc2
+    Tim1Oc2 = 1,
+    ///2: tim1_oc3
+    Tim1Oc3 = 2,
+    ///3: tim2_oc2
+    Tim2Oc2 = 3,
+    ///4: tim3_trgo
+    Tim3Trgo = 4,
+    ///5: tim4_oc4
+    Tim4Oc4 = 5,
+    ///6: exti11
+    Exti11 = 6,
+    ///7: tim8_trgo
+    Tim8Trgo = 7,
+    ///8: tim8_trgo2
+    Tim8Trgo2 = 8,
+    ///9: tim1_trgo
+    Tim1Trgo = 9,
+    ///10: tim1_trgo2
+    Tim1Trgo2 = 10,
+    ///11: tim2_trgo
+    Tim2Trgo = 11,
+    ///12: tim4_trgo
+    Tim4Trgo = 12,
+    ///13: tim6_trgo
+    Tim6Trgo = 13,
+    ///14: tim15_trgo
+    Tim15Trgo = 14,
+    ///15: tim3_oc4
+    Tim3Oc4 = 15,
+    ///16: exti15
+    Exti15 = 16,
+    ///18: lptim1_ch1
+    Lptim1Ch1 = 18,
+    ///19: lptim2_ch1
+    Lptim2Ch1 = 19,
+    ///20: lptim3_ch1
+    Lptim3Ch1 = 20,
+    ///21: lptim4_out
+    Lptim4Out = 21,
+}
+impl From<EXTSEL> for u8 {
+    #[inline(always)]
+    fn from(variant: EXTSEL) -> Self {
+        variant as _
+    }
+}
+impl crate::FieldSpec for EXTSEL {
+    type Ux = u8;
+}
+impl crate::IsEnum for EXTSEL {}
+///Field `EXTSEL` reader - EXTSEL
+pub type EXTSEL_R = crate::FieldReader<EXTSEL>;
+impl EXTSEL_R {
+    ///Get enumerated values variant
+    #[inline(always)]
+    pub const fn variant(&self) -> Option<EXTSEL> {
+        match self.bits {
+            0 => Some(EXTSEL::Tim1Oc1),
+            1 => Some(EXTSEL::Tim1Oc2),
+            2 => Some(EXTSEL::Tim1Oc3),
+            3 => Some(EXTSEL::Tim2Oc2),
+            4 => Some(EXTSEL::Tim3Trgo),
+            5 => Some(EXTSEL::Tim4Oc4),
+            6 => Some(EXTSEL::Exti11),
+            7 => Some(EXTSEL::Tim8Trgo),
+            8 => Some(EXTSEL::Tim8Trgo2),
+            9 => Some(EXTSEL::Tim1Trgo),
+            10 => Some(EXTSEL::Tim1Trgo2),
+            11 => Some(EXTSEL::Tim2Trgo),
+            12 => Some(EXTSEL::Tim4Trgo),
+            13 => Some(EXTSEL::Tim6Trgo),
+            14 => Some(EXTSEL::Tim15Trgo),
+            15 => Some(EXTSEL::Tim3Oc4),
+            16 => Some(EXTSEL::Exti15),
+            18 => Some(EXTSEL::Lptim1Ch1),
+            19 => Some(EXTSEL::Lptim2Ch1),
+            20 => Some(EXTSEL::Lptim3Ch1),
+            21 => Some(EXTSEL::Lptim4Out),
+            _ => None,
+        }
+    }
+    ///tim1_oc1
+    #[inline(always)]
+    pub fn is_tim1_oc1(&self) -> bool {
+        *self == EXTSEL::Tim1Oc1
+    }
+    ///tim1_oc2
+    #[inline(always)]
+    pub fn is_tim1_oc2(&self) -> bool {
+        *self == EXTSEL::Tim1Oc2
+    }
+    ///tim1_oc3
+    #[inline(always)]
+    pub fn is_tim1_oc3(&self) -> bool {
+        *self == EXTSEL::Tim1Oc3
+    }
+    ///tim2_oc2
+    #[inline(always)]
+    pub fn is_tim2_oc2(&self) -> bool {
+        *self == EXTSEL::Tim2Oc2
+    }
+    ///tim3_trgo
+    #[inline(always)]
+    pub fn is_tim3_trgo(&self) -> bool {
+        *self == EXTSEL::Tim3Trgo
+    }
+    ///tim4_oc4
+    #[inline(always)]
+    pub fn is_tim4_oc4(&self) -> bool {
+        *self == EXTSEL::Tim4Oc4
+    }
+    ///exti11
+    #[inline(always)]
+    pub fn is_exti11(&self) -> bool {
+        *self == EXTSEL::Exti11
+    }
+    ///tim8_trgo
+    #[inline(always)]
+    pub fn is_tim8_trgo(&self) -> bool {
+        *self == EXTSEL::Tim8Trgo
+    }
+    ///tim8_trgo2
+    #[inline(always)]
+    pub fn is_tim8_trgo2(&self) -> bool {
+        *self == EXTSEL::Tim8Trgo2
+    }
+    ///tim1_trgo
+    #[inline(always)]
+    pub fn is_tim1_trgo(&self) -> bool {
+        *self == EXTSEL::Tim1Trgo
+    }
+    ///tim1_trgo2
+    #[inline(always)]
+    pub fn is_tim1_trgo2(&self) -> bool {
+        *self == EXTSEL::Tim1Trgo2
+    }
+    ///tim2_trgo
+    #[inline(always)]
+    pub fn is_tim2_trgo(&self) -> bool {
+        *self == EXTSEL::Tim2Trgo
+    }
+    ///tim4_trgo
+    #[inline(always)]
+    pub fn is_tim4_trgo(&self) -> bool {
+        *self == EXTSEL::Tim4Trgo
+    }
+    ///tim6_trgo
+    #[inline(always)]
+    pub fn is_tim6_trgo(&self) -> bool {
+        *self == EXTSEL::Tim6Trgo
+    }
+    ///tim15_trgo
+    #[inline(always)]
+    pub fn is_tim15_trgo(&self) -> bool {
+        *self == EXTSEL::Tim15Trgo
+    }
+    ///tim3_oc4
+    #[inline(always)]
+    pub fn is_tim3_oc4(&self) -> bool {
+        *self == EXTSEL::Tim3Oc4
+    }
+    ///exti15
+    #[inline(always)]
+    pub fn is_exti15(&self) -> bool {
+        *self == EXTSEL::Exti15
+    }
+    ///lptim1_ch1
+    #[inline(always)]
+    pub fn is_lptim1_ch1(&self) -> bool {
+        *self == EXTSEL::Lptim1Ch1
+    }
+    ///lptim2_ch1
+    #[inline(always)]
+    pub fn is_lptim2_ch1(&self) -> bool {
+        *self == EXTSEL::Lptim2Ch1
+    }
+    ///lptim3_ch1
+    #[inline(always)]
+    pub fn is_lptim3_ch1(&self) -> bool {
+        *self == EXTSEL::Lptim3Ch1
+    }
+    ///lptim4_out
+    #[inline(always)]
+    pub fn is_lptim4_out(&self) -> bool {
+        *self == EXTSEL::Lptim4Out
+    }
+}
+///Field `EXTSEL` writer - EXTSEL
+pub type EXTSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 5, EXTSEL>;
+impl<'a, REG> EXTSEL_W<'a, REG>
+where
+    REG: crate::Writable + crate::RegisterSpec,
+    REG::Ux: From<u8>,
+{
+    ///tim1_oc1
+    #[inline(always)]
+    pub fn tim1_oc1(self) -> &'a mut crate::W<REG> {
+        self.variant(EXTSEL::Tim1Oc1)
+    }
+    ///tim1_oc2
+    #[inline(always)]
+    pub fn tim1_oc2(self) -> &'a mut crate::W<REG> {
+        self.variant(EXTSEL::Tim1Oc2)
+    }
+    ///tim1_oc3
+    #[inline(always)]
+    pub fn tim1_oc3(self) -> &'a mut crate::W<REG> {
+        self.variant(EXTSEL::Tim1Oc3)
+    }
+    ///tim2_oc2
+    #[inline(always)]
+    pub fn tim2_oc2(self) -> &'a mut crate::W<REG> {
+        self.variant(EXTSEL::Tim2Oc2)
+    }
+    ///tim3_trgo
+    #[inline(always)]
+    pub fn tim3_trgo(self) -> &'a mut crate::W<REG> {
+        self.variant(EXTSEL::Tim3Trgo)
+    }
+    ///tim4_oc4
+    #[inline(always)]
+    pub fn tim4_oc4(self) -> &'a mut crate::W<REG> {
+        self.variant(EXTSEL::Tim4Oc4)
+    }
+    ///exti11
+    #[inline(always)]
+    pub fn exti11(self) -> &'a mut crate::W<REG> {
+        self.variant(EXTSEL::Exti11)
+    }
+    ///tim8_trgo
+    #[inline(always)]
+    pub fn tim8_trgo(self) -> &'a mut crate::W<REG> {
+        self.variant(EXTSEL::Tim8Trgo)
+    }
+    ///tim8_trgo2
+    #[inline(always)]
+    pub fn tim8_trgo2(self) -> &'a mut crate::W<REG> {
+        self.variant(EXTSEL::Tim8Trgo2)
+    }
+    ///tim1_trgo
+    #[inline(always)]
+    pub fn tim1_trgo(self) -> &'a mut crate::W<REG> {
+        self.variant(EXTSEL::Tim1Trgo)
+    }
+    ///tim1_trgo2
+    #[inline(always)]
+    pub fn tim1_trgo2(self) -> &'a mut crate::W<REG> {
+        self.variant(EXTSEL::Tim1Trgo2)
+    }
+    ///tim2_trgo
+    #[inline(always)]
+    pub fn tim2_trgo(self) -> &'a mut crate::W<REG> {
+        self.variant(EXTSEL::Tim2Trgo)
+    }
+    ///tim4_trgo
+    #[inline(always)]
+    pub fn tim4_trgo(self) -> &'a mut crate::W<REG> {
+        self.variant(EXTSEL::Tim4Trgo)
+    }
+    ///tim6_trgo
+    #[inline(always)]
+    pub fn tim6_trgo(self) -> &'a mut crate::W<REG> {
+        self.variant(EXTSEL::Tim6Trgo)
+    }
+    ///tim15_trgo
+    #[inline(always)]
+    pub fn tim15_trgo(self) -> &'a mut crate::W<REG> {
+        self.variant(EXTSEL::Tim15Trgo)
+    }
+    ///tim3_oc4
+    #[inline(always)]
+    pub fn tim3_oc4(self) -> &'a mut crate::W<REG> {
+        self.variant(EXTSEL::Tim3Oc4)
+    }
+    ///exti15
+    #[inline(always)]
+    pub fn exti15(self) -> &'a mut crate::W<REG> {
+        self.variant(EXTSEL::Exti15)
+    }
+    ///lptim1_ch1
+    #[inline(always)]
+    pub fn lptim1_ch1(self) -> &'a mut crate::W<REG> {
+        self.variant(EXTSEL::Lptim1Ch1)
+    }
+    ///lptim2_ch1
+    #[inline(always)]
+    pub fn lptim2_ch1(self) -> &'a mut crate::W<REG> {
+        self.variant(EXTSEL::Lptim2Ch1)
+    }
+    ///lptim3_ch1
+    #[inline(always)]
+    pub fn lptim3_ch1(self) -> &'a mut crate::W<REG> {
+        self.variant(EXTSEL::Lptim3Ch1)
+    }
+    ///lptim4_out
+    #[inline(always)]
+    pub fn lptim4_out(self) -> &'a mut crate::W<REG> {
+        self.variant(EXTSEL::Lptim4Out)
+    }
+}
+/**EXTEN
+
+Value on reset: 0*/
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+#[repr(u8)]
+pub enum EXTEN {
+    ///0: Hardware trigger detection disabled (conversions can be launched by software)
+    Disabled = 0,
+    ///1: Hardware trigger detection on the rising edge
+    RisingEdge = 1,
+    ///2: Hardware trigger detection on the falling edge
+    FallingEdge = 2,
+    ///3: Hardware trigger detection on both the rising and falling edges
+    BothEdges = 3,
+}
+impl From<EXTEN> for u8 {
+    #[inline(always)]
+    fn from(variant: EXTEN) -> Self {
+        variant as _
+    }
+}
+impl crate::FieldSpec for EXTEN {
+    type Ux = u8;
+}
+impl crate::IsEnum for EXTEN {}
+///Field `EXTEN` reader - EXTEN
+pub type EXTEN_R = crate::FieldReader<EXTEN>;
+impl EXTEN_R {
+    ///Get enumerated values variant
+    #[inline(always)]
+    pub const fn variant(&self) -> EXTEN {
+        match self.bits {
+            0 => EXTEN::Disabled,
+            1 => EXTEN::RisingEdge,
+            2 => EXTEN::FallingEdge,
+            3 => EXTEN::BothEdges,
+            _ => unreachable!(),
+        }
+    }
+    ///Hardware trigger detection disabled (conversions can be launched by software)
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == EXTEN::Disabled
+    }
+    ///Hardware trigger detection on the rising edge
+    #[inline(always)]
+    pub fn is_rising_edge(&self) -> bool {
+        *self == EXTEN::RisingEdge
+    }
+    ///Hardware trigger detection on the falling edge
+    #[inline(always)]
+    pub fn is_falling_edge(&self) -> bool {
+        *self == EXTEN::FallingEdge
+    }
+    ///Hardware trigger detection on both the rising and falling edges
+    #[inline(always)]
+    pub fn is_both_edges(&self) -> bool {
+        *self == EXTEN::BothEdges
+    }
+}
+///Field `EXTEN` writer - EXTEN
+pub type EXTEN_W<'a, REG> = crate::FieldWriter<'a, REG, 2, EXTEN, crate::Safe>;
+impl<'a, REG> EXTEN_W<'a, REG>
+where
+    REG: crate::Writable + crate::RegisterSpec,
+    REG::Ux: From<u8>,
+{
+    ///Hardware trigger detection disabled (conversions can be launched by software)
+    #[inline(always)]
+    pub fn disabled(self) -> &'a mut crate::W<REG> {
+        self.variant(EXTEN::Disabled)
+    }
+    ///Hardware trigger detection on the rising edge
+    #[inline(always)]
+    pub fn rising_edge(self) -> &'a mut crate::W<REG> {
+        self.variant(EXTEN::RisingEdge)
+    }
+    ///Hardware trigger detection on the falling edge
+    #[inline(always)]
+    pub fn falling_edge(self) -> &'a mut crate::W<REG> {
+        self.variant(EXTEN::FallingEdge)
+    }
+    ///Hardware trigger detection on both the rising and falling edges
+    #[inline(always)]
+    pub fn both_edges(self) -> &'a mut crate::W<REG> {
+        self.variant(EXTEN::BothEdges)
+    }
+}
+/**OVRMOD
+
+Value on reset: 0*/
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub enum OVRMOD {
+    ///0: ADC_DR register is preserved with the old data when an overrun is detected
+    Preserve = 0,
+    ///1: ADC_DR register is overwritten with the last conversion result when an overrun is detected
+    Overwrite = 1,
+}
+impl From<OVRMOD> for bool {
+    #[inline(always)]
+    fn from(variant: OVRMOD) -> Self {
+        variant as u8 != 0
+    }
+}
+///Field `OVRMOD` reader - OVRMOD
+pub type OVRMOD_R = crate::BitReader<OVRMOD>;
+impl OVRMOD_R {
+    ///Get enumerated values variant
+    #[inline(always)]
+    pub const fn variant(&self) -> OVRMOD {
+        match self.bits {
+            false => OVRMOD::Preserve,
+            true => OVRMOD::Overwrite,
+        }
+    }
+    ///ADC_DR register is preserved with the old data when an overrun is detected
+    #[inline(always)]
+    pub fn is_preserve(&self) -> bool {
+        *self == OVRMOD::Preserve
+    }
+    ///ADC_DR register is overwritten with the last conversion result when an overrun is detected
+    #[inline(always)]
+    pub fn is_overwrite(&self) -> bool {
+        *self == OVRMOD::Overwrite
+    }
+}
+///Field `OVRMOD` writer - OVRMOD
+pub type OVRMOD_W<'a, REG> = crate::BitWriter<'a, REG, OVRMOD>;
+impl<'a, REG> OVRMOD_W<'a, REG>
+where
+    REG: crate::Writable + crate::RegisterSpec,
+{
+    ///ADC_DR register is preserved with the old data when an overrun is detected
+    #[inline(always)]
+    pub fn preserve(self) -> &'a mut crate::W<REG> {
+        self.variant(OVRMOD::Preserve)
+    }
+    ///ADC_DR register is overwritten with the last conversion result when an overrun is detected
+    #[inline(always)]
+    pub fn overwrite(self) -> &'a mut crate::W<REG> {
+        self.variant(OVRMOD::Overwrite)
+    }
+}
+/**CONT
+
+Value on reset: 0*/
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub enum CONT {
+    ///0: Single conversion mode
+    Single = 0,
+    ///1: Continuous conversion mode
+    Continuous = 1,
+}
+impl From<CONT> for bool {
+    #[inline(always)]
+    fn from(variant: CONT) -> Self {
+        variant as u8 != 0
+    }
+}
+///Field `CONT` reader - CONT
+pub type CONT_R = crate::BitReader<CONT>;
+impl CONT_R {
+    ///Get enumerated values variant
+    #[inline(always)]
+    pub const fn variant(&self) -> CONT {
+        match self.bits {
+            false => CONT::Single,
+            true => CONT::Continuous,
+        }
+    }
+    ///Single conversion mode
+    #[inline(always)]
+    pub fn is_single(&self) -> bool {
+        *self == CONT::Single
+    }
+    ///Continuous conversion mode
+    #[inline(always)]
+    pub fn is_continuous(&self) -> bool {
+        *self == CONT::Continuous
+    }
+}
+///Field `CONT` writer - CONT
+pub type CONT_W<'a, REG> = crate::BitWriter<'a, REG, CONT>;
+impl<'a, REG> CONT_W<'a, REG>
+where
+    REG: crate::Writable + crate::RegisterSpec,
+{
+    ///Single conversion mode
+    #[inline(always)]
+    pub fn single(self) -> &'a mut crate::W<REG> {
+        self.variant(CONT::Single)
+    }
+    ///Continuous conversion mode
+    #[inline(always)]
+    pub fn continuous(self) -> &'a mut crate::W<REG> {
+        self.variant(CONT::Continuous)
+    }
+}
+/**AUTDLY
+
+Value on reset: 0*/
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub enum AUTDLY {
+    ///0: Auto-delayed conversion mode off
+    Disabled = 0,
+    ///1: Auto-delayed conversion mode on
+    Enabled = 1,
+}
+impl From<AUTDLY> for bool {
+    #[inline(always)]
+    fn from(variant: AUTDLY) -> Self {
+        variant as u8 != 0
+    }
+}
+///Field `AUTDLY` reader - AUTDLY
+pub type AUTDLY_R = crate::BitReader<AUTDLY>;
+impl AUTDLY_R {
+    ///Get enumerated values variant
+    #[inline(always)]
+    pub const fn variant(&self) -> AUTDLY {
+        match self.bits {
+            false => AUTDLY::Disabled,
+            true => AUTDLY::Enabled,
+        }
+    }
+    ///Auto-delayed conversion mode off
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == AUTDLY::Disabled
+    }
+    ///Auto-delayed conversion mode on
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == AUTDLY::Enabled
+    }
+}
+///Field `AUTDLY` writer - AUTDLY
+pub type AUTDLY_W<'a, REG> = crate::BitWriter<'a, REG, AUTDLY>;
+impl<'a, REG> AUTDLY_W<'a, REG>
+where
+    REG: crate::Writable + crate::RegisterSpec,
+{
+    ///Auto-delayed conversion mode off
+    #[inline(always)]
+    pub fn disabled(self) -> &'a mut crate::W<REG> {
+        self.variant(AUTDLY::Disabled)
+    }
+    ///Auto-delayed conversion mode on
+    #[inline(always)]
+    pub fn enabled(self) -> &'a mut crate::W<REG> {
+        self.variant(AUTDLY::Enabled)
+    }
+}
+/**DISCEN
+
+Value on reset: 0*/
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub enum DISCEN {
+    ///0: Discontinuous mode for regular channels disabled
+    Disabled = 0,
+    ///1: Discontinuous mode for regular channels enabled
+    Enabled = 1,
+}
+impl From<DISCEN> for bool {
+    #[inline(always)]
+    fn from(variant: DISCEN) -> Self {
+        variant as u8 != 0
+    }
+}
+///Field `DISCEN` reader - DISCEN
+pub type DISCEN_R = crate::BitReader<DISCEN>;
+impl DISCEN_R {
+    ///Get enumerated values variant
+    #[inline(always)]
+    pub const fn variant(&self) -> DISCEN {
+        match self.bits {
+            false => DISCEN::Disabled,
+            true => DISCEN::Enabled,
+        }
+    }
+    ///Discontinuous mode for regular channels disabled
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == DISCEN::Disabled
+    }
+    ///Discontinuous mode for regular channels enabled
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == DISCEN::Enabled
+    }
+}
+///Field `DISCEN` writer - DISCEN
+pub type DISCEN_W<'a, REG> = crate::BitWriter<'a, REG, DISCEN>;
+impl<'a, REG> DISCEN_W<'a, REG>
+where
+    REG: crate::Writable + crate::RegisterSpec,
+{
+    ///Discontinuous mode for regular channels disabled
+    #[inline(always)]
+    pub fn disabled(self) -> &'a mut crate::W<REG> {
+        self.variant(DISCEN::Disabled)
+    }
+    ///Discontinuous mode for regular channels enabled
+    #[inline(always)]
+    pub fn enabled(self) -> &'a mut crate::W<REG> {
+        self.variant(DISCEN::Enabled)
+    }
+}
+/**DISCNUM
+
+Value on reset: 0*/
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+#[repr(u8)]
+pub enum DISCNUM {
+    ///0: 1 channel
+    N1 = 0,
+    ///1: 2 channels
+    N2 = 1,
+    ///2: 3 channels
+    N3 = 2,
+    ///3: 4 channels
+    N4 = 3,
+    ///4: 5 channels
+    N5 = 4,
+    ///5: 6 channels
+    N6 = 5,
+    ///6: 7 channels
+    N7 = 6,
+    ///7: 8 channels
+    N8 = 7,
+}
+impl From<DISCNUM> for u8 {
+    #[inline(always)]
+    fn from(variant: DISCNUM) -> Self {
+        variant as _
+    }
+}
+impl crate::FieldSpec for DISCNUM {
+    type Ux = u8;
+}
+impl crate::IsEnum for DISCNUM {}
+///Field `DISCNUM` reader - DISCNUM
+pub type DISCNUM_R = crate::FieldReader<DISCNUM>;
+impl DISCNUM_R {
+    ///Get enumerated values variant
+    #[inline(always)]
+    pub const fn variant(&self) -> DISCNUM {
+        match self.bits {
+            0 => DISCNUM::N1,
+            1 => DISCNUM::N2,
+            2 => DISCNUM::N3,
+            3 => DISCNUM::N4,
+            4 => DISCNUM::N5,
+            5 => DISCNUM::N6,
+            6 => DISCNUM::N7,
+            7 => DISCNUM::N8,
+            _ => unreachable!(),
+        }
+    }
+    ///1 channel
+    #[inline(always)]
+    pub fn is_n1(&self) -> bool {
+        *self == DISCNUM::N1
+    }
+    ///2 channels
+    #[inline(always)]
+    pub fn is_n2(&self) -> bool {
+        *self == DISCNUM::N2
+    }
+    ///3 channels
+    #[inline(always)]
+    pub fn is_n3(&self) -> bool {
+        *self == DISCNUM::N3
+    }
+    ///4 channels
+    #[inline(always)]
+    pub fn is_n4(&self) -> bool {
+        *self == DISCNUM::N4
+    }
+    ///5 channels
+    #[inline(always)]
+    pub fn is_n5(&self) -> bool {
+        *self == DISCNUM::N5
+    }
+    ///6 channels
+    #[inline(always)]
+    pub fn is_n6(&self) -> bool {
+        *self == DISCNUM::N6
+    }
+    ///7 channels
+    #[inline(always)]
+    pub fn is_n7(&self) -> bool {
+        *self == DISCNUM::N7
+    }
+    ///8 channels
+    #[inline(always)]
+    pub fn is_n8(&self) -> bool {
+        *self == DISCNUM::N8
+    }
+}
+///Field `DISCNUM` writer - DISCNUM
+pub type DISCNUM_W<'a, REG> = crate::FieldWriter<'a, REG, 3, DISCNUM, crate::Safe>;
+impl<'a, REG> DISCNUM_W<'a, REG>
+where
+    REG: crate::Writable + crate::RegisterSpec,
+    REG::Ux: From<u8>,
+{
+    ///1 channel
+    #[inline(always)]
+    pub fn n1(self) -> &'a mut crate::W<REG> {
+        self.variant(DISCNUM::N1)
+    }
+    ///2 channels
+    #[inline(always)]
+    pub fn n2(self) -> &'a mut crate::W<REG> {
+        self.variant(DISCNUM::N2)
+    }
+    ///3 channels
+    #[inline(always)]
+    pub fn n3(self) -> &'a mut crate::W<REG> {
+        self.variant(DISCNUM::N3)
+    }
+    ///4 channels
+    #[inline(always)]
+    pub fn n4(self) -> &'a mut crate::W<REG> {
+        self.variant(DISCNUM::N4)
+    }
+    ///5 channels
+    #[inline(always)]
+    pub fn n5(self) -> &'a mut crate::W<REG> {
+        self.variant(DISCNUM::N5)
+    }
+    ///6 channels
+    #[inline(always)]
+    pub fn n6(self) -> &'a mut crate::W<REG> {
+        self.variant(DISCNUM::N6)
+    }
+    ///7 channels
+    #[inline(always)]
+    pub fn n7(self) -> &'a mut crate::W<REG> {
+        self.variant(DISCNUM::N7)
+    }
+    ///8 channels
+    #[inline(always)]
+    pub fn n8(self) -> &'a mut crate::W<REG> {
+        self.variant(DISCNUM::N8)
+    }
+}
+/**JDISCEN
+
+Value on reset: 0*/
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub enum JDISCEN {
+    ///0: Discontinuous mode on injected channels disabled
+    Disabled = 0,
+    ///1: Discontinuous mode on injected channels enabled
+    Enabled = 1,
+}
+impl From<JDISCEN> for bool {
+    #[inline(always)]
+    fn from(variant: JDISCEN) -> Self {
+        variant as u8 != 0
+    }
+}
+///Field `JDISCEN` reader - JDISCEN
+pub type JDISCEN_R = crate::BitReader<JDISCEN>;
+impl JDISCEN_R {
+    ///Get enumerated values variant
+    #[inline(always)]
+    pub const fn variant(&self) -> JDISCEN {
+        match self.bits {
+            false => JDISCEN::Disabled,
+            true => JDISCEN::Enabled,
+        }
+    }
+    ///Discontinuous mode on injected channels disabled
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == JDISCEN::Disabled
+    }
+    ///Discontinuous mode on injected channels enabled
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == JDISCEN::Enabled
+    }
+}
+///Field `JDISCEN` writer - JDISCEN
+pub type JDISCEN_W<'a, REG> = crate::BitWriter<'a, REG, JDISCEN>;
+impl<'a, REG> JDISCEN_W<'a, REG>
+where
+    REG: crate::Writable + crate::RegisterSpec,
+{
+    ///Discontinuous mode on injected channels disabled
+    #[inline(always)]
+    pub fn disabled(self) -> &'a mut crate::W<REG> {
+        self.variant(JDISCEN::Disabled)
+    }
+    ///Discontinuous mode on injected channels enabled
+    #[inline(always)]
+    pub fn enabled(self) -> &'a mut crate::W<REG> {
+        self.variant(JDISCEN::Enabled)
+    }
+}
+/**AWD1SGL
+
+Value on reset: 0*/
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub enum AWD1SGL {
+    ///0: Analog watchdog 1 enabled on all channels
+    AllChannels = 0,
+    ///1: Analog watchdog 1 enabled on a single channel
+    SingleChannel = 1,
+}
+impl From<AWD1SGL> for bool {
+    #[inline(always)]
+    fn from(variant: AWD1SGL) -> Self {
+        variant as u8 != 0
+    }
+}
+///Field `AWD1SGL` reader - AWD1SGL
+pub type AWD1SGL_R = crate::BitReader<AWD1SGL>;
+impl AWD1SGL_R {
+    ///Get enumerated values variant
+    #[inline(always)]
+    pub const fn variant(&self) -> AWD1SGL {
+        match self.bits {
+            false => AWD1SGL::AllChannels,
+            true => AWD1SGL::SingleChannel,
+        }
+    }
+    ///Analog watchdog 1 enabled on all channels
+    #[inline(always)]
+    pub fn is_all_channels(&self) -> bool {
+        *self == AWD1SGL::AllChannels
+    }
+    ///Analog watchdog 1 enabled on a single channel
+    #[inline(always)]
+    pub fn is_single_channel(&self) -> bool {
+        *self == AWD1SGL::SingleChannel
+    }
+}
+///Field `AWD1SGL` writer - AWD1SGL
+pub type AWD1SGL_W<'a, REG> = crate::BitWriter<'a, REG, AWD1SGL>;
+impl<'a, REG> AWD1SGL_W<'a, REG>
+where
+    REG: crate::Writable + crate::RegisterSpec,
+{
+    ///Analog watchdog 1 enabled on all channels
+    #[inline(always)]
+    pub fn all_channels(self) -> &'a mut crate::W<REG> {
+        self.variant(AWD1SGL::AllChannels)
+    }
+    ///Analog watchdog 1 enabled on a single channel
+    #[inline(always)]
+    pub fn single_channel(self) -> &'a mut crate::W<REG> {
+        self.variant(AWD1SGL::SingleChannel)
+    }
+}
+/**AWD1EN
+
+Value on reset: 0*/
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub enum AWD1EN {
+    ///0: Analog watchdog 1 disabled on regular channels
+    Disabled = 0,
+    ///1: Analog watchdog 1 enabled on regular channels
+    Enabled = 1,
+}
+impl From<AWD1EN> for bool {
+    #[inline(always)]
+    fn from(variant: AWD1EN) -> Self {
+        variant as u8 != 0
+    }
+}
+///Field `AWD1EN` reader - AWD1EN
+pub type AWD1EN_R = crate::BitReader<AWD1EN>;
+impl AWD1EN_R {
+    ///Get enumerated values variant
+    #[inline(always)]
+    pub const fn variant(&self) -> AWD1EN {
+        match self.bits {
+            false => AWD1EN::Disabled,
+            true => AWD1EN::Enabled,
+        }
+    }
+    ///Analog watchdog 1 disabled on regular channels
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == AWD1EN::Disabled
+    }
+    ///Analog watchdog 1 enabled on regular channels
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == AWD1EN::Enabled
+    }
+}
+///Field `AWD1EN` writer - AWD1EN
+pub type AWD1EN_W<'a, REG> = crate::BitWriter<'a, REG, AWD1EN>;
+impl<'a, REG> AWD1EN_W<'a, REG>
+where
+    REG: crate::Writable + crate::RegisterSpec,
+{
+    ///Analog watchdog 1 disabled on regular channels
+    #[inline(always)]
+    pub fn disabled(self) -> &'a mut crate::W<REG> {
+        self.variant(AWD1EN::Disabled)
+    }
+    ///Analog watchdog 1 enabled on regular channels
+    #[inline(always)]
+    pub fn enabled(self) -> &'a mut crate::W<REG> {
+        self.variant(AWD1EN::Enabled)
+    }
+}
+/**JAWD1EN
+
+Value on reset: 0*/
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub enum JAWD1EN {
+    ///0: Analog watchdog 1 disabled on injected channels
+    Disabled = 0,
+    ///1: Analog watchdog 1 enabled on injected channels
+    Enabled = 1,
+}
+impl From<JAWD1EN> for bool {
+    #[inline(always)]
+    fn from(variant: JAWD1EN) -> Self {
+        variant as u8 != 0
+    }
+}
+///Field `JAWD1EN` reader - JAWD1EN
+pub type JAWD1EN_R = crate::BitReader<JAWD1EN>;
+impl JAWD1EN_R {
+    ///Get enumerated values variant
+    #[inline(always)]
+    pub const fn variant(&self) -> JAWD1EN {
+        match self.bits {
+            false => JAWD1EN::Disabled,
+            true => JAWD1EN::Enabled,
+        }
+    }
+    ///Analog watchdog 1 disabled on injected channels
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == JAWD1EN::Disabled
+    }
+    ///Analog watchdog 1 enabled on injected channels
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == JAWD1EN::Enabled
+    }
+}
+///Field `JAWD1EN` writer - JAWD1EN
+pub type JAWD1EN_W<'a, REG> = crate::BitWriter<'a, REG, JAWD1EN>;
+impl<'a, REG> JAWD1EN_W<'a, REG>
+where
+    REG: crate::Writable + crate::RegisterSpec,
+{
+    ///Analog watchdog 1 disabled on injected channels
+    #[inline(always)]
+    pub fn disabled(self) -> &'a mut crate::W<REG> {
+        self.variant(JAWD1EN::Disabled)
+    }
+    ///Analog watchdog 1 enabled on injected channels
+    #[inline(always)]
+    pub fn enabled(self) -> &'a mut crate::W<REG> {
+        self.variant(JAWD1EN::Enabled)
+    }
+}
+/**JAUTO
+
+Value on reset: 0*/
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub enum JAUTO {
+    ///0: Automatic injected group conversion disabled
+    Disabled = 0,
+    ///1: Automatic injected group conversion enabled
+    Enabled = 1,
+}
+impl From<JAUTO> for bool {
+    #[inline(always)]
+    fn from(variant: JAUTO) -> Self {
+        variant as u8 != 0
+    }
+}
+///Field `JAUTO` reader - JAUTO
+pub type JAUTO_R = crate::BitReader<JAUTO>;
+impl JAUTO_R {
+    ///Get enumerated values variant
+    #[inline(always)]
+    pub const fn variant(&self) -> JAUTO {
+        match self.bits {
+            false => JAUTO::Disabled,
+            true => JAUTO::Enabled,
+        }
+    }
+    ///Automatic injected group conversion disabled
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == JAUTO::Disabled
+    }
+    ///Automatic injected group conversion enabled
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == JAUTO::Enabled
+    }
+}
+///Field `JAUTO` writer - JAUTO
+pub type JAUTO_W<'a, REG> = crate::BitWriter<'a, REG, JAUTO>;
+impl<'a, REG> JAUTO_W<'a, REG>
+where
+    REG: crate::Writable + crate::RegisterSpec,
+{
+    ///Automatic injected group conversion disabled
+    #[inline(always)]
+    pub fn disabled(self) -> &'a mut crate::W<REG> {
+        self.variant(JAUTO::Disabled)
+    }
+    ///Automatic injected group conversion enabled
+    #[inline(always)]
+    pub fn enabled(self) -> &'a mut crate::W<REG> {
+        self.variant(JAUTO::Enabled)
+    }
+}
+///Field `AWD1CH` reader - AWD1CH
+pub type AWD1CH_R = crate::FieldReader;
+///Field `AWD1CH` writer - AWD1CH
+pub type AWD1CH_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
+impl R {
+    ///Bits 0:1 - DMNGT
+    #[inline(always)]
+    pub fn dmngt(&self) -> DMNGT_R {
+        DMNGT_R::new((self.bits & 3) as u8)
+    }
+    ///Bits 2:3 - RES
+    #[inline(always)]
+    pub fn res(&self) -> RES_R {
+        RES_R::new(((self.bits >> 2) & 3) as u8)
+    }
+    ///Bits 5:9 - EXTSEL
+    #[inline(always)]
+    pub fn extsel(&self) -> EXTSEL_R {
+        EXTSEL_R::new(((self.bits >> 5) & 0x1f) as u8)
+    }
+    ///Bits 10:11 - EXTEN
+    #[inline(always)]
+    pub fn exten(&self) -> EXTEN_R {
+        EXTEN_R::new(((self.bits >> 10) & 3) as u8)
+    }
+    ///Bit 12 - OVRMOD
+    #[inline(always)]
+    pub fn ovrmod(&self) -> OVRMOD_R {
+        OVRMOD_R::new(((self.bits >> 12) & 1) != 0)
+    }
+    ///Bit 13 - CONT
+    #[inline(always)]
+    pub fn cont(&self) -> CONT_R {
+        CONT_R::new(((self.bits >> 13) & 1) != 0)
+    }
+    ///Bit 14 - AUTDLY
+    #[inline(always)]
+    pub fn autdly(&self) -> AUTDLY_R {
+        AUTDLY_R::new(((self.bits >> 14) & 1) != 0)
+    }
+    ///Bit 16 - DISCEN
+    #[inline(always)]
+    pub fn discen(&self) -> DISCEN_R {
+        DISCEN_R::new(((self.bits >> 16) & 1) != 0)
+    }
+    ///Bits 17:19 - DISCNUM
+    #[inline(always)]
+    pub fn discnum(&self) -> DISCNUM_R {
+        DISCNUM_R::new(((self.bits >> 17) & 7) as u8)
+    }
+    ///Bit 20 - JDISCEN
+    #[inline(always)]
+    pub fn jdiscen(&self) -> JDISCEN_R {
+        JDISCEN_R::new(((self.bits >> 20) & 1) != 0)
+    }
+    ///Bit 22 - AWD1SGL
+    #[inline(always)]
+    pub fn awd1sgl(&self) -> AWD1SGL_R {
+        AWD1SGL_R::new(((self.bits >> 22) & 1) != 0)
+    }
+    ///Bit 23 - AWD1EN
+    #[inline(always)]
+    pub fn awd1en(&self) -> AWD1EN_R {
+        AWD1EN_R::new(((self.bits >> 23) & 1) != 0)
+    }
+    ///Bit 24 - JAWD1EN
+    #[inline(always)]
+    pub fn jawd1en(&self) -> JAWD1EN_R {
+        JAWD1EN_R::new(((self.bits >> 24) & 1) != 0)
+    }
+    ///Bit 25 - JAUTO
+    #[inline(always)]
+    pub fn jauto(&self) -> JAUTO_R {
+        JAUTO_R::new(((self.bits >> 25) & 1) != 0)
+    }
+    ///Bits 26:30 - AWD1CH
+    #[inline(always)]
+    pub fn awd1ch(&self) -> AWD1CH_R {
+        AWD1CH_R::new(((self.bits >> 26) & 0x1f) as u8)
+    }
+}
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CFGR1")
+            .field("awd1ch", &self.awd1ch())
+            .field("jauto", &self.jauto())
+            .field("jawd1en", &self.jawd1en())
+            .field("awd1en", &self.awd1en())
+            .field("awd1sgl", &self.awd1sgl())
+            .field("jdiscen", &self.jdiscen())
+            .field("discnum", &self.discnum())
+            .field("discen", &self.discen())
+            .field("autdly", &self.autdly())
+            .field("cont", &self.cont())
+            .field("ovrmod", &self.ovrmod())
+            .field("exten", &self.exten())
+            .field("extsel", &self.extsel())
+            .field("res", &self.res())
+            .field("dmngt", &self.dmngt())
+            .finish()
+    }
+}
+impl W {
+    ///Bits 0:1 - DMNGT
+    #[inline(always)]
+    pub fn dmngt(&mut self) -> DMNGT_W<CFGR1rs> {
+        DMNGT_W::new(self, 0)
+    }
+    ///Bits 2:3 - RES
+    #[inline(always)]
+    pub fn res(&mut self) -> RES_W<CFGR1rs> {
+        RES_W::new(self, 2)
+    }
+    ///Bits 5:9 - EXTSEL
+    #[inline(always)]
+    pub fn extsel(&mut self) -> EXTSEL_W<CFGR1rs> {
+        EXTSEL_W::new(self, 5)
+    }
+    ///Bits 10:11 - EXTEN
+    #[inline(always)]
+    pub fn exten(&mut self) -> EXTEN_W<CFGR1rs> {
+        EXTEN_W::new(self, 10)
+    }
+    ///Bit 12 - OVRMOD
+    #[inline(always)]
+    pub fn ovrmod(&mut self) -> OVRMOD_W<CFGR1rs> {
+        OVRMOD_W::new(self, 12)
+    }
+    ///Bit 13 - CONT
+    #[inline(always)]
+    pub fn cont(&mut self) -> CONT_W<CFGR1rs> {
+        CONT_W::new(self, 13)
+    }
+    ///Bit 14 - AUTDLY
+    #[inline(always)]
+    pub fn autdly(&mut self) -> AUTDLY_W<CFGR1rs> {
+        AUTDLY_W::new(self, 14)
+    }
+    ///Bit 16 - DISCEN
+    #[inline(always)]
+    pub fn discen(&mut self) -> DISCEN_W<CFGR1rs> {
+        DISCEN_W::new(self, 16)
+    }
+    ///Bits 17:19 - DISCNUM
+    #[inline(always)]
+    pub fn discnum(&mut self) -> DISCNUM_W<CFGR1rs> {
+        DISCNUM_W::new(self, 17)
+    }
+    ///Bit 20 - JDISCEN
+    #[inline(always)]
+    pub fn jdiscen(&mut self) -> JDISCEN_W<CFGR1rs> {
+        JDISCEN_W::new(self, 20)
+    }
+    ///Bit 22 - AWD1SGL
+    #[inline(always)]
+    pub fn awd1sgl(&mut self) -> AWD1SGL_W<CFGR1rs> {
+        AWD1SGL_W::new(self, 22)
+    }
+    ///Bit 23 - AWD1EN
+    #[inline(always)]
+    pub fn awd1en(&mut self) -> AWD1EN_W<CFGR1rs> {
+        AWD1EN_W::new(self, 23)
+    }
+    ///Bit 24 - JAWD1EN
+    #[inline(always)]
+    pub fn jawd1en(&mut self) -> JAWD1EN_W<CFGR1rs> {
+        JAWD1EN_W::new(self, 24)
+    }
+    ///Bit 25 - JAUTO
+    #[inline(always)]
+    pub fn jauto(&mut self) -> JAUTO_W<CFGR1rs> {
+        JAUTO_W::new(self, 25)
+    }
+    ///Bits 26:30 - AWD1CH
+    #[inline(always)]
+    pub fn awd1ch(&mut self) -> AWD1CH_W<CFGR1rs> {
+        AWD1CH_W::new(self, 26)
+    }
+}
+/**ADC configuration register
+
+You can [`read`](crate::Reg::read) this register and get [`cfgr1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfgr1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
+
+See register [structure](https://stm32-rs.github.io/stm32-rs/STM32U535.html#ADC1:CFGR1)*/
+pub struct CFGR1rs;
+impl crate::RegisterSpec for CFGR1rs {
+    type Ux = u32;
+}
+///`read()` method returns [`cfgr1::R`](R) reader structure
+impl crate::Readable for CFGR1rs {}
+///`write(|w| ..)` method takes [`cfgr1::W`](W) writer structure
+impl crate::Writable for CFGR1rs {
+    type Safety = crate::Unsafe;
+}
+///`reset()` method sets CFGR1 to value 0x8000_0000
+impl crate::Resettable for CFGR1rs {
+    const RESET_VALUE: u32 = 0x8000_0000;
+}

### external/vendor/stm32u5/src/stm32u535/adc1/cfgr2.rs
@@ -0,0 +1,612 @@
+///Register `CFGR2` reader
+pub type R = crate::R<CFGR2rs>;
+///Register `CFGR2` writer
+pub type W = crate::W<CFGR2rs>;
+/**ROVSE
+
+Value on reset: 0*/
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub enum ROVSE {
+    ///0: Regular oversampling disabled
+    Disabled = 0,
+    ///1: Regular oversampling enabled
+    Enabled = 1,
+}
+impl From<ROVSE> for bool {
+    #[inline(always)]
+    fn from(variant: ROVSE) -> Self {
+        variant as u8 != 0
+    }
+}
+///Field `ROVSE` reader - ROVSE
+pub type ROVSE_R = crate::BitReader<ROVSE>;
+impl ROVSE_R {
+    ///Get enumerated values variant
+    #[inline(always)]
+    pub const fn variant(&self) -> ROVSE {
+        match self.bits {
+            false => ROVSE::Disabled,
+            true => ROVSE::Enabled,
+        }
+    }
+    ///Regular oversampling disabled
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == ROVSE::Disabled
+    }
+    ///Regular oversampling enabled
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == ROVSE::Enabled
+    }
+}
+///Field `ROVSE` writer - ROVSE
+pub type ROVSE_W<'a, REG> = crate::BitWriter<'a, REG, ROVSE>;
+impl<'a, REG> ROVSE_W<'a, REG>
+where
+    REG: crate::Writable + crate::RegisterSpec,
+{
+    ///Regular oversampling disabled
+    #[inline(always)]
+    pub fn disabled(self) -> &'a mut crate::W<REG> {
+        self.variant(ROVSE::Disabled)
+    }
+    ///Regular oversampling enabled
+    #[inline(always)]
+    pub fn enabled(self) -> &'a mut crate::W<REG> {
+        self.variant(ROVSE::Enabled)
+    }
+}
+/**JOVSE
+
+Value on reset: 0*/
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub enum JOVSE {
+    ///0: Injected oversampling disabled
+    Disabled = 0,
+    ///1: Injected oversampling enabled
+    Enabled = 1,
+}
+impl From<JOVSE> for bool {
+    #[inline(always)]
+    fn from(variant: JOVSE) -> Self {
+        variant as u8 != 0
+    }
+}
+///Field `JOVSE` reader - JOVSE
+pub type JOVSE_R = crate::BitReader<JOVSE>;
+impl JOVSE_R {
+    ///Get enumerated values variant
+    #[inline(always)]
+    pub const fn variant(&self) -> JOVSE {
+        match self.bits {
+            false => JOVSE::Disabled,
+            true => JOVSE::Enabled,
+        }
+    }
+    ///Injected oversampling disabled
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == JOVSE::Disabled
+    }
+    ///Injected oversampling enabled
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == JOVSE::Enabled
+    }
+}
+///Field `JOVSE` writer - JOVSE
+pub type JOVSE_W<'a, REG> = crate::BitWriter<'a, REG, JOVSE>;
+impl<'a, REG> JOVSE_W<'a, REG>
+where
+    REG: crate::Writable + crate::RegisterSpec,
+{
+    ///Injected oversampling disabled
+    #[inline(always)]
+    pub fn disabled(self) -> &'a mut crate::W<REG> {
+        self.variant(JOVSE::Disabled)
+    }
+    ///Injected oversampling enabled
+    #[inline(always)]
+    pub fn enabled(self) -> &'a mut crate::W<REG> {
+        self.variant(JOVSE::Enabled)
+    }
+}
+///Field `OVSS` reader - OVSS
+pub type OVSS_R = crate::FieldReader;
+///Field `OVSS` writer - OVSS
+pub type OVSS_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
+/**TROVS
+
+Value on reset: 0*/
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub enum TROVS {
+    ///0: All oversampled conversions for a channel are done consecutively following a trigger
+    Automatic = 0,
+    ///1: Each oversampled conversion for a channel needs a new trigger
+    Triggered = 1,
+}
+impl From<TROVS> for bool {
+    #[inline(always)]
+    fn from(variant: TROVS) -> Self {
+        variant as u8 != 0
+    }
+}
+///Field `TROVS` reader - TROVS
+pub type TROVS_R = crate::BitReader<TROVS>;
+impl TROVS_R {
+    ///Get enumerated values variant
+    #[inline(always)]
+    pub const fn variant(&self) -> TROVS {
+        match self.bits {
+            false => TROVS::Automatic,
+            true => TROVS::Triggered,
+        }
+    }
+    ///All oversampled conversions for a channel are done consecutively following a trigger
+    #[inline(always)]
+    pub fn is_automatic(&self) -> bool {
+        *self == TROVS::Automatic
+    }
+    ///Each oversampled conversion for a channel needs a new trigger
+    #[inline(always)]
+    pub fn is_triggered(&self) -> bool {
+        *self == TROVS::Triggered
+    }
+}
+///Field `TROVS` writer - TROVS
+pub type TROVS_W<'a, REG> = crate::BitWriter<'a, REG, TROVS>;
+impl<'a, REG> TROVS_W<'a, REG>
+where
+    REG: crate::Writable + crate::RegisterSpec,
+{
+    ///All oversampled conversions for a channel are done consecutively following a trigger
+    #[inline(always)]
+    pub fn automatic(self) -> &'a mut crate::W<REG> {
+        self.variant(TROVS::Automatic)
+    }
+    ///Each oversampled conversion for a channel needs a new trigger
+    #[inline(always)]
+    pub fn triggered(self) -> &'a mut crate::W<REG> {
+        self.variant(TROVS::Triggered)
+    }
+}
+/**ROVSM
+
+Value on reset: 0*/
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub enum ROVSM {
+    ///0: When injected conversions are triggered, the oversampling is temporary stopped and continued after the injection sequence (oversampling buffer is maintained during injected sequence)
+    Continued = 0,
+    ///1: When injected conversions are triggered, the current oversampling is aborted and resumed from start after the injection sequence (oversampling buffer is zeroed by injected sequence start)
+    Resumed = 1,
+}
+impl From<ROVSM> for bool {
+    #[inline(always)]
+    fn from(variant: ROVSM) -> Self {
+        variant as u8 != 0
+    }
+}
+///Field `ROVSM` reader - ROVSM
+pub type ROVSM_R = crate::BitReader<ROVSM>;
+impl ROVSM_R {
+    ///Get enumerated values variant
+    #[inline(always)]
+    pub const fn variant(&self) -> ROVSM {
+        match self.bits {
+            false => ROVSM::Continued,
+            true => ROVSM::Resumed,
+        }
+    }
+    ///When injected conversions are triggered, the oversampling is temporary stopped and continued after the injection sequence (oversampling buffer is maintained during injected sequence)
+    #[inline(always)]
+    pub fn is_continued(&self) -> bool {
+        *self == ROVSM::Continued
+    }
+    ///When injected conversions are triggered, the current oversampling is aborted and resumed from start after the injection sequence (oversampling buffer is zeroed by injected sequence start)
+    #[inline(always)]
+    pub fn is_resumed(&self) -> bool {
+        *self == ROVSM::Resumed
+    }
+}
+///Field `ROVSM` writer - ROVSM
+pub type ROVSM_W<'a, REG> = crate::BitWriter<'a, REG, ROVSM>;
+impl<'a, REG> ROVSM_W<'a, REG>
+where
+    REG: crate::Writable + crate::RegisterSpec,
+{
+    ///When injected conversions are triggered, the oversampling is temporary stopped and continued after the injection sequence (oversampling buffer is maintained during injected sequence)
+    #[inline(always)]
+    pub fn continued(self) -> &'a mut crate::W<REG> {
+        self.variant(ROVSM::Continued)
+    }
+    ///When injected conversions are triggered, the current oversampling is aborted and resumed from start after the injection sequence (oversampling buffer is zeroed by injected sequence start)
+    #[inline(always)]
+    pub fn resumed(self) -> &'a mut crate::W<REG> {
+        self.variant(ROVSM::Resumed)
+    }
+}
+/**BULB
+
+Value on reset: 0*/
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub enum BULB {
+    ///0: Bulb sampling mode disabled
+    Disabled = 0,
+    ///1: Bulb sampling mode enabled. The sampling period starts just after the previous end of the conversion.
+    Enabled = 1,
+}
+impl From<BULB> for bool {
+    #[inline(always)]
+    fn from(variant: BULB) -> Self {
+        variant as u8 != 0
+    }
+}
+///Field `BULB` reader - BULB
+pub type BULB_R = crate::BitReader<BULB>;
+impl BULB_R {
+    ///Get enumerated values variant
+    #[inline(always)]
+    pub const fn variant(&self) -> BULB {
+        match self.bits {
+            false => BULB::Disabled,
+            true => BULB::Enabled,
+        }
+    }
+    ///Bulb sampling mode disabled
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == BULB::Disabled
+    }
+    ///Bulb sampling mode enabled. The sampling period starts just after the previous end of the conversion.
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == BULB::Enabled
+    }
+}
+///Field `BULB` writer - BULB
+pub type BULB_W<'a, REG> = crate::BitWriter<'a, REG, BULB>;
+impl<'a, REG> BULB_W<'a, REG>
+where
+    REG: crate::Writable + crate::RegisterSpec,
+{
+    ///Bulb sampling mode disabled
+    #[inline(always)]
+    pub fn disabled(self) -> &'a mut crate::W<REG> {
+        self.variant(BULB::Disabled)
+    }
+    ///Bulb sampling mode enabled. The sampling period starts just after the previous end of the conversion.
+    #[inline(always)]
+    pub fn enabled(self) -> &'a mut crate::W<REG> {
+        self.variant(BULB::Enabled)
+    }
+}
+/**SWTRIG
+
+Value on reset: 0*/
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub enum SWTRIG {
+    ///0: Software trigger starts the conversion for sampling time control trigger mode
+    Disabled = 0,
+    ///1: Software trigger starts the sampling for sampling time control trigger mode
+    Enabled = 1,
+}
+impl From<SWTRIG> for bool {
+    #[inline(always)]
+    fn from(variant: SWTRIG) -> Self {
+        variant as u8 != 0
+    }
+}
+///Field `SWTRIG` reader - SWTRIG
+pub type SWTRIG_R = crate::BitReader<SWTRIG>;
+impl SWTRIG_R {
+    ///Get enumerated values variant
+    #[inline(always)]
+    pub const fn variant(&self) -> SWTRIG {
+        match self.bits {
+            false => SWTRIG::Disabled,
+            true => SWTRIG::Enabled,
+        }
+    }
+    ///Software trigger starts the conversion for sampling time control trigger mode
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == SWTRIG::Disabled
+    }
+    ///Software trigger starts the sampling for sampling time control trigger mode
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == SWTRIG::Enabled
+    }
+}
+///Field `SWTRIG` writer - SWTRIG
+pub type SWTRIG_W<'a, REG> = crate::BitWriter<'a, REG, SWTRIG>;
+impl<'a, REG> SWTRIG_W<'a, REG>
+where
+    REG: crate::Writable + crate::RegisterSpec,
+{
+    ///Software trigger starts the conversion for sampling time control trigger mode
+    #[inline(always)]
+    pub fn disabled(self) -> &'a mut crate::W<REG> {
+        self.variant(SWTRIG::Disabled)
+    }
+    ///Software trigger starts the sampling for sampling time control trigger mode
+    #[inline(always)]
+    pub fn enabled(self) -> &'a mut crate::W<REG> {
+        self.variant(SWTRIG::Enabled)
+    }
+}
+/**SMPTRIG
+
+Value on reset: 0*/
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub enum SMPTRIG {
+    ///0: Sampling time control trigger mode disabled
+    Disabled = 0,
+    ///1: Sampling time control trigger mode enabled
+    Enabled = 1,
+}
+impl From<SMPTRIG> for bool {
+    #[inline(always)]
+    fn from(variant: SMPTRIG) -> Self {
+        variant as u8 != 0
+    }
+}
+///Field `SMPTRIG` reader - SMPTRIG
+pub type SMPTRIG_R = crate::BitReader<SMPTRIG>;
+impl SMPTRIG_R {
+    ///Get enumerated values variant
+    #[inline(always)]
+    pub const fn variant(&self) -> SMPTRIG {
+        match self.bits {
+            false => SMPTRIG::Disabled,
+            true => SMPTRIG::Enabled,
+        }
+    }
+    ///Sampling time control trigger mode disabled
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == SMPTRIG::Disabled
+    }
+    ///Sampling time control trigger mode enabled
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == SMPTRIG::Enabled
+    }
+}
+///Field `SMPTRIG` writer - SMPTRIG
+pub type SMPTRIG_W<'a, REG> = crate::BitWriter<'a, REG, SMPTRIG>;
+impl<'a, REG> SMPTRIG_W<'a, REG>
+where
+    REG: crate::Writable + crate::RegisterSpec,
+{
+    ///Sampling time control trigger mode disabled
+    #[inline(always)]
+    pub fn disabled(self) -> &'a mut crate::W<REG> {
+        self.variant(SMPTRIG::Disabled)
+    }
+    ///Sampling time control trigger mode enabled
+    #[inline(always)]
+    pub fn enabled(self) -> &'a mut crate::W<REG> {
+        self.variant(SMPTRIG::Enabled)
+    }
+}
+///Field `OSR` reader - OSR
+pub type OSR_R = crate::FieldReader<u16>;
+///Field `OSR` writer - OSR
+pub type OSR_W<'a, REG> = crate::FieldWriter<'a, REG, 10, u16, crate::Safe>;
+/**LFTRIG
+
+Value on reset: 0*/
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub enum LFTRIG {
+    ///0: Low-frequency trigger mode disabled
+    Disabled = 0,
+    ///1: Low-frequency trigger mode enabled
+    Enabled = 1,
+}
+impl From<LFTRIG> for bool {
+    #[inline(always)]
+    fn from(variant: LFTRIG) -> Self {
+        variant as u8 != 0
+    }
+}
+///Field `LFTRIG` reader - LFTRIG
+pub type LFTRIG_R = crate::BitReader<LFTRIG>;
+impl LFTRIG_R {
+    ///Get enumerated values variant
+    #[inline(always)]
+    pub const fn variant(&self) -> LFTRIG {
+        match self.bits {
+            false => LFTRIG::Disabled,
+            true => LFTRIG::Enabled,
+        }
+    }
+    ///Low-frequency trigger mode disabled
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == LFTRIG::Disabled
+    }
+    ///Low-frequency trigger mode enabled
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == LFTRIG::Enabled
+    }
+}
+///Field `LFTRIG` writer - LFTRIG
+pub type LFTRIG_W<'a, REG> = crate::BitWriter<'a, REG, LFTRIG>;
+impl<'a, REG> LFTRIG_W<'a, REG>
+where
+    REG: crate::Writable + crate::RegisterSpec,
+{
+    ///Low-frequency trigger mode disabled
+    #[inline(always)]
+    pub fn disabled(self) -> &'a mut crate::W<REG> {
+        self.variant(LFTRIG::Disabled)
+    }
+    ///Low-frequency trigger mode enabled
+    #[inline(always)]
+    pub fn enabled(self) -> &'a mut crate::W<REG> {
+        self.variant(LFTRIG::Enabled)
+    }
+}
+///Field `LSHIFT` reader - LSHIFT
+pub type LSHIFT_R = crate::FieldReader;
+///Field `LSHIFT` writer - LSHIFT
+pub type LSHIFT_W<'a, REG> = crate::FieldWriter<'a, REG, 4, u8, crate::Safe>;
+impl R {
+    ///Bit 0 - ROVSE
+    #[inline(always)]
+    pub fn rovse(&self) -> ROVSE_R {
+        ROVSE_R::new((self.bits & 1) != 0)
+    }
+    ///Bit 1 - JOVSE
+    #[inline(always)]
+    pub fn jovse(&self) -> JOVSE_R {
+        JOVSE_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    ///Bits 5:8 - OVSS
+    #[inline(always)]
+    pub fn ovss(&self) -> OVSS_R {
+        OVSS_R::new(((self.bits >> 5) & 0x0f) as u8)
+    }
+    ///Bit 9 - TROVS
+    #[inline(always)]
+    pub fn trovs(&self) -> TROVS_R {
+        TROVS_R::new(((self.bits >> 9) & 1) != 0)
+    }
+    ///Bit 10 - ROVSM
+    #[inline(always)]
+    pub fn rovsm(&self) -> ROVSM_R {
+        ROVSM_R::new(((self.bits >> 10) & 1) != 0)
+    }
+    ///Bit 13 - BULB
+    #[inline(always)]
+    pub fn bulb(&self) -> BULB_R {
+        BULB_R::new(((self.bits >> 13) & 1) != 0)
+    }
+    ///Bit 14 - SWTRIG
+    #[inline(always)]
+    pub fn swtrig(&self) -> SWTRIG_R {
+        SWTRIG_R::new(((self.bits >> 14) & 1) != 0)
+    }
+    ///Bit 15 - SMPTRIG
+    #[inline(always)]
+    pub fn smptrig(&self) -> SMPTRIG_R {
+        SMPTRIG_R::new(((self.bits >> 15) & 1) != 0)
+    }
+    ///Bits 16:25 - OSR
+    #[inline(always)]
+    pub fn osr(&self) -> OSR_R {
+        OSR_R::new(((self.bits >> 16) & 0x03ff) as u16)
+    }
+    ///Bit 27 - LFTRIG
+    #[inline(always)]
+    pub fn lftrig(&self) -> LFTRIG_R {
+        LFTRIG_R::new(((self.bits >> 27) & 1) != 0)
+    }
+    ///Bits 28:31 - LSHIFT
+    #[inline(always)]
+    pub fn lshift(&self) -> LSHIFT_R {
+        LSHIFT_R::new(((self.bits >> 28) & 0x0f) as u8)
+    }
+}
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CFGR2")
+            .field("lshift", &self.lshift())
+            .field("lftrig", &self.lftrig())
+            .field("osr", &self.osr())
+            .field("smptrig", &self.smptrig())
+            .field("swtrig", &self.swtrig())
+            .field("bulb", &self.bulb())
+            .field("rovsm", &self.rovsm())
+            .field("trovs", &self.trovs())
+            .field("ovss", &self.ovss())
+            .field("jovse", &self.jovse())
+            .field("rovse", &self.rovse())
+            .finish()
+    }
+}
+impl W {
+    ///Bit 0 - ROVSE
+    #[inline(always)]
+    pub fn rovse(&mut self) -> ROVSE_W<CFGR2rs> {
+        ROVSE_W::new(self, 0)
+    }
+    ///Bit 1 - JOVSE
+    #[inline(always)]
+    pub fn jovse(&mut self) -> JOVSE_W<CFGR2rs> {
+        JOVSE_W::new(self, 1)
+    }
+    ///Bits 5:8 - OVSS
+    #[inline(always)]
+    pub fn ovss(&mut self) -> OVSS_W<CFGR2rs> {
+        OVSS_W::new(self, 5)
+    }
+    ///Bit 9 - TROVS
+    #[inline(always)]
+    pub fn trovs(&mut self) -> TROVS_W<CFGR2rs> {
+        TROVS_W::new(self, 9)
+    }
+    ///Bit 10 - ROVSM
+    #[inline(always)]
+    pub fn rovsm(&mut self) -> ROVSM_W<CFGR2rs> {
+        ROVSM_W::new(self, 10)
+    }
+    ///Bit 13 - BULB
+    #[inline(always)]
+    pub fn bulb(&mut self) -> BULB_W<CFGR2rs> {
+        BULB_W::new(self, 13)
+    }
+    ///Bit 14 - SWTRIG
+    #[inline(always)]
+    pub fn swtrig(&mut self) -> SWTRIG_W<CFGR2rs> {
+        SWTRIG_W::new(self, 14)
+    }
+    ///Bit 15 - SMPTRIG
+    #[inline(always)]
+    pub fn smptrig(&mut self) -> SMPTRIG_W<CFGR2rs> {
+        SMPTRIG_W::new(self, 15)
+    }
+    ///Bits 16:25 - OSR
+    #[inline(always)]
+    pub fn osr(&mut self) -> OSR_W<CFGR2rs> {
+        OSR_W::new(self, 16)
+    }
+    ///Bit 27 - LFTRIG
+    #[inline(always)]
+    pub fn lftrig(&mut self) -> LFTRIG_W<CFGR2rs> {
+        LFTRIG_W::new(self, 27)
+    }
+    ///Bits 28:31 - LSHIFT
+    #[inline(always)]
+    pub fn lshift(&mut self) -> LSHIFT_W<CFGR2rs> {
+        LSHIFT_W::new(self, 28)
+    }
+}
+/**ADC configuration register 2
+
+You can [`read`](crate::Reg::read) this register and get [`cfgr2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfgr2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
+
+See register [structure](https://stm32-rs.github.io/stm32-rs/STM32U535.html#ADC1:CFGR2)*/
+pub struct CFGR2rs;
+impl crate::RegisterSpec for CFGR2rs {
+    type Ux = u32;
+}
+///`read()` method returns [`cfgr2::R`](R) reader structure
+impl crate::Readable for CFGR2rs {}
+///`write(|w| ..)` method takes [`cfgr2::W`](W) writer structure
+impl crate::Writable for CFGR2rs {
+    type Safety = crate::Unsafe;
+}
+///`reset()` method sets CFGR2 to value 0
+impl crate::Resettable for CFGR2rs {}

### external/vendor/stm32u5/src/stm32u535/adc1/cr.rs
@@ -0,0 +1,951 @@
+///Register `CR` reader
+pub type R = crate::R<CRrs>;
+///Register `CR` writer
+pub type W = crate::W<CRrs>;
+/**ADEN
+
+Value on reset: 0*/
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub enum ADENR {
+    ///0: ADC is disabled
+    Disabled = 0,
+    ///1: ADC is enabled
+    Enabled = 1,
+}
+impl From<ADENR> for bool {
+    #[inline(always)]
+    fn from(variant: ADENR) -> Self {
+        variant as u8 != 0
+    }
+}
+///Field `ADEN` reader - ADEN
+pub type ADEN_R = crate::BitReader<ADENR>;
+impl ADEN_R {
+    ///Get enumerated values variant
+    #[inline(always)]
+    pub const fn variant(&self) -> ADENR {
+        match self.bits {
+            false => ADENR::Disabled,
+            true => ADENR::Enabled,
+        }
+    }
+    ///ADC is disabled
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == ADENR::Disabled
+    }
+    ///ADC is enabled
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == ADENR::Enabled
+    }
+}
+/**ADEN
+
+Value on reset: 0*/
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub enum ADENW {
+    ///1: Enable the ADC
+    Enabled = 1,
+}
+impl From<ADENW> for bool {
+    #[inline(always)]
+    fn from(variant: ADENW) -> Self {
+        variant as u8 != 0
+    }
+}
+///Field `ADEN` writer - ADEN
+pub type ADEN_W<'a, REG> = crate::BitWriter<'a, REG, ADENW>;
+impl<'a, REG> ADEN_W<'a, REG>
+where
+    REG: crate::Writable + crate::RegisterSpec,
+{
+    ///Enable the ADC
+    #[inline(always)]
+    pub fn enabled(self) -> &'a mut crate::W<REG> {
+        self.variant(ADENW::Enabled)
+    }
+}
+/**ADDIS
+
+Value on reset: 0*/
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub enum ADDISR {
+    ///0: No ADDIS command ongoing
+    NotOngoing = 0,
+    ///1: An ADDIS command is in progress
+    InProgress = 1,
+}
+impl From<ADDISR> for bool {
+    #[inline(always)]
+    fn from(variant: ADDISR) -> Self {
+        variant as u8 != 0
+    }
+}
+///Field `ADDIS` reader - ADDIS
+pub type ADDIS_R = crate::BitReader<ADDISR>;
+impl ADDIS_R {
+    ///Get enumerated values variant
+    #[inline(always)]
+    pub const fn variant(&self) -> ADDISR {
+        match self.bits {
+            false => ADDISR::NotOngoing,
+            true => ADDISR::InProgress,
+        }
+    }
+    ///No ADDIS command ongoing
+    #[inline(always)]
+    pub fn is_not_ongoing(&self) -> bool {
+        *self == ADDISR::NotOngoing
+    }
+    ///An ADDIS command is in progress
+    #[inline(always)]
+    pub fn is_in_progress(&self) -> bool {
+        *self == ADDISR::InProgress
+    }
+}
+/**ADDIS
+
+Value on reset: 0*/
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub enum ADDISW {
+    ///1: Disable the ADC
+    Disable = 1,
+}
+impl From<ADDISW> for bool {
+    #[inline(always)]
+    fn from(variant: ADDISW) -> Self {
+        variant as u8 != 0
+    }
+}
+///Field `ADDIS` writer - ADDIS
+pub type ADDIS_W<'a, REG> = crate::BitWriter<'a, REG, ADDISW>;
+impl<'a, REG> ADDIS_W<'a, REG>
+where
+    REG: crate::Writable + crate::RegisterSpec,
+{
+    ///Disable the ADC
+    #[inline(always)]
+    pub fn disable(self) -> &'a mut crate::W<REG> {
+        self.variant(ADDISW::Disable)
+    }
+}
+/**ADSTART
+
+Value on reset: 0*/
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub enum ADSTARTR {
+    ///0: No ADC regular conversion is ongoing
+    NotActive = 0,
+    ///1: ADC is operating and eventually converting a regular channel
+    Active = 1,
+}
+impl From<ADSTARTR> for bool {
+    #[inline(always)]
+    fn from(variant: ADSTARTR) -> Self {
+        variant as u8 != 0
+    }
+}
+///Field `ADSTART` reader - ADSTART
+pub type ADSTART_R = crate::BitReader<ADSTARTR>;
+impl ADSTART_R {
+    ///Get enumerated values variant
+    #[inline(always)]
+    pub const fn variant(&self) -> ADSTARTR {
+        match self.bits {
+            false => ADSTARTR::NotActive,
+            true => ADSTARTR::Active,
+        }
+    }
+    ///No ADC regular conversion is ongoing
+    #[inline(always)]
+    pub fn is_not_active(&self) -> bool {
+        *self == ADSTARTR::NotActive
+    }
+    ///ADC is operating and eventually converting a regular channel
+    #[inline(always)]
+    pub fn is_active(&self) -> bool {
+        *self == ADSTARTR::Active
+    }
+}
+/**ADSTART
+
+Value on reset: 0*/
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub enum ADSTARTW {
+    ///1: Start regular conversions
+    Start = 1,
+}
+impl From<ADSTARTW> for bool {
+    #[inline(always)]
+    fn from(variant: ADSTARTW) -> Self {
+        variant as u8 != 0
+    }
+}
+///Field `ADSTART` writer - ADSTART
+pub type ADSTART_W<'a, REG> = crate::BitWriter<'a, REG, ADSTARTW>;
+impl<'a, REG> ADSTART_W<'a, REG>
+where
+    REG: crate::Writable + crate::RegisterSpec,
+{
+    ///Start regular conversions
+    #[inline(always)]
+    pub fn start(self) -> &'a mut crate::W<REG> {
+        self.variant(ADSTARTW::Start)
+    }
+}
+/**JADSTART
+
+Value on reset: 0*/
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub enum JADSTARTR {
+    ///0: No ADC injected conversion is ongoing
+    NotActive = 0,
+    ///1: ADC is operating and eventually converting an injected channel
+    Active = 1,
+}
+impl From<JADSTARTR> for bool {
+    #[inline(always)]
+    fn from(variant: JADSTARTR) -> Self {
+        variant as u8 != 0
+    }
+}
+///Field `JADSTART` reader - JADSTART
+pub type JADSTART_R = crate::BitReader<JADSTARTR>;
+impl JADSTART_R {
+    ///Get enumerated values variant
+    #[inline(always)]
+    pub const fn variant(&self) -> JADSTARTR {
+        match self.bits {
+            false => JADSTARTR::NotActive,
+            true => JADSTARTR::Active,
+        }
+    }
+    ///No ADC injected conversion is ongoing
+    #[inline(always)]
+    pub fn is_not_active(&self) -> bool {
+        *self == JADSTARTR::NotActive
+    }
+    ///ADC is operating and eventually converting an injected channel
+    #[inline(always)]
+    pub fn is_active(&self) -> bool {
+        *self == JADSTARTR::Active
+    }
+}
+/**JADSTART
+
+Value on reset: 0*/
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub enum JADSTARTW {
+    ///1: Start injected conversions
+    Start = 1,
+}
+impl From<JADSTARTW> for bool {
+    #[inline(always)]
+    fn from(variant: JADSTARTW) -> Self {
+        variant as u8 != 0
+    }
+}
+///Field `JADSTART` writer - JADSTART
+pub type JADSTART_W<'a, REG> = crate::BitWriter<'a, REG, JADSTARTW>;
+impl<'a, REG> JADSTART_W<'a, REG>
+where
+    REG: crate::Writable + crate::RegisterSpec,
+{
+    ///Start injected conversions
+    #[inline(always)]
+    pub fn start(self) -> &'a mut crate::W<REG> {
+        self.variant(JADSTARTW::Start)
+    }
+}
+/**ADSTP
+
+Value on reset: 0*/
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub enum ADSTPR {
+    ///0: No ADC stop regular conversion command ongoing
+    NotStopping = 0,
+    ///1: ADSTP command is in progress
+    Stopping = 1,
+}
+impl From<ADSTPR> for bool {
+    #[inline(always)]
+    fn from(variant: ADSTPR) -> Self {
+        variant as u8 != 0
+    }
+}
+///Field `ADSTP` reader - ADSTP
+pub type ADSTP_R = crate::BitReader<ADSTPR>;
+impl ADSTP_R {
+    ///Get enumerated values variant
+    #[inline(always)]
+    pub const fn variant(&self) -> ADSTPR {
+        match self.bits {
+            false => ADSTPR::NotStopping,
+            true => ADSTPR::Stopping,
+        }
+    }
+    ///No ADC stop regular conversion command ongoing
+    #[inline(always)]
+    pub fn is_not_stopping(&self) -> bool {
+        *self == ADSTPR::NotStopping
+    }
+    ///ADSTP command is in progress
+    #[inline(always)]
+    pub fn is_stopping(&self) -> bool {
+        *self == ADSTPR::Stopping
+    }
+}
+/**ADSTP
+
+Value on reset: 0*/
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub enum ADSTPW {
+    ///1: Stop regular conversions ongoing
+    StopConversion = 1,
+}
+impl From<ADSTPW> for bool {
+    #[inline(always)]
+    fn from(variant: ADSTPW) -> Self {
+        variant as u8 != 0
+    }
+}
+///Field `ADSTP` writer - ADSTP
+pub type ADSTP_W<'a, REG> = crate::BitWriter<'a, REG, ADSTPW>;
+impl<'a, REG> ADSTP_W<'a, REG>
+where
+    REG: crate::Writable + crate::RegisterSpec,
+{
+    ///Stop regular conversions ongoing
+    #[inline(always)]
+    pub fn stop_conversion(self) -> &'a mut crate::W<REG> {
+        self.variant(ADSTPW::StopConversion)
+    }
+}
+/**JADSTP
+
+Value on reset: 0*/
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub enum JADSTPR {
+    ///0: No ADC stop injected conversion command ongoing
+    NotStopped = 0,
+    ///1: ADSTP command is in progress
+    Stopped = 1,
+}
+impl From<JADSTPR> for bool {
+    #[inline(always)]
+    fn from(variant: JADSTPR) -> Self {
+        variant as u8 != 0
+    }
+}
+///Field `JADSTP` reader - JADSTP
+pub type JADSTP_R = crate::BitReader<JADSTPR>;
+impl JADSTP_R {
+    ///Get enumerated values variant
+    #[inline(always)]
+    pub const fn variant(&self) -> JADSTPR {
+        match self.bits {
+            false => JADSTPR::NotStopped,
+            true => JADSTPR::Stopped,
+        }
+    }
+    ///No ADC stop injected conversion command ongoing
+    #[inline(always)]
+    pub fn is_not_stopped(&self) -> bool {
+        *self == JADSTPR::NotStopped
+    }
+    ///ADSTP command is in progress
+    #[inline(always)]
+    pub fn is_stopped(&self) -> bool {
+        *self == JADSTPR::Stopped
+    }
+}
+/**JADSTP
+
+Value on reset: 0*/
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub enum JADSTPW {
+    ///1: Stop injected conversions ongoing
+    Stop = 1,
+}
+impl From<JADSTPW> for bool {
+    #[inline(always)]
+    fn from(variant: JADSTPW) -> Self {
+        variant as u8 != 0
+    }
+}
+///Field `JADSTP` writer - JADSTP
+pub type JADSTP_W<'a, REG> = crate::BitWriter<'a, REG, JADSTPW>;
+impl<'a, REG> JADSTP_W<'a, REG>
+where
+    REG: crate::Writable + crate::RegisterSpec,
+{
+    ///Stop injected conversions ongoing
+    #[inline(always)]
+    pub fn stop(self) -> &'a mut crate::W<REG> {
+        self.variant(JADSTPW::Stop)
+    }
+}
+/**ADCALLIN
+
+Value on reset: 0*/
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub enum ADCALLIN {
+    ///0: Writing ADCAL launches a calibration without the linearity calibration
+    Disabled = 0,
+    ///1: Writing ADCAL launches a calibration with he linearity calibration
+    Enabled = 1,
+}
+impl From<ADCALLIN> for bool {
+    #[inline(always)]
+    fn from(variant: ADCALLIN) -> Self {
+        variant as u8 != 0
+    }
+}
+///Field `ADCALLIN` reader - ADCALLIN
+pub type ADCALLIN_R = crate::BitReader<ADCALLIN>;
+impl ADCALLIN_R {
+    ///Get enumerated values variant
+    #[inline(always)]
+    pub const fn variant(&self) -> ADCALLIN {
+        match self.bits {
+            false => ADCALLIN::Disabled,
+            true => ADCALLIN::Enabled,
+        }
+    }
+    ///Writing ADCAL launches a calibration without the linearity calibration
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == ADCALLIN::Disabled
+    }
+    ///Writing ADCAL launches a calibration with he linearity calibration
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == ADCALLIN::Enabled
+    }
+}
+///Field `ADCALLIN` writer - ADCALLIN
+pub type ADCALLIN_W<'a, REG> = crate::BitWriter<'a, REG, ADCALLIN>;
+impl<'a, REG> ADCALLIN_W<'a, REG>
+where
+    REG: crate::Writable + crate::RegisterSpec,
+{
+    ///Writing ADCAL launches a calibration without the linearity calibration
+    #[inline(always)]
+    pub fn disabled(self) -> &'a mut crate::W<REG> {
+        self.variant(ADCALLIN::Disabled)
+    }
+    ///Writing ADCAL launches a calibration with he linearity calibration
+    #[inline(always)]
+    pub fn enabled(self) -> &'a mut crate::W<REG> {
+        self.variant(ADCALLIN::Enabled)
+    }
+}
+/**CALINDEX
+
+Value on reset: 0*/
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+#[repr(u8)]
+pub enum CALINDEX {
+    ///0: Offset calibration factor
+    OffsetCalFactor = 0,
+    ///1: Calibration factor 1
+    CalFactor1 = 1,
+    ///2: Calibration factor 2
+    CalFactor2 = 2,
+    ///3: Calibration factor 3
+    CalFactor3 = 3,
+    ///4: Calibration factor 4
+    CalFactor4 = 4,
+    ///5: Calibration factor 5
+    CalFactor5 = 5,
+    ///6: Calibration factor 6
+    CalFactor6 = 6,
+    ///7: Calibration factor 7 and (write access only) internal offset
+    CalFactor7 = 7,
+    ///8: Internal offset (read access only)
+    InternalOffset = 8,
+    ///9: Calibration mode selection
+    CalibrationMode = 9,
+}
+impl From<CALINDEX> for u8 {
+    #[inline(always)]
+    fn from(variant: CALINDEX) -> Self {
+        variant as _
+    }
+}
+impl crate::FieldSpec for CALINDEX {
+    type Ux = u8;
+}
+impl crate::IsEnum for CALINDEX {}
+///Field `CALINDEX` reader - CALINDEX
+pub type CALINDEX_R = crate::FieldReader<CALINDEX>;
+impl CALINDEX_R {
+    ///Get enumerated values variant
+    #[inline(always)]
+    pub const fn variant(&self) -> Option<CALINDEX> {
+        match self.bits {
+            0 => Some(CALINDEX::OffsetCalFactor),
+            1 => Some(CALINDEX::CalFactor1),
+            2 => Some(CALINDEX::CalFactor2),
+            3 => Some(CALINDEX::CalFactor3),
+            4 => Some(CALINDEX::CalFactor4),
+            5 => Some(CALINDEX::CalFactor5),
+            6 => Some(CALINDEX::CalFactor6),
+            7 => Some(CALINDEX::CalFactor7),
+            8 => Some(CALINDEX::InternalOffset),
+            9 => Some(CALINDEX::CalibrationMode),
+            _ => None,
+        }
+    }
+    ///Offset calibration factor
+    #[inline(always)]
+    pub fn is_offset_cal_factor(&self) -> bool {
+        *self == CALINDEX::OffsetCalFactor
+    }
+    ///Calibration factor 1
+    #[inline(always)]
+    pub fn is_cal_factor1(&self) -> bool {
+        *self == CALINDEX::CalFactor1
+    }
+    ///Calibration factor 2
+    #[inline(always)]
+    pub fn is_cal_factor2(&self) -> bool {
+        *self == CALINDEX::CalFactor2
+    }
+    ///Calibration factor 3
+    #[inline(always)]
+    pub fn is_cal_factor3(&self) -> bool {
+        *self == CALINDEX::CalFactor3
+    }
+    ///Calibration factor 4
+    #[inline(always)]
+    pub fn is_cal_factor4(&self) -> bool {
+        *self == CALINDEX::CalFactor4
+    }
+    ///Calibration factor 5
+    #[inline(always)]
+    pub fn is_cal_factor5(&self) -> bool {
+        *self == CALINDEX::CalFactor5
+    }
+    ///Calibration factor 6
+    #[inline(always)]
+    pub fn is_cal_factor6(&self) -> bool {
+        *self == CALINDEX::CalFactor6
+    }
+    ///Calibration factor 7 and (write access only) internal offset
+    #[inline(always)]
+    pub fn is_cal_factor7(&self) -> bool {
+        *self == CALINDEX::CalFactor7
+    }
+    ///Internal offset (read access only)
+    #[inline(always)]
+    pub fn is_internal_offset(&self) -> bool {
+        *self == CALINDEX::InternalOffset
+    }
+    ///Calibration mode selection
+    #[inline(always)]
+    pub fn is_calibration_mode(&self) -> bool {
+        *self == CALINDEX::CalibrationMode
+    }
+}
+///Field `CALINDEX` writer - CALINDEX
+pub type CALINDEX_W<'a, REG> = crate::FieldWriter<'a, REG, 4, CALINDEX>;
+impl<'a, REG> CALINDEX_W<'a, REG>
+where
+    REG: crate::Writable + crate::RegisterSpec,
+    REG::Ux: From<u8>,
+{
+    ///Offset calibration factor
+    #[inline(always)]
+    pub fn offset_cal_factor(self) -> &'a mut crate::W<REG> {
+        self.variant(CALINDEX::OffsetCalFactor)
+    }
+    ///Calibration factor 1
+    #[inline(always)]
+    pub fn cal_factor1(self) -> &'a mut crate::W<REG> {
+        self.variant(CALINDEX::CalFactor1)
+    }
+    ///Calibration factor 2
+    #[inline(always)]
+    pub fn cal_factor2(self) -> &'a mut crate::W<REG> {
+        self.variant(CALINDEX::CalFactor2)
+    }
+    ///Calibration factor 3
+    #[inline(always)]
+    pub fn cal_factor3(self) -> &'a mut crate::W<REG> {
+        self.variant(CALINDEX::CalFactor3)
+    }
+    ///Calibration factor 4
+    #[inline(always)]
+    pub fn cal_factor4(self) -> &'a mut crate::W<REG> {
+        self.variant(CALINDEX::CalFactor4)
+    }
+    ///Calibration factor 5
+    #[inline(always)]
+    pub fn cal_factor5(self) -> &'a mut crate::W<REG> {
+        self.variant(CALINDEX::CalFactor5)
+    }
+    ///Calibration factor 6
+    #[inline(always)]
+    pub fn cal_factor6(self) -> &'a mut crate::W<REG> {
+        self.variant(CALINDEX::CalFactor6)
+    }
+    ///Calibration factor 7 and (write access only) internal offset
+    #[inline(always)]
+    pub fn cal_factor7(self) -> &'a mut crate::W<REG> {
+        self.variant(CALINDEX::CalFactor7)
+    }
+    ///Internal offset (read access only)
+    #[inline(always)]
+    pub fn internal_offset(self) -> &'a mut crate::W<REG> {
+        self.variant(CALINDEX::InternalOffset)
+    }
+    ///Calibration mode selection
+    #[inline(always)]
+    pub fn calibration_mode(self) -> &'a mut crate::W<REG> {
+        self.variant(CALINDEX::CalibrationMode)
+    }
+}
+/**ADVREGEN
+
+Value on reset: 0*/
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub enum ADVREGEN {
+    ///0: ADC voltage regulator disabled
+    Disabled = 0,
+    ///1: ADC voltage regulator enabled
+    Enabled = 1,
+}
+impl From<ADVREGEN> for bool {
+    #[inline(always)]
+    fn from(variant: ADVREGEN) -> Self {
+        variant as u8 != 0
+    }
+}
+///Field `ADVREGEN` reader - ADVREGEN
+pub type ADVREGEN_R = crate::BitReader<ADVREGEN>;
+impl ADVREGEN_R {
+    ///Get enumerated values variant
+    #[inline(always)]
+    pub const fn variant(&self) -> ADVREGEN {
+        match self.bits {
+            false => ADVREGEN::Disabled,
+            true => ADVREGEN::Enabled,
+        }
+    }
+    ///ADC voltage regulator disabled
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == ADVREGEN::Disabled
+    }
+    ///ADC voltage regulator enabled
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == ADVREGEN::Enabled
+    }
+}
+///Field `ADVREGEN` writer - ADVREGEN
+pub type ADVREGEN_W<'a, REG> = crate::BitWriter<'a, REG, ADVREGEN>;
+impl<'a, REG> ADVREGEN_W<'a, REG>
+where
+    REG: crate::Writable + crate::RegisterSpec,
+{
+    ///ADC voltage regulator disabled
+    #[inline(always)]
+    pub fn disabled(self) -> &'a mut crate::W<REG> {
+        self.variant(ADVREGEN::Disabled)
+    }
+    ///ADC voltage regulator enabled
+    #[inline(always)]
+    pub fn enabled(self) -> &'a mut crate::W<REG> {
+        self.variant(ADVREGEN::Enabled)
+    }
+}
+/**DEEPPWD
+
+Value on reset: 1*/
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub enum DEEPPWD {
+    ///0: ADC not in deep-power down
+    Disabled = 0,
+    ///1: ADC in deep-power down
+    Enabled = 1,
+}
+impl From<DEEPPWD> for bool {
+    #[inline(always)]
+    fn from(variant: DEEPPWD) -> Self {
+        variant as u8 != 0
+    }
+}
+///Field `DEEPPWD` reader - DEEPPWD
+pub type DEEPPWD_R = crate::BitReader<DEEPPWD>;
+impl DEEPPWD_R {
+    ///Get enumerated values variant
+    #[inline(always)]
+    pub const fn variant(&self) -> DEEPPWD {
+        match self.bits {
+            false => DEEPPWD::Disabled,
+            true => DEEPPWD::Enabled,
+        }
+    }
+    ///ADC not in deep-power down
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == DEEPPWD::Disabled
+    }
+    ///ADC in deep-power down
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == DEEPPWD::Enabled
+    }
+}
+///Field `DEEPPWD` writer - DEEPPWD
+pub type DEEPPWD_W<'a, REG> = crate::BitWriter<'a, REG, DEEPPWD>;
+impl<'a, REG> DEEPPWD_W<'a, REG>
+where
+    REG: crate::Writable + crate::RegisterSpec,
+{
+    ///ADC not in deep-power down
+    #[inline(always)]
+    pub fn disabled(self) -> &'a mut crate::W<REG> {
+        self.variant(DEEPPWD::Disabled)
+    }
+    ///ADC in deep-power down
+    #[inline(always)]
+    pub fn enabled(self) -> &'a mut crate::W<REG> {
+        self.variant(DEEPPWD::Enabled)
+    }
+}
+/**ADCAL
+
+Value on reset: 0*/
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub enum ADCALR {
+    ///0: Calibration complete
+    NotCalibrating = 0,
+    ///1: Calibration in progress
+    Calibrating = 1,
+}
+impl From<ADCALR> for bool {
+    #[inline(always)]
+    fn from(variant: ADCALR) -> Self {
+        variant as u8 != 0
+    }
+}
+///Field `ADCAL` reader - ADCAL
+pub type ADCAL_R = crate::BitReader<ADCALR>;
+impl ADCAL_R {
+    ///Get enumerated values variant
+    #[inline(always)]
+    pub const fn variant(&self) -> ADCALR {
+        match self.bits {
+            false => ADCALR::NotCalibrating,
+            true => ADCALR::Calibrating,
+        }
+    }
+    ///Calibration complete
+    #[inline(always)]
+    pub fn is_not_calibrating(&self) -> bool {
+        *self == ADCALR::NotCalibrating
+    }
+    ///Calibration in progress
+    #[inline(always)]
+    pub fn is_calibrating(&self) -> bool {
+        *self == ADCALR::Calibrating
+    }
+}
+/**ADCAL
+
+Value on reset: 0*/
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub enum ADCALW {
+    ///1: Calibrate the ADC
+    StartCalibration = 1,
+}
+impl From<ADCALW> for bool {
+    #[inline(always)]
+    fn from(variant: ADCALW) -> Self {
+        variant as u8 != 0
+    }
+}
+///Field `ADCAL` writer - ADCAL
+pub type ADCAL_W<'a, REG> = crate::BitWriter<'a, REG, ADCALW>;
+impl<'a, REG> ADCAL_W<'a, REG>
+where
+    REG: crate::Writable + crate::RegisterSpec,
+{
+    ///Calibrate the ADC
+    #[inline(always)]
+    pub fn start_calibration(self) -> &'a mut crate::W<REG> {
+        self.variant(ADCALW::StartCalibration)
+    }
+}
+impl R {
+    ///Bit 0 - ADEN
+    #[inline(always)]
+    pub fn aden(&self) -> ADEN_R {
+        ADEN_R::new((self.bits & 1) != 0)
+    }
+    ///Bit 1 - ADDIS
+    #[inline(always)]
+    pub fn addis(&self) -> ADDIS_R {
+        ADDIS_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    ///Bit 2 - ADSTART
+    #[inline(always)]
+    pub fn adstart(&self) -> ADSTART_R {
+        ADSTART_R::new(((self.bits >> 2) & 1) != 0)
+    }
+    ///Bit 3 - JADSTART
+    #[inline(always)]
+    pub fn jadstart(&self) -> JADSTART_R {
+        JADSTART_R::new(((self.bits >> 3) & 1) != 0)
+    }
+    ///Bit 4 - ADSTP
+    #[inline(always)]
+    pub fn adstp(&self) -> ADSTP_R {
+        ADSTP_R::new(((self.bits >> 4) & 1) != 0)
+    }
+    ///Bit 5 - JADSTP
+    #[inline(always)]
+    pub fn jadstp(&self) -> JADSTP_R {
+        JADSTP_R::new(((self.bits >> 5) & 1) != 0)
+    }
+    ///Bit 16 - ADCALLIN
+    #[inline(always)]
+    pub fn adcallin(&self) -> ADCALLIN_R {
+        ADCALLIN_R::new(((self.bits >> 16) & 1) != 0)
+    }
+    ///Bits 24:27 - CALINDEX
+    #[inline(always)]
+    pub fn calindex(&self) -> CALINDEX_R {
+        CALINDEX_R::new(((self.bits >> 24) & 0x0f) as u8)
+    }
+    ///Bit 28 - ADVREGEN
+    #[inline(always)]
+    pub fn advregen(&self) -> ADVREGEN_R {
+        ADVREGEN_R::new(((self.bits >> 28) & 1) != 0)
+    }
+    ///Bit 29 - DEEPPWD
+    #[inline(always)]
+    pub fn deeppwd(&self) -> DEEPPWD_R {
+        DEEPPWD_R::new(((self.bits >> 29) & 1) != 0)
+    }
+    ///Bit 31 - ADCAL
+    #[inline(always)]
+    pub fn adcal(&self) -> ADCAL_R {
+        ADCAL_R::new(((self.bits >> 31) & 1) != 0)
+    }
+}
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CR")
+            .field("adcal", &self.adcal())
+            .field("deeppwd", &self.deeppwd())
+            .field("advregen", &self.advregen())
+            .field("calindex", &self.calindex())
+            .field("adcallin", &self.adcallin())
+            .field("jadstp", &self.jadstp())
+            .field("adstp", &self.adstp())
+            .field("jadstart", &self.jadstart())
+            .field("adstart", &self.adstart())
+            .field("addis", &self.addis())
+            .field("aden", &self.aden())
+            .finish()
+    }
+}
+impl W {
+    ///Bit 0 - ADEN
+    #[inline(always)]
+    pub fn aden(&mut self) -> ADEN_W<CRrs> {
+        ADEN_W::new(self, 0)
+    }
+    ///Bit 1 - ADDIS
+    #[inline(always)]
+    pub fn addis(&mut self) -> ADDIS_W<CRrs> {
+        ADDIS_W::new(self, 1)
+    }
+    ///Bit 2 - ADSTART
+    #[inline(always)]
+    pub fn adstart(&mut self) -> ADSTART_W<CRrs> {
+        ADSTART_W::new(self, 2)
+    }
+    ///Bit 3 - JADSTART
+    #[inline(always)]
+    pub fn jadstart(&mut self) -> JADSTART_W<CRrs> {
+        JADSTART_W::new(self, 3)
+    }
+    ///Bit 4 - ADSTP
+    #[inline(always)]
+    pub fn adstp(&mut self) -> ADSTP_W<CRrs> {
+        ADSTP_W::new(self, 4)
+    }
+    ///Bit 5 - JADSTP
+    #[inline(always)]
+    pub fn jadstp(&mut self) -> JADSTP_W<CRrs> {
+        JADSTP_W::new(self, 5)
+    }
+    ///Bit 16 - ADCALLIN
+    #[inline(always)]
+    pub fn adcallin(&mut self) -> ADCALLIN_W<CRrs> {
+        ADCALLIN_W::new(self, 16)
+    }
+    ///Bits 24:27 - CALINDEX
+    #[inline(always)]
+    pub fn calindex(&mut self) -> CALINDEX_W<CRrs> {
+        CALINDEX_W::new(self, 24)
+    }
+    ///Bit 28 - ADVREGEN
+    #[inline(always)]
+    pub fn advregen(&mut self) -> ADVREGEN_W<CRrs> {
+        ADVREGEN_W::new(self, 28)
+    }
+    ///Bit 29 - DEEPPWD
+    #[inline(always)]
+    pub fn deeppwd(&mut self) -> DEEPPWD_W<CRrs> {
+        DEEPPWD_W::new(self, 29)
+    }
+    ///Bit 31 - ADCAL
+    #[inline(always)]
+    pub fn adcal(&mut self) -> ADCAL_W<CRrs> {
+        ADCAL_W::new(self, 31)
+    }
+}
+/**ADC control register
+
+You can [`read`](crate::Reg::read) this register and get [`cr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
+
+See register [structure](https://stm32-rs.github.io/stm32-rs/STM32U535.html#ADC1:CR)*/
+pub struct CRrs;
+impl crate::RegisterSpec for CRrs {
+    type Ux = u32;
+}
+///`read()` method returns [`cr::R`](R) reader structure
+impl crate::Readable for CRrs {}
+///`write(|w| ..)` method takes [`cr::W`](W) writer structure
+impl crate::Writable for CRrs {
+    type Safety = crate::Unsafe;
+}
+///`reset()` method sets CR to value 0x2000_0000
+impl crate::Resettable for CRrs {
+    const RESET_VALUE: u32 = 0x2000_0000;
+}

### external/vendor/stm32u5/src/stm32u535/adc1/difsel.rs
@@ -0,0 +1,331 @@
+///Register `DIFSEL` reader
+pub type R = crate::R<DIFSELrs>;
+///Register `DIFSEL` writer
+pub type W = crate::W<DIFSELrs>;
+/**Differential mode for channel %s
+
+Value on reset: 0*/
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub enum DIFSEL0 {
+    ///0: ADC analog input channel x is configured in single-ended mode
+    SingleEnded = 0,
+    ///1: ADC analog input channel x is configured in differential mode
+    Differential = 1,
+}
+impl From<DIFSEL0> for bool {
+    #[inline(always)]
+    fn from(variant: DIFSEL0) -> Self {
+        variant as u8 != 0
+    }
+}
+///Field `DIFSEL(0-19)` reader - Differential mode for channel %s
+pub type DIFSEL_R = crate::BitReader<DIFSEL0>;
+impl DIFSEL_R {
+    ///Get enumerated values variant
+    #[inline(always)]
+    pub const fn variant(&self) -> DIFSEL0 {
+        match self.bits {
+            false => DIFSEL0::SingleEnded,
+            true => DIFSEL0::Differential,
+        }
+    }
+    ///ADC analog input channel x is configured in single-ended mode
+    #[inline(always)]
+    pub fn is_single_ended(&self) -> bool {
+        *self == DIFSEL0::SingleEnded
+    }
+    ///ADC analog input channel x is configured in differential mode
+    #[inline(always)]
+    pub fn is_differential(&self) -> bool {
+        *self == DIFSEL0::Differential
+    }
+}
+///Field `DIFSEL(0-19)` writer - Differential mode for channel %s
+pub type DIFSEL_W<'a, REG> = crate::BitWriter<'a, REG, DIFSEL0>;
+impl<'a, REG> DIFSEL_W<'a, REG>
+where
+    REG: crate::Writable + crate::RegisterSpec,
+{
+    ///ADC analog input channel x is configured in single-ended mode
+    #[inline(always)]
+    pub fn single_ended(self) -> &'a mut crate::W<REG> {
+        self.variant(DIFSEL0::SingleEnded)
+    }
+    ///ADC analog input channel x is configured in differential mode
+    #[inline(always)]
+    pub fn differential(self) -> &'a mut crate::W<REG> {
+        self.variant(DIFSEL0::Differential)
+    }
+}
+impl R {
+    ///Differential mode for channel (0-19)
+    ///
+    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `DIFSEL0` field.</div>
+    #[inline(always)]
+    pub fn difsel(&self, n: u8) -> DIFSEL_R {
+        #[allow(clippy::no_effect)]
+        [(); 20][n as usize];
+        DIFSEL_R::new(((self.bits >> n) & 1) != 0)
+    }
+    ///Iterator for array of:
+    ///Differential mode for channel (0-19)
+    #[inline(always)]
+    pub fn difsel_iter(&self) -> impl Iterator<Item = DIFSEL_R> + '_ {
+        (0..20).map(move |n| DIFSEL_R::new(((self.bits >> n) & 1) != 0))
+    }
+    ///Bit 0 - Differential mode for channel 0
+    #[inline(always)]
+    pub fn difsel0(&self) -> DIFSEL_R {
+        DIFSEL_R::new((self.bits & 1) != 0)
+    }
+    ///Bit 1 - Differential mode for channel 1
+    #[inline(always)]
+    pub fn difsel1(&self) -> DIFSEL_R {
+        DIFSEL_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    ///Bit 2 - Differential mode for channel 2
+    #[inline(always)]
+    pub fn difsel2(&self) -> DIFSEL_R {
+        DIFSEL_R::new(((self.bits >> 2) & 1) != 0)
+    }
+    ///Bit 3 - Differential mode for channel 3
+    #[inline(always)]
+    pub fn difsel3(&self) -> DIFSEL_R {
+        DIFSEL_R::new(((self.bits >> 3) & 1) != 0)
+    }
+    ///Bit 4 - Differential mode for channel 4
+    #[inline(always)]
+    pub fn difsel4(&self) -> DIFSEL_R {
+        DIFSEL_R::new(((self.bits >> 4) & 1) != 0)
+    }
+    ///Bit 5 - Differential mode for channel 5
+    #[inline(always)]
+    pub fn difsel5(&self) -> DIFSEL_R {
+        DIFSEL_R::new(((self.bits >> 5) & 1) != 0)
+    }
+    ///Bit 6 - Differential mode for channel 6
+    #[inline(always)]
+    pub fn difsel6(&self) -> DIFSEL_R {
+        DIFSEL_R::new(((self.bits >> 6) & 1) != 0)
+    }
+    ///Bit 7 - Differential mode for channel 7
+    #[inline(always)]
+    pub fn difsel7(&self) -> DIFSEL_R {
+        DIFSEL_R::new(((self.bits >> 7) & 1) != 0)
+    }
+    ///Bit 8 - Differential mode for channel 8
+    #[inline(always)]
+    pub fn difsel8(&self) -> DIFSEL_R {
+        DIFSEL_R::new(((self.bits >> 8) & 1) != 0)
+    }
+    ///Bit 9 - Differential mode for channel 9
+    #[inline(always)]
+    pub fn difsel9(&self) -> DIFSEL_R {
+        DIFSEL_R::new(((self.bits >> 9) & 1) != 0)
+    }
+    ///Bit 10 - Differential mode for channel 10
+    #[inline(always)]
+    pub fn difsel10(&self) -> DIFSEL_R {
+        DIFSEL_R::new(((self.bits >> 10) & 1) != 0)
+    }
+    ///Bit 11 - Differential mode for channel 11
+    #[inline(always)]
+    pub fn difsel11(&self) -> DIFSEL_R {
+        DIFSEL_R::new(((self.bits >> 11) & 1) != 0)
+    }
+    ///Bit 12 - Differential mode for channel 12
+    #[inline(always)]
+    pub fn difsel12(&self) -> DIFSEL_R {
+        DIFSEL_R::new(((self.bits >> 12) & 1) != 0)
+    }
+    ///Bit 13 - Differential mode for channel 13
+    #[inline(always)]
+    pub fn difsel13(&self) -> DIFSEL_R {
+        DIFSEL_R::new(((self.bits >> 13) & 1) != 0)
+    }
+    ///Bit 14 - Differential mode for channel 14
+    #[inline(always)]
+    pub fn difsel14(&self) -> DIFSEL_R {
+        DIFSEL_R::new(((self.bits >> 14) & 1) != 0)
+    }
+    ///Bit 15 - Differential mode for channel 15
+    #[inline(always)]
+    pub fn difsel15(&self) -> DIFSEL_R {
+        DIFSEL_R::new(((self.bits >> 15) & 1) != 0)
+    }
+    ///Bit 16 - Differential mode for channel 16
+    #[inline(always)]
+    pub fn difsel16(&self) -> DIFSEL_R {
+        DIFSEL_R::new(((self.bits >> 16) & 1) != 0)
+    }
+    ///Bit 17 - Differential mode for channel 17
+    #[inline(always)]
+    pub fn difsel17(&self) -> DIFSEL_R {
+        DIFSEL_R::new(((self.bits >> 17) & 1) != 0)
+    }
+    ///Bit 18 - Differential mode for channel 18
+    #[inline(always)]
+    pub fn difsel18(&self) -> DIFSEL_R {
+        DIFSEL_R::new(((self.bits >> 18) & 1) != 0)
+    }
+    ///Bit 19 - Differential mode for channel 19
+    #[inline(always)]
+    pub fn difsel19(&self) -> DIFSEL_R {
+        DIFSEL_R::new(((self.bits >> 19) & 1) != 0)
+    }
+}
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("DIFSEL")
+            .field("difsel0", &self.difsel0())
+            .field("difsel1", &self.difsel1())
+            .field("difsel2", &self.difsel2())
+            .field("difsel3", &self.difsel3())
+            .field("difsel4", &self.difsel4())
+            .field("difsel5", &self.difsel5())
+            .field("difsel6", &self.difsel6())
+            .field("difsel7", &self.difsel7())
+            .field("difsel8", &self.difsel8())
+            .field("difsel9", &self.difsel9())
+            .field("difsel10", &self.difsel10())
+            .field("difsel11", &self.difsel11())
+            .field("difsel12", &self.difsel12())
+            .field("difsel13", &self.difsel13())
+            .field("difsel14", &self.difsel14())
+            .field("difsel15", &self.difsel15())
+            .field("difsel16", &self.difsel16())
+            .field("difsel17", &self.difsel17())
+            .field("difsel18", &self.difsel18())
+            .field("difsel19", &self.difsel19())
+            .finish()
+    }
+}
+impl W {
+    ///Differential mode for channel (0-19)
+    ///
+    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `DIFSEL0` field.</div>
+    #[inline(always)]
+    pub fn difsel(&mut self, n: u8) -> DIFSEL_W<DIFSELrs> {
+        #[allow(clippy::no_effect)]
+        [(); 20][n as usize];
+        DIFSEL_W::new(self, n)
+    }
+    ///Bit 0 - Differential mode for channel 0
+    #[inline(always)]
+    pub fn difsel0(&mut self) -> DIFSEL_W<DIFSELrs> {
+        DIFSEL_W::new(self, 0)
+    }
+    ///Bit 1 - Differential mode for channel 1
+    #[inline(always)]
+    pub fn difsel1(&mut self) -> DIFSEL_W<DIFSELrs> {
+        DIFSEL_W::new(self, 1)
+    }
+    ///Bit 2 - Differential mode for channel 2
+    #[inline(always)]
+    pub fn difsel2(&mut self) -> DIFSEL_W<DIFSELrs> {
+        DIFSEL_W::new(self, 2)
+    }
+    ///Bit 3 - Differential mode for channel 3
+    #[inline(always)]
+    pub fn difsel3(&mut self) -> DIFSEL_W<DIFSELrs> {
+        DIFSEL_W::new(self, 3)
+    }
+    ///Bit 4 - Differential mode for channel 4
+    #[inline(always)]
+    pub fn difsel4(&mut self) -> DIFSEL_W<DIFSELrs> {
+        DIFSEL_W::new(self, 4)
+    }
+    ///Bit 5 - Differential mode for channel 5
+    #[inline(always)]
+    pub fn difsel5(&mut self) -> DIFSEL_W<DIFSELrs> {
+        DIFSEL_W::new(self, 5)
+    }
+    ///Bit 6 - Differential mode for channel 6
+    #[inline(always)]
+    pub fn difsel6(&mut self) -> DIFSEL_W<DIFSELrs> {
+        DIFSEL_W::new(self, 6)
+    }
+    ///Bit 7 - Differential mode for channel 7
+    #[inline(always)]
+    pub fn difsel7(&mut self) -> DIFSEL_W<DIFSELrs> {
+        DIFSEL_W::new(self, 7)
+    }
+    ///Bit 8 - Differential mode for channel 8
+    #[inline(always)]
+    pub fn difsel8(&mut self) -> DIFSEL_W<DIFSELrs> {
+        DIFSEL_W::new(self, 8)
+    }
+    ///Bit 9 - Differential mode for channel 9
+    #[inline(always)]
+    pub fn difsel9(&mut self) -> DIFSEL_W<DIFSELrs> {
+        DIFSEL_W::new(self, 9)
+    }
+    ///Bit 10 - Differential mode for channel 10
+    #[inline(always)]
+    pub fn difsel10(&mut self) -> DIFSEL_W<DIFSELrs> {
+        DIFSEL_W::new(self, 10)
+    }
+    ///Bit 11 - Differential mode for channel 11
+    #[inline(always)]
+    pub fn difsel11(&mut self) -> DIFSEL_W<DIFSELrs> {
+        DIFSEL_W::new(self, 11)
+    }
+    ///Bit 12 - Differential mode for channel 12
+    #[inline(always)]
+    pub fn difsel12(&mut self) -> DIFSEL_W<DIFSELrs> {
+        DIFSEL_W::new(self, 12)
+    }
+    ///Bit 13 - Differential mode for channel 13
+    #[inline(always)]
+    pub fn difsel13(&mut self) -> DIFSEL_W<DIFSELrs> {
+        DIFSEL_W::new(self, 13)
+    }
+    ///Bit 14 - Differential mode for channel 14
+    #[inline(always)]
+    pub fn difsel14(&mut self) -> DIFSEL_W<DIFSELrs> {
+        DIFSEL_W::new(self, 14)
+    }
+    ///Bit 15 - Differential mode for channel 15
+    #[inline(always)]
+    pub fn difsel15(&mut self) -> DIFSEL_W<DIFSELrs> {
+        DIFSEL_W::new(self, 15)
+    }
+    ///Bit 16 - Differential mode for channel 16
+    #[inline(always)]
+    pub fn difsel16(&mut self) -> DIFSEL_W<DIFSELrs> {
+        DIFSEL_W::new(self, 16)
+    }
+    ///Bit 17 - Differential mode for channel 17
+    #[inline(always)]
+    pub fn difsel17(&mut self) -> DIFSEL_W<DIFSELrs> {
+        DIFSEL_W::new(self, 17)
+    }
+    ///Bit 18 - Differential mode for channel 18
+    #[inline(always)]
+    pub fn difsel18(&mut self) -> DIFSEL_W<DIFSELrs> {
+        DIFSEL_W::new(self, 18)
+    }
+    ///Bit 19 - Differential mode for channel 19
+    #[inline(always)]
+    pub fn difsel19(&mut self) -> DIFSEL_W<DIFSELrs> {
+        DIFSEL_W::new(self, 19)
+    }
+}
+/**ADC differential mode selection register
+
+You can [`read`](crate::Reg::read) this register and get [`difsel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`difsel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
+
+See register [structure](https://stm32-rs.github.io/stm32-rs/STM32U535.html#ADC1:DIFSEL)*/
+pub struct DIFSELrs;
+impl crate::RegisterSpec for DIFSELrs {
+    type Ux = u32;
+}
+///`read()` method returns [`difsel::R`](R) reader structure
+impl crate::Readable for DIFSELrs {}
+///`write(|w| ..)` method takes [`difsel::W`](W) writer structure
+impl crate::Writable for DIFSELrs {
+    type Safety = crate::Unsafe;
+}
+///`reset()` method sets DIFSEL to value 0
+impl crate::Resettable for DIFSELrs {}

### external/vendor/stm32u5/src/stm32u535/adc1/dr.rs
@@ -0,0 +1,29 @@
+///Register `DR` reader
+pub type R = crate::R<DRrs>;
+///Field `RDATA` reader - RDATA
+pub type RDATA_R = crate::FieldReader<u32>;
+impl R {
+    ///Bits 0:31 - RDATA
+    #[inline(always)]
+    pub fn rdata(&self) -> RDATA_R {
+        RDATA_R::new(self.bits)
+    }
+}
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("DR").field("rdata", &self.rdata()).finish()
+    }
+}
+/**ADC regular Data Register
+
+You can [`read`](crate::Reg::read) this register and get [`dr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
+
+See register [structure](https://stm32-rs.github.io/stm32-rs/STM32U535.html#ADC1:DR)*/
+pub struct DRrs;
+impl crate::RegisterSpec for DRrs {
+    type Ux = u32;
+}
+///`read()` method returns [`dr::R`](R) reader structure
+impl crate::Readable for DRrs {}
+///`reset()` method sets DR to value 0
+impl crate::Resettable for DRrs {}

### external/vendor/stm32u5/src/stm32u535/adc1/gcomp.rs
@@ -0,0 +1,113 @@
+///Register `GCOMP` reader
+pub type R = crate::R<GCOMPrs>;
+///Register `GCOMP` writer
+pub type W = crate::W<GCOMPrs>;
+///Field `GCOMPCOEFF` reader - GCOMPCOEFF
+pub type GCOMPCOEFF_R = crate::FieldReader<u16>;
+///Field `GCOMPCOEFF` writer - GCOMPCOEFF
+pub type GCOMPCOEFF_W<'a, REG> = crate::FieldWriter<'a, REG, 14, u16, crate::Safe>;
+/**GCOMP
+
+Value on reset: 0*/
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub enum GCOMP {
+    ///0: Regular ADC operating mode
+    Disabled = 0,
+    ///1: Gain compensation enabled and applied to all channels
+    Enabled = 1,
+}
+impl From<GCOMP> for bool {
+    #[inline(always)]
+    fn from(variant: GCOMP) -> Self {
+        variant as u8 != 0
+    }
+}
+///Field `GCOMP` reader - GCOMP
+pub type GCOMP_R = crate::BitReader<GCOMP>;
+impl GCOMP_R {
+    ///Get enumerated values variant
+    #[inline(always)]
+    pub const fn variant(&self) -> GCOMP {
+        match self.bits {
+            false => GCOMP::Disabled,
+            true => GCOMP::Enabled,
+        }
+    }
+    ///Regular ADC operating mode
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == GCOMP::Disabled
+    }
+    ///Gain compensation enabled and applied to all channels
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == GCOMP::Enabled
+    }
+}
+///Field `GCOMP` writer - GCOMP
+pub type GCOMP_W<'a, REG> = crate::BitWriter<'a, REG, GCOMP>;
+impl<'a, REG> GCOMP_W<'a, REG>
+where
+    REG: crate::Writable + crate::RegisterSpec,
+{
+    ///Regular ADC operating mode
+    #[inline(always)]
+    pub fn disabled(self) -> &'a mut crate::W<REG> {
+        self.variant(GCOMP::Disabled)
+    }
+    ///Gain compensation enabled and applied to all channels
+    #[inline(always)]
+    pub fn enabled(self) -> &'a mut crate::W<REG> {
+        self.variant(GCOMP::Enabled)
+    }
+}
+impl R {
+    ///Bits 0:13 - GCOMPCOEFF
+    #[inline(always)]
+    pub fn gcompcoeff(&self) -> GCOMPCOEFF_R {
+        GCOMPCOEFF_R::new((self.bits & 0x3fff) as u16)
+    }
+    ///Bit 31 - GCOMP
+    #[inline(always)]
+    pub fn gcomp(&self) -> GCOMP_R {
+        GCOMP_R::new(((self.bits >> 31) & 1) != 0)
+    }
+}
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("GCOMP")
+            .field("gcomp", &self.gcomp())
+            .field("gcompcoeff", &self.gcompcoeff())
+            .finish()
+    }
+}
+impl W {
+    ///Bits 0:13 - GCOMPCOEFF
+    #[inline(always)]
+    pub fn gcompcoeff(&mut self) -> GCOMPCOEFF_W<GCOMPrs> {
+        GCOMPCOEFF_W::new(self, 0)
+    }
+    ///Bit 31 - GCOMP
+    #[inline(always)]
+    pub fn gcomp(&mut self) -> GCOMP_W<GCOMPrs> {
+        GCOMP_W::new(self, 31)
+    }
+}
+/**ADC gain compensation register
+
+You can [`read`](crate::Reg::read) this register and get [`gcomp::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gcomp::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
+
+See register [structure](https://stm32-rs.github.io/stm32-rs/STM32U535.html#ADC1:GCOMP)*/
+pub struct GCOMPrs;
+impl crate::RegisterSpec for GCOMPrs {
+    type Ux = u32;
+}
+///`read()` method returns [`gcomp::R`](R) reader structure
+impl crate::Readable for GCOMPrs {}
+///`write(|w| ..)` method takes [`gcomp::W`](W) writer structure
+impl crate::Writable for GCOMPrs {
+    type Safety = crate::Unsafe;
+}
+///`reset()` method sets GCOMP to value 0
+impl crate::Resettable for GCOMPrs {}

### external/vendor/stm32u5/src/stm32u535/adc1/htr1.rs
@@ -0,0 +1,200 @@
+///Register `HTR1` reader
+pub type R = crate::R<HTR1rs>;
+///Register `HTR1` writer
+pub type W = crate::W<HTR1rs>;
+///Field `HTR1` reader - HTR1
+pub type HTR1_R = crate::FieldReader<u32>;
+///Field `HTR1` writer - HTR1
+pub type HTR1_W<'a, REG> = crate::FieldWriter<'a, REG, 25, u32, crate::Safe>;
+/**AWDFILT1
+
+Value on reset: 0*/
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+#[repr(u8)]
+pub enum AWDFILT1 {
+    ///0: No filtering
+    NoFiltering = 0,
+    ///1: Two consecutive detections generates an AWDx flag or an interrupt
+    Detections2 = 1,
+    ///2: Three consecutive detections generates an AWDx flag or an interrupt
+    Detections3 = 2,
+    ///3: Four consecutive detections generates an AWDx flag or an interrupt
+    Detections4 = 3,
+    ///4: Five consecutive detections generates an AWDx flag or an interrupt
+    Detections5 = 4,
+    ///5: Six consecutive detections generates an AWDx flag or an interrupt
+    Detections6 = 5,
+    ///6: Seven consecutive detections generates an AWDx flag or an interrupt
+    Detections7 = 6,
+    ///7: Eight consecutive detections generates an AWDx flag or an interrupt
+    Detections8 = 7,
+}
+impl From<AWDFILT1> for u8 {
+    #[inline(always)]
+    fn from(variant: AWDFILT1) -> Self {
+        variant as _
+    }
+}
+impl crate::FieldSpec for AWDFILT1 {
+    type Ux = u8;
+}
+impl crate::IsEnum for AWDFILT1 {}
+///Field `AWDFILT1` reader - AWDFILT1
+pub type AWDFILT1_R = crate::FieldReader<AWDFILT1>;
+impl AWDFILT1_R {
+    ///Get enumerated values variant
+    #[inline(always)]
+    pub const fn variant(&self) -> AWDFILT1 {
+        match self.bits {
+            0 => AWDFILT1::NoFiltering,
+            1 => AWDFILT1::Detections2,
+            2 => AWDFILT1::Detections3,
+            3 => AWDFILT1::Detections4,
+            4 => AWDFILT1::Detections5,
+            5 => AWDFILT1::Detections6,
+            6 => AWDFILT1::Detections7,
+            7 => AWDFILT1::Detections8,
+            _ => unreachable!(),
+        }
+    }
+    ///No filtering
+    #[inline(always)]
+    pub fn is_no_filtering(&self) -> bool {
+        *self == AWDFILT1::NoFiltering
+    }
+    ///Two consecutive detections generates an AWDx flag or an interrupt
+    #[inline(always)]
+    pub fn is_detections2(&self) -> bool {
+        *self == AWDFILT1::Detections2
+    }
+    ///Three consecutive detections generates an AWDx flag or an interrupt
+    #[inline(always)]
+    pub fn is_detections3(&self) -> bool {
+        *self == AWDFILT1::Detections3
+    }
+    ///Four consecutive detections generates an AWDx flag or an interrupt
+    #[inline(always)]
+    pub fn is_detections4(&self) -> bool {
+        *self == AWDFILT1::Detections4
+    }
+    ///Five consecutive detections generates an AWDx flag or an interrupt
+    #[inline(always)]
+    pub fn is_detections5(&self) -> bool {
+        *self == AWDFILT1::Detections5
+    }
+    ///Six consecutive detections generates an AWDx flag or an interrupt
+    #[inline(always)]
+    pub fn is_detections6(&self) -> bool {
+        *self == AWDFILT1::Detections6
+    }
+    ///Seven consecutive detections generates an AWDx flag or an interrupt
+    #[inline(always)]
+    pub fn is_detections7(&self) -> bool {
+        *self == AWDFILT1::Detections7
+    }
+    ///Eight consecutive detections generates an AWDx flag or an interrupt
+    #[inline(always)]
+    pub fn is_detections8(&self) -> bool {
+        *self == AWDFILT1::Detections8
+    }
+}
+///Field `AWDFILT1` writer - AWDFILT1
+pub type AWDFILT1_W<'a, REG> = crate::FieldWriter<'a, REG, 3, AWDFILT1, crate::Safe>;
+impl<'a, REG> AWDFILT1_W<'a, REG>
+where
+    REG: crate::Writable + crate::RegisterSpec,
+    REG::Ux: From<u8>,
+{
+    ///No filtering
+    #[inline(always)]
+    pub fn no_filtering(self) -> &'a mut crate::W<REG> {
+        self.variant(AWDFILT1::NoFiltering)
+    }
+    ///Two consecutive detections generates an AWDx flag or an interrupt
+    #[inline(always)]
+    pub fn detections2(self) -> &'a mut crate::W<REG> {
+        self.variant(AWDFILT1::Detections2)
+    }
+    ///Three consecutive detections generates an AWDx flag or an interrupt
+    #[inline(always)]
+    pub fn detections3(self) -> &'a mut crate::W<REG> {
+        self.variant(AWDFILT1::Detections3)
+    }
+    ///Four consecutive detections generates an AWDx flag or an interrupt
+    #[inline(always)]
+    pub fn detections4(self) -> &'a mut crate::W<REG> {
+        self.variant(AWDFILT1::Detections4)
+    }
+    ///Five consecutive detections generates an AWDx flag or an interrupt
+    #[inline(always)]
+    pub fn detections5(self) -> &'a mut crate::W<REG> {
+        self.variant(AWDFILT1::Detections5)
+    }
+    ///Six consecutive detections generates an AWDx flag or an interrupt
+    #[inline(always)]
+    pub fn detections6(self) -> &'a mut crate::W<REG> {
+        self.variant(AWDFILT1::Detections6)
+    }
+    ///Seven consecutive detections generates an AWDx flag or an interrupt
+    #[inline(always)]
+    pub fn detections7(self) -> &'a mut crate::W<REG> {
+        self.variant(AWDFILT1::Detections7)
+    }
+    ///Eight consecutive detections generates an AWDx flag or an interrupt
+    #[inline(always)]
+    pub fn detections8(self) -> &'a mut crate::W<REG> {
+        self.variant(AWDFILT1::Detections8)
+    }
+}
+impl R {
+    ///Bits 0:24 - HTR1
+    #[inline(always)]
+    pub fn htr1(&self) -> HTR1_R {
+        HTR1_R::new(self.bits & 0x01ff_ffff)
+    }
+    ///Bits 29:31 - AWDFILT1
+    #[inline(always)]
+    pub fn awdfilt1(&self) -> AWDFILT1_R {
+        AWDFILT1_R::new(((self.bits >> 29) & 7) as u8)
+    }
+}
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("HTR1")
+            .field("awdfilt1", &self.awdfilt1())
+            .field("htr1", &self.htr1())
+            .finish()
+    }
+}
+impl W {
+    ///Bits 0:24 - HTR1
+    #[inline(always)]
+    pub fn htr1(&mut self) -> HTR1_W<HTR1rs> {
+        HTR1_W::new(self, 0)
+    }
+    ///Bits 29:31 - AWDFILT1
+    #[inline(always)]
+    pub fn awdfilt1(&mut self) -> AWDFILT1_W<HTR1rs> {
+        AWDFILT1_W::new(self, 29)
+    }
+}
+/**ADC watchdog threshold register 1
+
+You can [`read`](crate::Reg::read) this register and get [`htr1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`htr1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
+
+See register [structure](https://stm32-rs.github.io/stm32-rs/STM32U535.html#ADC1:HTR1)*/
+pub struct HTR1rs;
+impl crate::RegisterSpec for HTR1rs {
+    type Ux = u32;
+}
+///`read()` method returns [`htr1::R`](R) reader structure
+impl crate::Readable for HTR1rs {}
+///`write(|w| ..)` method takes [`htr1::W`](W) writer structure
+impl crate::Writable for HTR1rs {
+    type Safety = crate::Unsafe;
+}
+///`reset()` method sets HTR1 to value 0x01ff_ffff
+impl crate::Resettable for HTR1rs {
+    const RESET_VALUE: u32 = 0x01ff_ffff;
+}

### external/vendor/stm32u5/src/stm32u535/adc1/htr2.rs
@@ -0,0 +1,46 @@
+///Register `HTR2` reader
+pub type R = crate::R<HTR2rs>;
+///Register `HTR2` writer
+pub type W = crate::W<HTR2rs>;
+///Field `HTR2` reader - HTR2
+pub type HTR2_R = crate::FieldReader<u32>;
+///Field `HTR2` writer - HTR2
+pub type HTR2_W<'a, REG> = crate::FieldWriter<'a, REG, 25, u32, crate::Safe>;
+impl R {
+    ///Bits 0:24 - HTR2
+    #[inline(always)]
+    pub fn htr2(&self) -> HTR2_R {
+        HTR2_R::new(self.bits & 0x01ff_ffff)
+    }
+}
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("HTR2").field("htr2", &self.htr2()).finish()
+    }
+}
+impl W {
+    ///Bits 0:24 - HTR2
+    #[inline(always)]
+    pub fn htr2(&mut self) -> HTR2_W<HTR2rs> {
+        HTR2_W::new(self, 0)
+    }
+}
+/**ADC watchdog higher threshold register 2
+
+You can [`read`](crate::Reg::read) this register and get [`htr2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`htr2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
+
+See register [structure](https://stm32-rs.github.io/stm32-rs/STM32U535.html#ADC1:HTR2)*/
+pub struct HTR2rs;
+impl crate::RegisterSpec for HTR2rs {
+    type Ux = u32;
+}
+///`read()` method returns [`htr2::R`](R) reader structure
+impl crate::Readable for HTR2rs {}
+///`write(|w| ..)` method takes [`htr2::W`](W) writer structure
+impl crate::Writable for HTR2rs {
+    type Safety = crate::Unsafe;
+}
+///`reset()` method sets HTR2 to value 0x01ff_ffff
+impl crate::Resettable for HTR2rs {
+    const RESET_VALUE: u32 = 0x01ff_ffff;
+}

### external/vendor/stm32u5/src/stm32u535/adc1/htr3.rs
@@ -0,0 +1,46 @@
+///Register `HTR3` reader
+pub type R = crate::R<HTR3rs>;
+///Register `HTR3` writer
+pub type W = crate::W<HTR3rs>;
+///Field `HTR3` reader - HTR3
+pub type HTR3_R = crate::FieldReader<u32>;
+///Field `HTR3` writer - HTR3
+pub type HTR3_W<'a, REG> = crate::FieldWriter<'a, REG, 25, u32, crate::Safe>;
+impl R {
+    ///Bits 0:24 - HTR3
+    #[inline(always)]
+    pub fn htr3(&self) -> HTR3_R {
+        HTR3_R::new(self.bits & 0x01ff_ffff)
+    }
+}
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("HTR3").field("htr3", &self.htr3()).finish()
+    }
+}
+impl W {
+    ///Bits 0:24 - HTR3
+    #[inline(always)]
+    pub fn htr3(&mut self) -> HTR3_W<HTR3rs> {
+        HTR3_W::new(self, 0)
+    }
+}
+/**ADC watchdog higher threshold register 3
+
+You can [`read`](crate::Reg::read) this register and get [`htr3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`htr3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
+
+See register [structure](https://stm32-rs.github.io/stm32-rs/STM32U535.html#ADC1:HTR3)*/
+pub struct HTR3rs;
+impl crate::RegisterSpec for HTR3rs {
+    type Ux = u32;
+}
+///`read()` method returns [`htr3::R`](R) reader structure
+impl crate::Readable for HTR3rs {}
+///`write(|w| ..)` method takes [`htr3::W`](W) writer structure
+impl crate::Writable for HTR3rs {
+    type Safety = crate::Unsafe;
+}
+///`reset()` method sets HTR3 to value 0x01ff_ffff
+impl crate::Resettable for HTR3rs {
+    const RESET_VALUE: u32 = 0x01ff_ffff;
+}

### external/vendor/stm32u5/src/stm32u535/adc1/ier.rs
@@ -0,0 +1,613 @@
+///Register `IER` reader
+pub type R = crate::R<IERrs>;
+///Register `IER` writer
+pub type W = crate::W<IERrs>;
+/**ADRDYIE
+
+Value on reset: 0*/
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub enum ADRDYIE {
+    ///0: ADRDY interrupt disabled
+    Disabled = 0,
+    ///1: ADRDY interrupt enabled. An interrupt is generated when the ADRDY bit is set.
+    Enabled = 1,
+}
+impl From<ADRDYIE> for bool {
+    #[inline(always)]
+    fn from(variant: ADRDYIE) -> Self {
+        variant as u8 != 0
+    }
+}
+///Field `ADRDYIE` reader - ADRDYIE
+pub type ADRDYIE_R = crate::BitReader<ADRDYIE>;
+impl ADRDYIE_R {
+    ///Get enumerated values variant
+    #[inline(always)]
+    pub const fn variant(&self) -> ADRDYIE {
+        match self.bits {
+            false => ADRDYIE::Disabled,
+            true => ADRDYIE::Enabled,
+        }
+    }
+    ///ADRDY interrupt disabled
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == ADRDYIE::Disabled
+    }
+    ///ADRDY interrupt enabled. An interrupt is generated when the ADRDY bit is set.
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == ADRDYIE::Enabled
+    }
+}
+///Field `ADRDYIE` writer - ADRDYIE
+pub type ADRDYIE_W<'a, REG> = crate::BitWriter<'a, REG, ADRDYIE>;
+impl<'a, REG> ADRDYIE_W<'a, REG>
+where
+    REG: crate::Writable + crate::RegisterSpec,
+{
+    ///ADRDY interrupt disabled
+    #[inline(always)]
+    pub fn disabled(self) -> &'a mut crate::W<REG> {
+        self.variant(ADRDYIE::Disabled)
+    }
+    ///ADRDY interrupt enabled. An interrupt is generated when the ADRDY bit is set.
+    #[inline(always)]
+    pub fn enabled(self) -> &'a mut crate::W<REG> {
+        self.variant(ADRDYIE::Enabled)
+    }
+}
+/**EOSMPIE
+
+Value on reset: 0*/
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub enum EOSMPIE {
+    ///0: EOSMP interrupt disabled
+    Disabled = 0,
+    ///1: EOSMP interrupt enabled. An interrupt is generated when the EOSMP bit is set.
+    Enabled = 1,
+}
+impl From<EOSMPIE> for bool {
+    #[inline(always)]
+    fn from(variant: EOSMPIE) -> Self {
+        variant as u8 != 0
+    }
+}
+///Field `EOSMPIE` reader - EOSMPIE
+pub type EOSMPIE_R = crate::BitReader<EOSMPIE>;
+impl EOSMPIE_R {
+    ///Get enumerated values variant
+    #[inline(always)]
+    pub const fn variant(&self) -> EOSMPIE {
+        match self.bits {
+            false => EOSMPIE::Disabled,
+            true => EOSMPIE::Enabled,
+        }
+    }
+    ///EOSMP interrupt disabled
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == EOSMPIE::Disabled
+    }
+    ///EOSMP interrupt enabled. An interrupt is generated when the EOSMP bit is set.
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == EOSMPIE::Enabled
+    }
+}
+///Field `EOSMPIE` writer - EOSMPIE
+pub type EOSMPIE_W<'a, REG> = crate::BitWriter<'a, REG, EOSMPIE>;
+impl<'a, REG> EOSMPIE_W<'a, REG>
+where
+    REG: crate::Writable + crate::RegisterSpec,
+{
+    ///EOSMP interrupt disabled
+    #[inline(always)]
+    pub fn disabled(self) -> &'a mut crate::W<REG> {
+        self.variant(EOSMPIE::Disabled)
+    }
+    ///EOSMP interrupt enabled. An interrupt is generated when the EOSMP bit is set.
+    #[inline(always)]
+    pub fn enabled(self) -> &'a mut crate::W<REG> {
+        self.variant(EOSMPIE::Enabled)
+    }
+}
+/**EOCIE
+
+Value on reset: 0*/
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub enum EOCIE {
+    ///0: EOC interrupt disabled
+    Disabled = 0,
+    ///1: EOC interrupt enabled. An interrupt is generated when the EOC bit is set.
+    Enabled = 1,
+}
+impl From<EOCIE> for bool {
+    #[inline(always)]
+    fn from(variant: EOCIE) -> Self {
+        variant as u8 != 0
+    }
+}
+///Field `EOCIE` reader - EOCIE
+pub type EOCIE_R = crate::BitReader<EOCIE>;
+impl EOCIE_R {
+    ///Get enumerated values variant
+    #[inline(always)]
+    pub const fn variant(&self) -> EOCIE {
+        match self.bits {
+            false => EOCIE::Disabled,
+            true => EOCIE::Enabled,
+        }
+    }
+    ///EOC interrupt disabled
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == EOCIE::Disabled
+    }
+    ///EOC interrupt enabled. An interrupt is generated when the EOC bit is set.
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == EOCIE::Enabled
+    }
+}
+///Field `EOCIE` writer - EOCIE
+pub type EOCIE_W<'a, REG> = crate::BitWriter<'a, REG, EOCIE>;
+impl<'a, REG> EOCIE_W<'a, REG>
+where
+    REG: crate::Writable + crate::RegisterSpec,
+{
+    ///EOC interrupt disabled
+    #[inline(always)]
+    pub fn disabled(self) -> &'a mut crate::W<REG> {
+        self.variant(EOCIE::Disabled)
+    }
+    ///EOC interrupt enabled. An interrupt is generated when the EOC bit is set.
+    #[inline(always)]
+    pub fn enabled(self) -> &'a mut crate::W<REG> {
+        self.variant(EOCIE::Enabled)
+    }
+}
+/**EOSIE
+
+Value on reset: 0*/
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub enum EOSIE {
+    ///0: EOS interrupt disabled
+    Disabled = 0,
+    ///1: EOS interrupt enabled. An interrupt is generated when the EOS bit is set.
+    Enabled = 1,
+}
+impl From<EOSIE> for bool {
+    #[inline(always)]
+    fn from(variant: EOSIE) -> Self {
+        variant as u8 != 0
+    }
+}
+///Field `EOSIE` reader - EOSIE
+pub type EOSIE_R = crate::BitReader<EOSIE>;
+impl EOSIE_R {
+    ///Get enumerated values variant
+    #[inline(always)]
+    pub const fn variant(&self) -> EOSIE {
+        match self.bits {
+            false => EOSIE::Disabled,
+            true => EOSIE::Enabled,
+        }
+    }
+    ///EOS interrupt disabled
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == EOSIE::Disabled
+    }
+    ///EOS interrupt enabled. An interrupt is generated when the EOS bit is set.
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == EOSIE::Enabled
+    }
+}
+///Field `EOSIE` writer - EOSIE
+pub type EOSIE_W<'a, REG> = crate::BitWriter<'a, REG, EOSIE>;
+impl<'a, REG> EOSIE_W<'a, REG>
+where
+    REG: crate::Writable + crate::RegisterSpec,
+{
+    ///EOS interrupt disabled
+    #[inline(always)]
+    pub fn disabled(self) -> &'a mut crate::W<REG> {
+        self.variant(EOSIE::Disabled)
+    }
+    ///EOS interrupt enabled. An interrupt is generated when the EOS bit is set.
+    #[inline(always)]
+    pub fn enabled(self) -> &'a mut crate::W<REG> {
+        self.variant(EOSIE::Enabled)
+    }
+}
+/**OVRIE
+
+Value on reset: 0*/
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub enum OVRIE {
+    ///0: Overrun interrupt disabled
+    Disabled = 0,
+    ///1: Overrun interrupt enabled. An interrupt is generated when the OVR bit is set.
+    Enabled = 1,
+}
+impl From<OVRIE> for bool {
+    #[inline(always)]
+    fn from(variant: OVRIE) -> Self {
+        variant as u8 != 0
+    }
+}
+///Field `OVRIE` reader - OVRIE
+pub type OVRIE_R = crate::BitReader<OVRIE>;
+impl OVRIE_R {
+    ///Get enumerated values variant
+    #[inline(always)]
+    pub const fn variant(&self) -> OVRIE {
+        match self.bits {
+            false => OVRIE::Disabled,
+            true => OVRIE::Enabled,
+        }
+    }
+    ///Overrun interrupt disabled
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == OVRIE::Disabled
+    }
+    ///Overrun interrupt enabled. An interrupt is generated when the OVR bit is set.
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == OVRIE::Enabled
+    }
+}
+///Field `OVRIE` writer - OVRIE
+pub type OVRIE_W<'a, REG> = crate::BitWriter<'a, REG, OVRIE>;
+impl<'a, REG> OVRIE_W<'a, REG>
+where
+    REG: crate::Writable + crate::RegisterSpec,
+{
+    ///Overrun interrupt disabled
+    #[inline(always)]
+    pub fn disabled(self) -> &'a mut crate::W<REG> {
+        self.variant(OVRIE::Disabled)
+    }
+    ///Overrun interrupt enabled. An interrupt is generated when the OVR bit is set.
+    #[inline(always)]
+    pub fn enabled(self) -> &'a mut crate::W<REG> {
+        self.variant(OVRIE::Enabled)
+    }
+}
+/**JEOCIE
+
+Value on reset: 0*/
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub enum JEOCIE {
+    ///0: JEOC interrupt disable
+    Disabled = 0,
+    ///1: JEOC interrupt enabled. An interrupt is generated when the JEOC bit is set.
+    Enabled = 1,
+}
+impl From<JEOCIE> for bool {
+    #[inline(always)]
+    fn from(variant: JEOCIE) -> Self {
+        variant as u8 != 0
+    }
+}
+///Field `JEOCIE` reader - JEOCIE
+pub type JEOCIE_R = crate::BitReader<JEOCIE>;
+impl JEOCIE_R {
+    ///Get enumerated values variant
+    #[inline(always)]
+    pub const fn variant(&self) -> JEOCIE {
+        match self.bits {
+            false => JEOCIE::Disabled,
+            true => JEOCIE::Enabled,
+        }
+    }
+    ///JEOC interrupt disable
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == JEOCIE::Disabled
+    }
+    ///JEOC interrupt enabled. An interrupt is generated when the JEOC bit is set.
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == JEOCIE::Enabled
+    }
+}
+///Field `JEOCIE` writer - JEOCIE
+pub type JEOCIE_W<'a, REG> = crate::BitWriter<'a, REG, JEOCIE>;
+impl<'a, REG> JEOCIE_W<'a, REG>
+where
+    REG: crate::Writable + crate::RegisterSpec,
+{
+    ///JEOC interrupt disable
+    #[inline(always)]
+    pub fn disabled(self) -> &'a mut crate::W<REG> {
+        self.variant(JEOCIE::Disabled)
+    }
+    ///JEOC interrupt enabled. An interrupt is generated when the JEOC bit is set.
+    #[inline(always)]
+    pub fn enabled(self) -> &'a mut crate::W<REG> {
+        self.variant(JEOCIE::Enabled)
+    }
+}
+/**JEOSIE
+
+Value on reset: 0*/
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub enum JEOSIE {
+    ///0: JEOS interrupt disabled
+    Disabled = 0,
+    ///1: JEOS interrupt enabled. An interrupt is generated when the JEOS bit is set.
+    Enabled = 1,
+}
+impl From<JEOSIE> for bool {
+    #[inline(always)]
+    fn from(variant: JEOSIE) -> Self {
+        variant as u8 != 0
+    }
+}
+///Field `JEOSIE` reader - JEOSIE
+pub type JEOSIE_R = crate::BitReader<JEOSIE>;
+impl JEOSIE_R {
+    ///Get enumerated values variant
+    #[inline(always)]
+    pub const fn variant(&self) -> JEOSIE {
+        match self.bits {
+            false => JEOSIE::Disabled,
+            true => JEOSIE::Enabled,
+        }
+    }
+    ///JEOS interrupt disabled
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == JEOSIE::Disabled
+    }
+    ///JEOS interrupt enabled. An interrupt is generated when the JEOS bit is set.
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == JEOSIE::Enabled
+    }
+}
+///Field `JEOSIE` writer - JEOSIE
+pub type JEOSIE_W<'a, REG> = crate::BitWriter<'a, REG, JEOSIE>;
+impl<'a, REG> JEOSIE_W<'a, REG>
+where
+    REG: crate::Writable + crate::RegisterSpec,
+{
+    ///JEOS interrupt disabled
+    #[inline(always)]
+    pub fn disabled(self) -> &'a mut crate::W<REG> {
+        self.variant(JEOSIE::Disabled)
+    }
+    ///JEOS interrupt enabled. An interrupt is generated when the JEOS bit is set.
+    #[inline(always)]
+    pub fn enabled(self) -> &'a mut crate::W<REG> {
+        self.variant(JEOSIE::Enabled)
+    }
+}
+/**Analog watchdog %s interrupt enable
+
+Value on reset: 0*/
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub enum AWD1IE {
+    ///0: Analog watchdog x interrupt disabled
+    Disabled = 0,
+    ///1: Analog watchdog x interrupt enabled
+    Enabled = 1,
+}
+impl From<AWD1IE> for bool {
+    #[inline(always)]
+    fn from(variant: AWD1IE) -> Self {
+        variant as u8 != 0
+    }
+}
+///Field `AWDIE(1-3)` reader - Analog watchdog %s interrupt enable
+pub type AWDIE_R = crate::BitReader<AWD1IE>;
+impl AWDIE_R {
+    ///Get enumerated values variant
+    #[inline(always)]
+    pub const fn variant(&self) -> AWD1IE {
+        match self.bits {
+            false => AWD1IE::Disabled,
+            true => AWD1IE::Enabled,
+        }
+    }
+    ///Analog watchdog x interrupt disabled
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == AWD1IE::Disabled
+    }
+    ///Analog watchdog x interrupt enabled
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == AWD1IE::Enabled
+    }
+}
+///Field `AWDIE(1-3)` writer - Analog watchdog %s interrupt enable
+pub type AWDIE_W<'a, REG> = crate::BitWriter<'a, REG, AWD1IE>;
+impl<'a, REG> AWDIE_W<'a, REG>
+where
+    REG: crate::Writable + crate::RegisterSpec,
+{
+    ///Analog watchdog x interrupt disabled
+    #[inline(always)]
+    pub fn disabled(self) -> &'a mut crate::W<REG> {
+        self.variant(AWD1IE::Disabled)
+    }
+    ///Analog watchdog x interrupt enabled
+    #[inline(always)]
+    pub fn enabled(self) -> &'a mut crate::W<REG> {
+        self.variant(AWD1IE::Enabled)
+    }
+}
+impl R {
+    ///Bit 0 - ADRDYIE
+    #[inline(always)]
+    pub fn adrdyie(&self) -> ADRDYIE_R {
+        ADRDYIE_R::new((self.bits & 1) != 0)
+    }
+    ///Bit 1 - EOSMPIE
+    #[inline(always)]
+    pub fn eosmpie(&self) -> EOSMPIE_R {
+        EOSMPIE_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    ///Bit 2 - EOCIE
+    #[inline(always)]
+    pub fn eocie(&self) -> EOCIE_R {
+        EOCIE_R::new(((self.bits >> 2) & 1) != 0)
+    }
+    ///Bit 3 - EOSIE
+    #[inline(always)]
+    pub fn eosie(&self) -> EOSIE_R {
+        EOSIE_R::new(((self.bits >> 3) & 1) != 0)
+    }
+    ///Bit 4 - OVRIE
+    #[inline(always)]
+    pub fn ovrie(&self) -> OVRIE_R {
+        OVRIE_R::new(((self.bits >> 4) & 1) != 0)
+    }
+    ///Bit 5 - JEOCIE
+    #[inline(always)]
+    pub fn jeocie(&self) -> JEOCIE_R {
+        JEOCIE_R::new(((self.bits >> 5) & 1) != 0)
+    }
+    ///Bit 6 - JEOSIE
+    #[inline(always)]
+    pub fn jeosie(&self) -> JEOSIE_R {
+        JEOSIE_R::new(((self.bits >> 6) & 1) != 0)
+    }
+    ///Analog watchdog (1-3) interrupt enable
+    ///
+    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `AWD1IE` field.</div>
+    #[inline(always)]
+    pub fn awdie(&self, n: u8) -> AWDIE_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        AWDIE_R::new(((self.bits >> (n + 7)) & 1) != 0)
+    }
+    ///Iterator for array of:
+    ///Analog watchdog (1-3) interrupt enable
+    #[inline(always)]
+    pub fn awdie_iter(&self) -> impl Iterator<Item = AWDIE_R> + '_ {
+        (0..3).map(move |n| AWDIE_R::new(((self.bits >> (n + 7)) & 1) != 0))
+    }
+    ///Bit 7 - Analog watchdog 1 interrupt enable
+    #[inline(always)]
+    pub fn awd1ie(&self) -> AWDIE_R {
+        AWDIE_R::new(((self.bits >> 7) & 1) != 0)
+    }
+    ///Bit 8 - Analog watchdog 2 interrupt enable
+    #[inline(always)]
+    pub fn awd2ie(&self) -> AWDIE_R {
+        AWDIE_R::new(((self.bits >> 8) & 1) != 0)
+    }
+    ///Bit 9 - Analog watchdog 3 interrupt enable
+    #[inline(always)]
+    pub fn awd3ie(&self) -> AWDIE_R {
+        AWDIE_R::new(((self.bits >> 9) & 1) != 0)
+    }
+}
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("IER")
+            .field("awd1ie", &self.awd1ie())
+            .field("awd2ie", &self.awd2ie())
+            .field("awd3ie", &self.awd3ie())
+            .field("jeosie", &self.jeosie())
+            .field("jeocie", &self.jeocie())
+            .field("ovrie", &self.ovrie())
+            .field("eosie", &self.eosie())
+            .field("eocie", &self.eocie())
+            .field("eosmpie", &self.eosmpie())
+            .field("adrdyie", &self.adrdyie())
+            .finish()
+    }
+}
+impl W {
+    ///Bit 0 - ADRDYIE
+    #[inline(always)]
+    pub fn adrdyie(&mut self) -> ADRDYIE_W<IERrs> {
+        ADRDYIE_W::new(self, 0)
+    }
+    ///Bit 1 - EOSMPIE
+    #[inline(always)]
+    pub fn eosmpie(&mut self) -> EOSMPIE_W<IERrs> {
+        EOSMPIE_W::new(self, 1)
+    }
+    ///Bit 2 - EOCIE
+    #[inline(always)]
+    pub fn eocie(&mut self) -> EOCIE_W<IERrs> {
+        EOCIE_W::new(self, 2)
+    }
+    ///Bit 3 - EOSIE
+    #[inline(always)]
+    pub fn eosie(&mut self) -> EOSIE_W<IERrs> {
+        EOSIE_W::new(self, 3)
+    }
+    ///Bit 4 - OVRIE
+    #[inline(always)]
+    pub fn ovrie(&mut self) -> OVRIE_W<IERrs> {
+        OVRIE_W::new(self, 4)
+    }
+    ///Bit 5 - JEOCIE
+    #[inline(always)]
+    pub fn jeocie(&mut self) -> JEOCIE_W<IERrs> {
+        JEOCIE_W::new(self, 5)
+    }
+    ///Bit 6 - JEOSIE
+    #[inline(always)]
+    pub fn jeosie(&mut self) -> JEOSIE_W<IERrs> {
+        JEOSIE_W::new(self, 6)
+    }
+    ///Analog watchdog (1-3) interrupt enable
+    ///
+    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `AWD1IE` field.</div>
+    #[inline(always)]
+    pub fn awdie(&mut self, n: u8) -> AWDIE_W<IERrs> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        AWDIE_W::new(self, n + 7)
+    }
+    ///Bit 7 - Analog watchdog 1 interrupt enable
+    #[inline(always)]
+    pub fn awd1ie(&mut self) -> AWDIE_W<IERrs> {
+        AWDIE_W::new(self, 7)
+    }
+    ///Bit 8 - Analog watchdog 2 interrupt enable
+    #[inline(always)]
+    pub fn awd2ie(&mut self) -> AWDIE_W<IERrs> {
+        AWDIE_W::new(self, 8)
+    }
+    ///Bit 9 - Analog watchdog 3 interrupt enable
+    #[inline(always)]
+    pub fn awd3ie(&mut self) -> AWDIE_W<IERrs> {
+        AWDIE_W::new(self, 9)
+    }
+}
+/**ADC interrupt enable register
+
+You can [`read`](crate::Reg::read) this register and get [`ier::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ier::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
+
+See register [structure](https://stm32-rs.github.io/stm32-rs/STM32U535.html#ADC1:IER)*/
+pub struct IERrs;
+impl crate::RegisterSpec for IERrs {
+    type Ux = u32;
+}
+///`read()` method returns [`ier::R`](R) reader structure
+impl crate::Readable for IERrs {}
+///`write(|w| ..)` method takes [`ier::W`](W) writer structure
+impl crate::Writable for IERrs {
+    type Safety = crate::Unsafe;
+}
+///`reset()` method sets IER to value 0
+impl crate::Resettable for IERrs {}

### external/vendor/stm32u5/src/stm32u535/adc1/isr.rs
@@ -0,0 +1,738 @@
+///Register `ISR` reader
+pub type R = crate::R<ISRrs>;
+///Register `ISR` writer
+pub type W = crate::W<ISRrs>;
+/**ADRDY
+
+Value on reset: 0*/
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub enum ADRDYR {
+    ///0: ADC not yet ready to start conversion (or the flag event was already acknowledged and cleared by software)
+    NotReady = 0,
+    ///1: ADC is ready to start conversion
+    Ready = 1,
+}
+impl From<ADRDYR> for bool {
+    #[inline(always)]
+    fn from(variant: ADRDYR) -> Self {
+        variant as u8 != 0
+    }
+}
+///Field `ADRDY` reader - ADRDY
+pub type ADRDY_R = crate::BitReader<ADRDYR>;
+impl ADRDY_R {
+    ///Get enumerated values variant
+    #[inline(always)]
+    pub const fn variant(&self) -> ADRDYR {
+        match self.bits {
+            false => ADRDYR::NotReady,
+            true => ADRDYR::Ready,
+        }
+    }
+    ///ADC not yet ready to start conversion (or the flag event was already acknowledged and cleared by software)
+    #[inline(always)]
+    pub fn is_not_ready(&self) -> bool {
+        *self == ADRDYR::NotReady
+    }
+    ///ADC is ready to start conversion
+    #[inline(always)]
+    pub fn is_ready(&self) -> bool {
+        *self == ADRDYR::Ready
+    }
+}
+/**ADRDY
+
+Value on reset: 0*/
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub enum ADRDYW {
+    ///1: Clear the ADC ready flag
+    Clear = 1,
+}
+impl From<ADRDYW> for bool {
+    #[inline(always)]
+    fn from(variant: ADRDYW) -> Self {
+        variant as u8 != 0
+    }
+}
+///Field `ADRDY` writer - ADRDY
+pub type ADRDY_W<'a, REG> = crate::BitWriter<'a, REG, ADRDYW>;
+impl<'a, REG> ADRDY_W<'a, REG>
+where
+    REG: crate::Writable + crate::RegisterSpec,
+{
+    ///Clear the ADC ready flag
+    #[inline(always)]
+    pub fn clear(self) -> &'a mut crate::W<REG> {
+        self.variant(ADRDYW::Clear)
+    }
+}
+/**EOSMP
+
+Value on reset: 0*/
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub enum EOSMPR {
+    ///0: Not at the end of the sampling phase (or the flag event was already acknowledged and cleared by software)
+    NotAtEnd = 0,
+    ///1: End of sampling phase reached
+    AtEnd = 1,
+}
+impl From<EOSMPR> for bool {
+    #[inline(always)]
+    fn from(variant: EOSMPR) -> Self {
+        variant as u8 != 0
+    }
+}
+///Field `EOSMP` reader - EOSMP
+pub type EOSMP_R = crate::BitReader<EOSMPR>;
+impl EOSMP_R {
+    ///Get enumerated values variant
+    #[inline(always)]
+    pub const fn variant(&self) -> EOSMPR {
+        match self.bits {
+            false => EOSMPR::NotAtEnd,
+            true => EOSMPR::AtEnd,
+        }
+    }
+    ///Not at the end of the sampling phase (or the flag event was already acknowledged and cleared by software)
+    #[inline(always)]
+    pub fn is_not_at_end(&self) -> bool {
+        *self == EOSMPR::NotAtEnd
+    }
+    ///End of sampling phase reached
+    #[inline(always)]
+    pub fn is_at_end(&self) -> bool {
+        *self == EOSMPR::AtEnd
+    }
+}
+/**EOSMP
+
+Value on reset: 0*/
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub enum EOSMPW {
+    ///1: Clear the sampling phase flag
+    Clear = 1,
+}
+impl From<EOSMPW> for bool {
+    #[inline(always)]
+    fn from(variant: EOSMPW) -> Self {
+        variant as u8 != 0
+    }
+}
+///Field `EOSMP` writer - EOSMP
+pub type EOSMP_W<'a, REG> = crate::BitWriter<'a, REG, EOSMPW>;
+impl<'a, REG> EOSMP_W<'a, REG>
+where
+    REG: crate::Writable + crate::RegisterSpec,
+{
+    ///Clear the sampling phase flag
+    #[inline(always)]
+    pub fn clear(self) -> &'a mut crate::W<REG> {
+        self.variant(EOSMPW::Clear)
+    }
+}
+/**EOC
+
+Value on reset: 0*/
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub enum EOCR {
+    ///0: Regular channel conversion not complete (or the flag event was already acknowledged and cleared by software)
+    NotComplete = 0,
+    ///1: Regular channel conversion complete
+    Complete = 1,
+}
+impl From<EOCR> for bool {
+    #[inline(always)]
+    fn from(variant: EOCR) -> Self {
+        variant as u8 != 0
+    }
+}
+///Field `EOC` reader - EOC
+pub type EOC_R = crate::BitReader<EOCR>;
+impl EOC_R {
+    ///Get enumerated values variant
+    #[inline(always)]
+    pub const fn variant(&self) -> EOCR {
+        match self.bits {
+            false => EOCR::NotComplete,
+            true => EOCR::Complete,
+        }
+    }
+    ///Regular channel conversion not complete (or the flag event was already acknowledged and cleared by software)
+    #[inline(always)]
+    pub fn is_not_complete(&self) -> bool {
+        *self == EOCR::NotComplete
+    }
+    ///Regular channel conversion complete
+    #[inline(always)]
+    pub fn is_complete(&self) -> bool {
+        *self == EOCR::Complete
+    }
+}
+/**EOC
+
+Value on reset: 0*/
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub enum EOCW {
+    ///1: Clear the regular channel conversion flag
+    Clear = 1,
+}
+impl From<EOCW> for bool {
+    #[inline(always)]
+    fn from(variant: EOCW) -> Self {
+        variant as u8 != 0
+    }
+}
+///Field `EOC` writer - EOC
+pub type EOC_W<'a, REG> = crate::BitWriter<'a, REG, EOCW>;
+impl<'a, REG> EOC_W<'a, REG>
+where
+    REG: crate::Writable + crate::RegisterSpec,
+{
+    ///Clear the regular channel conversion flag
+    #[inline(always)]
+    pub fn clear(self) -> &'a mut crate::W<REG> {
+        self.variant(EOCW::Clear)
+    }
+}
+/**EOS
+
+Value on reset: 0*/
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub enum EOSR {
+    ///0: Regular conversions sequence not complete (or the flag event was already acknowledged and cleared by software)
+    NotComplete = 0,
+    ///1: Regular conversions sequence complete
+    Complete = 1,
+}
+impl From<EOSR> for bool {
+    #[inline(always)]
+    fn from(variant: EOSR) -> Self {
+        variant as u8 != 0
+    }
+}
+///Field `EOS` reader - EOS
+pub type EOS_R = crate::BitReader<EOSR>;
+impl EOS_R {
+    ///Get enumerated values variant
+    #[inline(always)]
+    pub const fn variant(&self) -> EOSR {
+        match self.bits {
+            false => EOSR::NotComplete,
+            true => EOSR::Complete,
+        }
+    }
+    ///Regular conversions sequence not complete (or the flag event was already acknowledged and cleared by software)
+    #[inline(always)]
+    pub fn is_not_complete(&self) -> bool {
+        *self == EOSR::NotComplete
+    }
+    ///Regular conversions sequence complete
+    #[inline(always)]
+    pub fn is_complete(&self) -> bool {
+        *self == EOSR::Complete
+    }
+}
+/**EOS
+
+Value on reset: 0*/
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub enum EOSW {
+    ///1: Clear the regular conversion sequence flag
+    Clear = 1,
+}
+impl From<EOSW> for bool {
+    #[inline(always)]
+    fn from(variant: EOSW) -> Self {
+        variant as u8 != 0
+    }
+}
+///Field `EOS` writer - EOS
+pub type EOS_W<'a, REG> = crate::BitWriter<'a, REG, EOSW>;
+impl<'a, REG> EOS_W<'a, REG>
+where
+    REG: crate::Writable + crate::RegisterSpec,
+{
+    ///Clear the regular conversion sequence flag
+    #[inline(always)]
+    pub fn clear(self) -> &'a mut crate::W<REG> {
+        self.variant(EOSW::Clear)
+    }
+}
+/**OVR
+
+Value on reset: 0*/
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub enum OVRR {
+    ///0: No overrun occurred (or the flag event was already acknowledged and cleared by software)
+    NoOverrun = 0,
+    ///1: Overrun has occurred
+    Overrun = 1,
+}
+impl From<OVRR> for bool {
+    #[inline(always)]
+    fn from(variant: OVRR) -> Self {
+        variant as u8 != 0
+    }
+}
+///Field `OVR` reader - OVR
+pub type OVR_R = crate::BitReader<OVRR>;
+impl OVR_R {
+    ///Get enumerated values variant
+    #[inline(always)]
+    pub const fn variant(&self) -> OVRR {
+        match self.bits {
+            false => OVRR::NoOverrun,
+            true => OVRR::Overrun,
+        }
+    }
+    ///No overrun occurred (or the flag event was already acknowledged and cleared by software)
+    #[inline(always)]
+    pub fn is_no_overrun(&self) -> bool {
+        *self == OVRR::NoOverrun
+    }
+    ///Overrun has occurred
+    #[inline(always)]
+    pub fn is_overrun(&self) -> bool {
+        *self == OVRR::Overrun
+    }
+}
+/**OVR
+
+Value on reset: 0*/
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub enum OVRW {
+    ///1: Clear the overrun flag
+    Clear = 1,
+}
+impl From<OVRW> for bool {
+    #[inline(always)]
+    fn from(variant: OVRW) -> Self {
+        variant as u8 != 0
+    }
+}
+///Field `OVR` writer - OVR
+pub type OVR_W<'a, REG> = crate::BitWriter<'a, REG, OVRW>;
+impl<'a, REG> OVR_W<'a, REG>
+where
+    REG: crate::Writable + crate::RegisterSpec,
+{
+    ///Clear the overrun flag
+    #[inline(always)]
+    pub fn clear(self) -> &'a mut crate::W<REG> {
+        self.variant(OVRW::Clear)
+    }
+}
+/**JEOC
+
+Value on reset: 0*/
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub enum JEOCR {
+    ///0: Injected channel conversion not complete (or the flag event was already acknowledged and cleared by software)
+    NotComplete = 0,
+    ///1: Injected channel conversion complete
+    Complete = 1,
+}
+impl From<JEOCR> for bool {
+    #[inline(always)]
+    fn from(variant: JEOCR) -> Self {
+        variant as u8 != 0
+    }
+}
+///Field `JEOC` reader - JEOC
+pub type JEOC_R = crate::BitReader<JEOCR>;
+impl JEOC_R {
+    ///Get enumerated values variant
+    #[inline(always)]
+    pub const fn variant(&self) -> JEOCR {
+        match self.bits {
+            false => JEOCR::NotComplete,
+            true => JEOCR::Complete,
+        }
+    }
+    ///Injected channel conversion not complete (or the flag event was already acknowledged and cleared by software)
+    #[inline(always)]
+    pub fn is_not_complete(&self) -> bool {
+        *self == JEOCR::NotComplete
+    }
+    ///Injected channel conversion complete
+    #[inline(always)]
+    pub fn is_complete(&self) -> bool {
+        *self == JEOCR::Complete
+    }
+}
+/**JEOC
+
+Value on reset: 0*/
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub enum JEOCW {
+    ///1: Clear the injected channel conversion flag
+    Clear = 1,
+}
+impl From<JEOCW> for bool {
+    #[inline(always)]
+    fn from(variant: JEOCW) -> Self {
+        variant as u8 != 0
+    }
+}
+///Field `JEOC` writer - JEOC
+pub type JEOC_W<'a, REG> = crate::BitWriter<'a, REG, JEOCW>;
+impl<'a, REG> JEOC_W<'a, REG>
+where
+    REG: crate::Writable + crate::RegisterSpec,
+{
+    ///Clear the injected channel conversion flag
+    #[inline(always)]
+    pub fn clear(self) -> &'a mut crate::W<REG> {
+        self.variant(JEOCW::Clear)
+    }
+}
+/**JEOS
+
+Value on reset: 0*/
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub enum JEOSR {
+    ///0: Injected conversion sequence not complete (or the flag event was already acknowledged and cleared by software)
+    NotComplete = 0,
+    ///1: Injected conversions sequence complete
+    Complete = 1,
+}
+impl From<JEOSR> for bool {
+    #[inline(always)]
+    fn from(variant: JEOSR) -> Self {
+        variant as u8 != 0
+    }
+}
+///Field `JEOS` reader - JEOS
+pub type JEOS_R = crate::BitReader<JEOSR>;
+impl JEOS_R {
+    ///Get enumerated values variant
+    #[inline(always)]
+    pub const fn variant(&self) -> JEOSR {
+        match self.bits {
+            false => JEOSR::NotComplete,
+            true => JEOSR::Complete,
+        }
+    }
+    ///Injected conversion sequence not complete (or the flag event was already acknowledged and cleared by software)
+    #[inline(always)]
+    pub fn is_not_complete(&self) -> bool {
+        *self == JEOSR::NotComplete
+    }
+    ///Injected conversions sequence complete
+    #[inline(always)]
+    pub fn is_complete(&self) -> bool {
+        *self == JEOSR::Complete
+    }
+}
+/**JEOS
+
+Value on reset: 0*/
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub enum JEOSW {
+    ///1: Clear the injected conversion sequence flag
+    Clear = 1,
+}
+impl From<JEOSW> for bool {
+    #[inline(always)]
+    fn from(variant: JEOSW) -> Self {
+        variant as u8 != 0
+    }
+}
+///Field `JEOS` writer - JEOS
+pub type JEOS_W<'a, REG> = crate::BitWriter<'a, REG, JEOSW>;
+impl<'a, REG> JEOS_W<'a, REG>
+where
+    REG: crate::Writable + crate::RegisterSpec,
+{
+    ///Clear the injected conversion sequence flag
+    #[inline(always)]
+    pub fn clear(self) -> &'a mut crate::W<REG> {
+        self.variant(JEOSW::Clear)
+    }
+}
+/**Analog watchdog %s flag
+
+Value on reset: 0*/
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub enum AWD1R {
+    ///0: No analog watchdog x event occurred (or the flag event was already acknowledged and cleared by software)
+    NoEvent = 0,
+    ///1: Analog watchdog x event occurred
+    Event = 1,
+}
+impl From<AWD1R> for bool {
+    #[inline(always)]
+    fn from(variant: AWD1R) -> Self {
+        variant as u8 != 0
+    }
+}
+///Field `AWD(1-3)` reader - Analog watchdog %s flag
+pub type AWD_R = crate::BitReader<AWD1R>;
+impl AWD_R {
+    ///Get enumerated values variant
+    #[inline(always)]
+    pub const fn variant(&self) -> AWD1R {
+        match self.bits {
+            false => AWD1R::NoEvent,
+            true => AWD1R::Event,
+        }
+    }
+    ///No analog watchdog x event occurred (or the flag event was already acknowledged and cleared by software)
+    #[inline(always)]
+    pub fn is_no_event(&self) -> bool {
+        *self == AWD1R::NoEvent
+    }
+    ///Analog watchdog x event occurred
+    #[inline(always)]
+    pub fn is_event(&self) -> bool {
+        *self == AWD1R::Event
+    }
+}
+/**Analog watchdog %s flag
+
+Value on reset: 0*/
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub enum AWD1W {
+    ///1: Clear the analog watchdog x event flag
+    Clear = 1,
+}
+impl From<AWD1W> for bool {
+    #[inline(always)]
+    fn from(variant: AWD1W) -> Self {
+        variant as u8 != 0
+    }
+}
+///Field `AWD(1-3)` writer - Analog watchdog %s flag
+pub type AWD_W<'a, REG> = crate::BitWriter<'a, REG, AWD1W>;
+impl<'a, REG> AWD_W<'a, REG>
+where
+    REG: crate::Writable + crate::RegisterSpec,
+{
+    ///Clear the analog watchdog x event flag
+    #[inline(always)]
+    pub fn clear(self) -> &'a mut crate::W<REG> {
+        self.variant(AWD1W::Clear)
+    }
+}
+/**LDORDY
+
+Value on reset: 0*/
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub enum LDORDYR {
+    ///0: ADC voltage regulator disabled
+    Disabled = 0,
+    ///1: ADC voltage regulator enabled
+    Enabled = 1,
+}
+impl From<LDORDYR> for bool {
+    #[inline(always)]
+    fn from(variant: LDORDYR) -> Self {
+        variant as u8 != 0
+    }
+}
+///Field `LDORDY` reader - LDORDY
+pub type LDORDY_R = crate::BitReader<LDORDYR>;
+impl LDORDY_R {
+    ///Get enumerated values variant
+    #[inline(always)]
+    pub const fn variant(&self) -> LDORDYR {
+        match self.bits {
+            false => LDORDYR::Disabled,
+            true => LDORDYR::Enabled,
+        }
+    }
+    ///ADC voltage regulator disabled
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == LDORDYR::Disabled
+    }
+    ///ADC voltage regulator enabled
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == LDORDYR::Enabled
+    }
+}
+impl R {
+    ///Bit 0 - ADRDY
+    #[inline(always)]
+    pub fn adrdy(&self) -> ADRDY_R {
+        ADRDY_R::new((self.bits & 1) != 0)
+    }
+    ///Bit 1 - EOSMP
+    #[inline(always)]
+    pub fn eosmp(&self) -> EOSMP_R {
+        EOSMP_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    ///Bit 2 - EOC
+    #[inline(always)]
+    pub fn eoc(&self) -> EOC_R {
+        EOC_R::new(((self.bits >> 2) & 1) != 0)
+    }
+    ///Bit 3 - EOS
+    #[inline(always)]
+    pub fn eos(&self) -> EOS_R {
+        EOS_R::new(((self.bits >> 3) & 1) != 0)
+    }
+    ///Bit 4 - OVR
+    #[inline(always)]
+    pub fn ovr(&self) -> OVR_R {
+        OVR_R::new(((self.bits >> 4) & 1) != 0)
+    }
+    ///Bit 5 - JEOC
+    #[inline(always)]
+    pub fn jeoc(&self) -> JEOC_R {
+        JEOC_R::new(((self.bits >> 5) & 1) != 0)
+    }
+    ///Bit 6 - JEOS
+    #[inline(always)]
+    pub fn jeos(&self) -> JEOS_R {
+        JEOS_R::new(((self.bits >> 6) & 1) != 0)
+    }
+    ///Analog watchdog (1-3) flag
+    ///
+    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `AWD1` field.</div>
+    #[inline(always)]
+    pub fn awd(&self, n: u8) -> AWD_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        AWD_R::new(((self.bits >> (n + 7)) & 1) != 0)
+    }
+    ///Iterator for array of:
+    ///Analog watchdog (1-3) flag
+    #[inline(always)]
+    pub fn awd_iter(&self) -> impl Iterator<Item = AWD_R> + '_ {
+        (0..3).map(move |n| AWD_R::new(((self.bits >> (n + 7)) & 1) != 0))
+    }
+    ///Bit 7 - Analog watchdog 1 flag
+    #[inline(always)]
+    pub fn awd1(&self) -> AWD_R {
+        AWD_R::new(((self.bits >> 7) & 1) != 0)
+    }
+    ///Bit 8 - Analog watchdog 2 flag
+    #[inline(always)]
+    pub fn awd2(&self) -> AWD_R {
+        AWD_R::new(((self.bits >> 8) & 1) != 0)
+    }
+    ///Bit 9 - Analog watchdog 3 flag
+    #[inline(always)]
+    pub fn awd3(&self) -> AWD_R {
+        AWD_R::new(((self.bits >> 9) & 1) != 0)
+    }
+    ///Bit 12 - LDORDY
+    #[inline(always)]
+    pub fn ldordy(&self) -> LDORDY_R {
+        LDORDY_R::new(((self.bits >> 12) & 1) != 0)
+    }
+}
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("ISR")
+            .field("ldordy", &self.ldordy())
+            .field("awd1", &self.awd1())
+            .field("awd2", &self.awd2())
+            .field("awd3", &self.awd3())
+            .field("jeos", &self.jeos())
+            .field("jeoc", &self.jeoc())
+            .field("ovr", &self.ovr())
+            .field("eos", &self.eos())
+            .field("eoc", &self.eoc())
+            .field("eosmp", &self.eosmp())
+            .field("adrdy", &self.adrdy())
+            .finish()
+    }
+}
+impl W {
+    ///Bit 0 - ADRDY
+    #[inline(always)]
+    pub fn adrdy(&mut self) -> ADRDY_W<ISRrs> {
+        ADRDY_W::new(self, 0)
+    }
+    ///Bit 1 - EOSMP
+    #[inline(always)]
+    pub fn eosmp(&mut self) -> EOSMP_W<ISRrs> {
+        EOSMP_W::new(self, 1)
+    }
+    ///Bit 2 - EOC
+    #[inline(always)]
+    pub fn eoc(&mut self) -> EOC_W<ISRrs> {
+        EOC_W::new(self, 2)
+    }
+    ///Bit 3 - EOS
+    #[inline(always)]
+    pub fn eos(&mut self) -> EOS_W<ISRrs> {
+        EOS_W::new(self, 3)
+    }
+    ///Bit 4 - OVR
+    #[inline(always)]
+    pub fn ovr(&mut self) -> OVR_W<ISRrs> {
+        OVR_W::new(self, 4)
+    }
+    ///Bit 5 - JEOC
+    #[inline(always)]
+    pub fn jeoc(&mut self) -> JEOC_W<ISRrs> {
+        JEOC_W::new(self, 5)
+    }
+    ///Bit 6 - JEOS
+    #[inline(always)]
+    pub fn jeos(&mut self) -> JEOS_W<ISRrs> {
+        JEOS_W::new(self, 6)
+    }
+    ///Analog watchdog (1-3) flag
+    ///
+    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `AWD1` field.</div>
+    #[inline(always)]
+    pub fn awd(&mut self, n: u8) -> AWD_W<ISRrs> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        AWD_W::new(self, n + 7)
+    }
+    ///Bit 7 - Analog watchdog 1 flag
+    #[inline(always)]
+    pub fn awd1(&mut self) -> AWD_W<ISRrs> {
+        AWD_W::new(self, 7)
+    }
+    ///Bit 8 - Analog watchdog 2 flag
+    #[inline(always)]
+    pub fn awd2(&mut self) -> AWD_W<ISRrs> {
+        AWD_W::new(self, 8)
+    }
+    ///Bit 9 - Analog watchdog 3 flag
+    #[inline(always)]
+    pub fn awd3(&mut self) -> AWD_W<ISRrs> {
+        AWD_W::new(self, 9)
+    }
+}
+/**ADC interrupt and status register
+
+You can [`read`](crate::Reg::read) this register and get [`isr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`isr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
+
+See register [structure](https://stm32-rs.github.io/stm32-rs/STM32U535.html#ADC1:ISR)*/
+pub struct ISRrs;
+impl crate::RegisterSpec for ISRrs {
+    type Ux = u32;
+}
+///`read()` method returns [`isr::R`](R) reader structure
+impl crate::Readable for ISRrs {}
+///`write(|w| ..)` method takes [`isr::W`](W) writer structure
+impl crate::Writable for ISRrs {
+    type Safety = crate::Unsafe;
+}
+///`reset()` method sets ISR to value 0
+impl crate::Resettable for ISRrs {}

### external/vendor/stm32u5/src/stm32u535/adc1/jdr.rs
@@ -0,0 +1,29 @@
+///Register `JDR%s` reader
+pub type R = crate::R<JDRrs>;
+///Field `JDATA` reader - JDATA
+pub type JDATA_R = crate::FieldReader<u32>;
+impl R {
+    ///Bits 0:31 - JDATA
+    #[inline(always)]
+    pub fn jdata(&self) -> JDATA_R {
+        JDATA_R::new(self.bits)
+    }
+}
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("JDR").field("jdata", &self.jdata()).finish()
+    }
+}
+/**ADC injected data register
+
+You can [`read`](crate::Reg::read) this register and get [`jdr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
+
+See register [structure](https://stm32-rs.github.io/stm32-rs/STM32U535.html#ADC1:JDR[1])*/
+pub struct JDRrs;
+impl crate::RegisterSpec for JDRrs {
+    type Ux = u32;
+}
+///`read()` method returns [`jdr::R`](R) reader structure
+impl crate::Readable for JDRrs {}
+///`reset()` method sets JDR%s to value 0
+impl crate::Resettable for JDRrs {}

### external/vendor/stm32u5/src/stm32u535/adc1/jsqr.rs
@@ -0,0 +1,526 @@
+///Register `JSQR` reader
+pub type R = crate::R<JSQRrs>;
+///Register `JSQR` writer
+pub type W = crate::W<JSQRrs>;
+///Field `JL` reader - JL
+pub type JL_R = crate::FieldReader;
+///Field `JL` writer - JL
+pub type JL_W<'a, REG> = crate::FieldWriter<'a, REG, 2, u8, crate::Safe>;
+/**JEXTSEL
+
+Value on reset: 0*/
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+#[repr(u8)]
+pub enum JEXTSEL {
+    ///0: tim1_trgo
+    Tim1Trgo = 0,
+    ///1: tim1_oc4
+    Tim1Oc4 = 1,
+    ///2: tim2_trgo
+    Tim2Trgo = 2,
+    ///3: tim2_oc1
+    Tim2Oc1 = 3,
+    ///4: tim3_oc4
+    Tim3Oc4 = 4,
+    ///5: tim4_trgo
+    Tim4Trgo = 5,
+    ///6: exti15
+    Exti15 = 6,
+    ///7: tim8_oc4
+    Tim8Oc4 = 7,
+    ///8: tim1_trgo2
+    Tim1Trgo2 = 8,
+    ///9: tim8_trgo
+    Tim8Trgo = 9,
+    ///10: tim8_trgo2
+    Tim8Trgo2 = 10,
+    ///11: tim3_oc3
+    Tim3Oc3 = 11,
+    ///12: tim3_trgo
+    Tim3Trgo = 12,
+    ///13: tim3_oc1
+    Tim3Oc1 = 13,
+    ///14: tim6_trgo
+    Tim6Trgo = 14,
+    ///15: tim15_trgo
+    Tim15Trgo = 15,
+    ///16: lptim1_ch2
+    Lptim1Ch2 = 16,
+    ///17: lptim2_ch2
+    Lptim2Ch2 = 17,
+    ///18: lptim3_ch1
+    Lptim3Ch1 = 18,
+    ///19: lptim4_out1
+    Lptim4Out1 = 19,
+}
+impl From<JEXTSEL> for u8 {
+    #[inline(always)]
+    fn from(variant: JEXTSEL) -> Self {
+        variant as _
+    }
+}
+impl crate::FieldSpec for JEXTSEL {
+    type Ux = u8;
+}
+impl crate::IsEnum for JEXTSEL {}
+///Field `JEXTSEL` reader - JEXTSEL
+pub type JEXTSEL_R = crate::FieldReader<JEXTSEL>;
+impl JEXTSEL_R {
+    ///Get enumerated values variant
+    #[inline(always)]
+    pub const fn variant(&self) -> Option<JEXTSEL> {
+        match self.bits {
+            0 => Some(JEXTSEL::Tim1Trgo),
+            1 => Some(JEXTSEL::Tim1Oc4),
+            2 => Some(JEXTSEL::Tim2Trgo),
+            3 => Some(JEXTSEL::Tim2Oc1),
+            4 => Some(JEXTSEL::Tim3Oc4),
+            5 => Some(JEXTSEL::Tim4Trgo),
+            6 => Some(JEXTSEL::Exti15),
+            7 => Some(JEXTSEL::Tim8Oc4),
+            8 => Some(JEXTSEL::Tim1Trgo2),
+            9 => Some(JEXTSEL::Tim8Trgo),
+            10 => Some(JEXTSEL::Tim8Trgo2),
+            11 => Some(JEXTSEL::Tim3Oc3),
+            12 => Some(JEXTSEL::Tim3Trgo),
+            13 => Some(JEXTSEL::Tim3Oc1),
+            14 => Some(JEXTSEL::Tim6Trgo),
+            15 => Some(JEXTSEL::Tim15Trgo),
+            16 => Some(JEXTSEL::Lptim1Ch2),
+            17 => Some(JEXTSEL::Lptim2Ch2),
+            18 => Some(JEXTSEL::Lptim3Ch1),
+            19 => Some(JEXTSEL::Lptim4Out1),
+            _ => None,
+        }
+    }
+    ///tim1_trgo
+    #[inline(always)]
+    pub fn is_tim1_trgo(&self) -> bool {
+        *self == JEXTSEL::Tim1Trgo
+    }
+    ///tim1_oc4
+    #[inline(always)]
+    pub fn is_tim1_oc4(&self) -> bool {
+        *self == JEXTSEL::Tim1Oc4
+    }
+    ///tim2_trgo
+    #[inline(always)]
+    pub fn is_tim2_trgo(&self) -> bool {
+        *self == JEXTSEL::Tim2Trgo
+    }
+    ///tim2_oc1
+    #[inline(always)]
+    pub fn is_tim2_oc1(&self) -> bool {
+        *self == JEXTSEL::Tim2Oc1
+    }
+    ///tim3_oc4
+    #[inline(always)]
+    pub fn is_tim3_oc4(&self) -> bool {
+        *self == JEXTSEL::Tim3Oc4
+    }
+    ///tim4_trgo
+    #[inline(always)]
+    pub fn is_tim4_trgo(&self) -> bool {
+        *self == JEXTSEL::Tim4Trgo
+    }
+    ///exti15
+    #[inline(always)]
+    pub fn is_exti15(&self) -> bool {
+        *self == JEXTSEL::Exti15
+    }
+    ///tim8_oc4
+    #[inline(always)]
+    pub fn is_tim8_oc4(&self) -> bool {
+        *self == JEXTSEL::Tim8Oc4
+    }
+    ///tim1_trgo2
+    #[inline(always)]
+    pub fn is_tim1_trgo2(&self) -> bool {
+        *self == JEXTSEL::Tim1Trgo2
+    }
+    ///tim8_trgo
+    #[inline(always)]
+    pub fn is_tim8_trgo(&self) -> bool {
+        *self == JEXTSEL::Tim8Trgo
+    }
+    ///tim8_trgo2
+    #[inline(always)]
+    pub fn is_tim8_trgo2(&self) -> bool {
+        *self == JEXTSEL::Tim8Trgo2
+    }
+    ///tim3_oc3
+    #[inline(always)]
+    pub fn is_tim3_oc3(&self) -> bool {
+        *self == JEXTSEL::Tim3Oc3
+    }
+    ///tim3_trgo
+    #[inline(always)]
+    pub fn is_tim3_trgo(&self) -> bool {
+        *self == JEXTSEL::Tim3Trgo
+    }
+    ///tim3_oc1
+    #[inline(always)]
+    pub fn is_tim3_oc1(&self) -> bool {
+        *self == JEXTSEL::Tim3Oc1
+    }
+    ///tim6_trgo
+    #[inline(always)]
+    pub fn is_tim6_trgo(&self) -> bool {
+        *self == JEXTSEL::Tim6Trgo
+    }
+    ///tim15_trgo
+    #[inline(always)]
+    pub fn is_tim15_trgo(&self) -> bool {
+        *self == JEXTSEL::Tim15Trgo
+    }
+    ///lptim1_ch2
+    #[inline(always)]
+    pub fn is_lptim1_ch2(&self) -> bool {
+        *self == JEXTSEL::Lptim1Ch2
+    }
+    ///lptim2_ch2
+    #[inline(always)]
+    pub fn is_lptim2_ch2(&self) -> bool {
+        *self == JEXTSEL::Lptim2Ch2
+    }
+    ///lptim3_ch1
+    #[inline(always)]
+    pub fn is_lptim3_ch1(&self) -> bool {
+        *self == JEXTSEL::Lptim3Ch1
+    }
+    ///lptim4_out1
+    #[inline(always)]
+    pub fn is_lptim4_out1(&self) -> bool {
+        *self == JEXTSEL::Lptim4Out1
+    }
+}
+///Field `JEXTSEL` writer - JEXTSEL
+pub type JEXTSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 5, JEXTSEL>;
+impl<'a, REG> JEXTSEL_W<'a, REG>
+where
+    REG: crate::Writable + crate::RegisterSpec,
+    REG::Ux: From<u8>,
+{
+    ///tim1_trgo
+    #[inline(always)]
+    pub fn tim1_trgo(self) -> &'a mut crate::W<REG> {
+        self.variant(JEXTSEL::Tim1Trgo)
+    }
+    ///tim1_oc4
+    #[inline(always)]
+    pub fn tim1_oc4(self) -> &'a mut crate::W<REG> {
+        self.variant(JEXTSEL::Tim1Oc4)
+    }
+    ///tim2_trgo
+    #[inline(always)]
+    pub fn tim2_trgo(self) -> &'a mut crate::W<REG> {
+        self.variant(JEXTSEL::Tim2Trgo)
+    }
+    ///tim2_oc1
+    #[inline(always)]
+    pub fn tim2_oc1(self) -> &'a mut crate::W<REG> {
+        self.variant(JEXTSEL::Tim2Oc1)
+    }
+    ///tim3_oc4
+    #[inline(always)]
+    pub fn tim3_oc4(self) -> &'a mut crate::W<REG> {
+        self.variant(JEXTSEL::Tim3Oc4)
+    }
+    ///tim4_trgo
+    #[inline(always)]
+    pub fn tim4_trgo(self) -> &'a mut crate::W<REG> {
+        self.variant(JEXTSEL::Tim4Trgo)
+    }
+    ///exti15
+    #[inline(always)]
+    pub fn exti15(self) -> &'a mut crate::W<REG> {
+        self.variant(JEXTSEL::Exti15)
+    }
+    ///tim8_oc4
+    #[inline(always)]
+    pub fn tim8_oc4(self) -> &'a mut crate::W<REG> {
+        self.variant(JEXTSEL::Tim8Oc4)
+    }
+    ///tim1_trgo2
+    #[inline(always)]
+    pub fn tim1_trgo2(self) -> &'a mut crate::W<REG> {
+        self.variant(JEXTSEL::Tim1Trgo2)
+    }
+    ///tim8_trgo
+    #[inline(always)]
+    pub fn tim8_trgo(self) -> &'a mut crate::W<REG> {
+        self.variant(JEXTSEL::Tim8Trgo)
+    }
+    ///tim8_trgo2
+    #[inline(always)]
+    pub fn tim8_trgo2(self) -> &'a mut crate::W<REG> {
+        self.variant(JEXTSEL::Tim8Trgo2)
+    }
+    ///tim3_oc3
+    #[inline(always)]
+    pub fn tim3_oc3(self) -> &'a mut crate::W<REG> {
+        self.variant(JEXTSEL::Tim3Oc3)
+    }
+    ///tim3_trgo
+    #[inline(always)]
+    pub fn tim3_trgo(self) -> &'a mut crate::W<REG> {
+        self.variant(JEXTSEL::Tim3Trgo)
+    }
+    ///tim3_oc1
+    #[inline(always)]
+    pub fn tim3_oc1(self) -> &'a mut crate::W<REG> {
+        self.variant(JEXTSEL::Tim3Oc1)
+    }
+    ///tim6_trgo
+    #[inline(always)]
+    pub fn tim6_trgo(self) -> &'a mut crate::W<REG> {
+        self.variant(JEXTSEL::Tim6Trgo)
+    }
+    ///tim15_trgo
+    #[inline(always)]
+    pub fn tim15_trgo(self) -> &'a mut crate::W<REG> {
+        self.variant(JEXTSEL::Tim15Trgo)
+    }
+    ///lptim1_ch2
+    #[inline(always)]
+    pub fn lptim1_ch2(self) -> &'a mut crate::W<REG> {
+        self.variant(JEXTSEL::Lptim1Ch2)
+    }
+    ///lptim2_ch2
+    #[inline(always)]
+    pub fn lptim2_ch2(self) -> &'a mut crate::W<REG> {
+        self.variant(JEXTSEL::Lptim2Ch2)
+    }
+    ///lptim3_ch1
+    #[inline(always)]
+    pub fn lptim3_ch1(self) -> &'a mut crate::W<REG> {
+        self.variant(JEXTSEL::Lptim3Ch1)
+    }
+    ///lptim4_out1
+    #[inline(always)]
+    pub fn lptim4_out1(self) -> &'a mut crate::W<REG> {
+        self.variant(JEXTSEL::Lptim4Out1)
+    }
+}
+/**JEXTEN
+
+Value on reset: 0*/
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+#[repr(u8)]
+pub enum JEXTEN {
+    ///0: Hardware trigger detection disabled (conversions can be launched by software)
+    Disabled = 0,
+    ///1: Hardware trigger detection on the rising edge
+    RisingEdge = 1,
+    ///2: Hardware trigger detection on the falling edge
+    FallingEdge = 2,
+    ///3: Hardware trigger detection on both the rising and falling edges
+    BothEdges = 3,
+}
+impl From<JEXTEN> for u8 {
+    #[inline(always)]
+    fn from(variant: JEXTEN) -> Self {
+        variant as _
+    }
+}
+impl crate::FieldSpec for JEXTEN {
+    type Ux = u8;
+}
+impl crate::IsEnum for JEXTEN {}
+///Field `JEXTEN` reader - JEXTEN
+pub type JEXTEN_R = crate::FieldReader<JEXTEN>;
+impl JEXTEN_R {
+    ///Get enumerated values variant
+    #[inline(always)]
+    pub const fn variant(&self) -> JEXTEN {
+        match self.bits {
+            0 => JEXTEN::Disabled,
+            1 => JEXTEN::RisingEdge,
+            2 => JEXTEN::FallingEdge,
+            3 => JEXTEN::BothEdges,
+            _ => unreachable!(),
+        }
+    }
+    ///Hardware trigger detection disabled (conversions can be launched by software)
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == JEXTEN::Disabled
+    }
+    ///Hardware trigger detection on the rising edge
+    #[inline(always)]
+    pub fn is_rising_edge(&self) -> bool {
+        *self == JEXTEN::RisingEdge
+    }
+    ///Hardware trigger detection on the falling edge
+    #[inline(always)]
+    pub fn is_falling_edge(&self) -> bool {
+        *self == JEXTEN::FallingEdge
+    }
+    ///Hardware trigger detection on both the rising and falling edges
+    #[inline(always)]
+    pub fn is_both_edges(&self) -> bool {
+        *self == JEXTEN::BothEdges
+    }
+}
+///Field `JEXTEN` writer - JEXTEN
+pub type JEXTEN_W<'a, REG> = crate::FieldWriter<'a, REG, 2, JEXTEN, crate::Safe>;
+impl<'a, REG> JEXTEN_W<'a, REG>
+where
+    REG: crate::Writable + crate::RegisterSpec,
+    REG::Ux: From<u8>,
+{
+    ///Hardware trigger detection disabled (conversions can be launched by software)
+    #[inline(always)]
+    pub fn disabled(self) -> &'a mut crate::W<REG> {
+        self.variant(JEXTEN::Disabled)
+    }
+    ///Hardware trigger detection on the rising edge
+    #[inline(always)]
+    pub fn rising_edge(self) -> &'a mut crate::W<REG> {
+        self.variant(JEXTEN::RisingEdge)
+    }
+    ///Hardware trigger detection on the falling edge
+    #[inline(always)]
+    pub fn falling_edge(self) -> &'a mut crate::W<REG> {
+        self.variant(JEXTEN::FallingEdge)
+    }
+    ///Hardware trigger detection on both the rising and falling edges
+    #[inline(always)]
+    pub fn both_edges(self) -> &'a mut crate::W<REG> {
+        self.variant(JEXTEN::BothEdges)
+    }
+}
+///Field `JSQ(1-4)` reader - %s conversion in injected sequence
+pub type JSQ_R = crate::FieldReader;
+///Field `JSQ(1-4)` writer - %s conversion in injected sequence
+pub type JSQ_W<'a, REG> = crate::FieldWriter<'a, REG, 5, u8, crate::Safe>;
+impl R {
+    ///Bits 0:1 - JL
+    #[inline(always)]
+    pub fn jl(&self) -> JL_R {
+        JL_R::new((self.bits & 3) as u8)
+    }
+    ///Bits 2:6 - JEXTSEL
+    #[inline(always)]
+    pub fn jextsel(&self) -> JEXTSEL_R {
+        JEXTSEL_R::new(((self.bits >> 2) & 0x1f) as u8)
+    }
+    ///Bits 7:8 - JEXTEN
+    #[inline(always)]
+    pub fn jexten(&self) -> JEXTEN_R {
+        JEXTEN_R::new(((self.bits >> 7) & 3) as u8)
+    }
+    ///(1-4) conversion in injected sequence
+    ///
+    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `JSQ1` field.</div>
+    #[inline(always)]
+    pub fn jsq(&self, n: u8) -> JSQ_R {
+        #[allow(clippy::no_effect)]
+        [(); 4][n as usize];
+        JSQ_R::new(((self.bits >> (n * 6 + 9)) & 0x1f) as u8)
+    }
+    ///Iterator for array of:
+    ///(1-4) conversion in injected sequence
+    #[inline(always)]
+    pub fn jsq_iter(&self) -> impl Iterator<Item = JSQ_R> + '_ {
+        (0..4).map(move |n| JSQ_R::new(((self.bits >> (n * 6 + 9)) & 0x1f) as u8))
+    }
+    ///Bits 9:13 - 1 conversion in injected sequence
+    #[inline(always)]
+    pub fn jsq1(&self) -> JSQ_R {
+        JSQ_R::new(((self.bits >> 9) & 0x1f) as u8)
+    }
+    ///Bits 15:19 - 2 conversion in injected sequence
+    #[inline(always)]
+    pub fn jsq2(&self) -> JSQ_R {
+        JSQ_R::new(((self.bits >> 15) & 0x1f) as u8)
+    }
+    ///Bits 21:25 - 3 conversion in injected sequence
+    #[inline(always)]
+    pub fn jsq3(&self) -> JSQ_R {
+        JSQ_R::new(((self.bits >> 21) & 0x1f) as u8)
+    }
+    ///Bits 27:31 - 4 conversion in injected sequence
+    #[inline(always)]
+    pub fn jsq4(&self) -> JSQ_R {
+        JSQ_R::new(((self.bits >> 27) & 0x1f) as u8)
+    }
+}
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("JSQR")
+            .field("jsq1", &self.jsq1())
+            .field("jsq2", &self.jsq2())
+            .field("jsq3", &self.jsq3())
+            .field("jsq4", &self.jsq4())
+            .field("jexten", &self.jexten())
+            .field("jextsel", &self.jextsel())
+            .field("jl", &self.jl())
+            .finish()
+    }
+}
+impl W {
+    ///Bits 0:1 - JL
+    #[inline(always)]
+    pub fn jl(&mut self) -> JL_W<JSQRrs> {
+        JL_W::new(self, 0)
+    }
+    ///Bits 2:6 - JEXTSEL
+    #[inline(always)]
+    pub fn jextsel(&mut self) -> JEXTSEL_W<JSQRrs> {
+        JEXTSEL_W::new(self, 2)
+    }
+    ///Bits 7:8 - JEXTEN
+    #[inline(always)]
+    pub fn jexten(&mut self) -> JEXTEN_W<JSQRrs> {
+        JEXTEN_W::new(self, 7)
+    }
+    ///(1-4) conversion in injected sequence
+    ///
+    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `JSQ1` field.</div>
+    #[inline(always)]
+    pub fn jsq(&mut self, n: u8) -> JSQ_W<JSQRrs> {
+        #[allow(clippy::no_effect)]
+        [(); 4][n as usize];
+        JSQ_W::new(self, n * 6 + 9)
+    }
+    ///Bits 9:13 - 1 conversion in injected sequence
+    #[inline(always)]
+    pub fn jsq1(&mut self) -> JSQ_W<JSQRrs> {
+        JSQ_W::new(self, 9)
+    }
+    ///Bits 15:19 - 2 conversion in injected sequence
+    #[inline(always)]
+    pub fn jsq2(&mut self) -> JSQ_W<JSQRrs> {
+        JSQ_W::new(self, 15)
+    }
+    ///Bits 21:25 - 3 conversion in injected sequence
+    #[inline(always)]
+    pub fn jsq3(&mut self) -> JSQ_W<JSQRrs> {
+        JSQ_W::new(self, 21)
+    }
+    ///Bits 27:31 - 4 conversion in injected sequence
+    #[inline(always)]
+    pub fn jsq4(&mut self) -> JSQ_W<JSQRrs> {
+        JSQ_W::new(self, 27)
+    }
+}
+/**ADC injected sequence register
+
+You can [`read`](crate::Reg::read) this register and get [`jsqr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`jsqr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
+
+See register [structure](https://stm32-rs.github.io/stm32-rs/STM32U535.html#ADC1:JSQR)*/
+pub struct JSQRrs;
+impl crate::RegisterSpec for JSQRrs {
+    type Ux = u32;
+}
+///`read()` method returns [`jsqr::R`](R) reader structure
+impl crate::Readable for JSQRrs {}
+///`write(|w| ..)` method takes [`jsqr::W`](W) writer structure
+impl crate::Writable for JSQRrs {
+    type Safety = crate::Unsafe;
+}
+///`reset()` method sets JSQR to value 0
+impl crate::Resettable for JSQRrs {}

### external/vendor/stm32u5/src/stm32u535/adc1/ltr1.rs
@@ -0,0 +1,44 @@
+///Register `LTR1` reader
+pub type R = crate::R<LTR1rs>;
+///Register `LTR1` writer
+pub type W = crate::W<LTR1rs>;
+///Field `LTR1` reader - LTR1
+pub type LTR1_R = crate::FieldReader<u32>;
+///Field `LTR1` writer - LTR1
+pub type LTR1_W<'a, REG> = crate::FieldWriter<'a, REG, 25, u32, crate::Safe>;
+impl R {
+    ///Bits 0:24 - LTR1
+    #[inline(always)]
+    pub fn ltr1(&self) -> LTR1_R {
+        LTR1_R::new(self.bits & 0x01ff_ffff)
+    }
+}
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("LTR1").field("ltr1", &self.ltr1()).finish()
+    }
+}
+impl W {
+    ///Bits 0:24 - LTR1
+    #[inline(always)]
+    pub fn ltr1(&mut self) -> LTR1_W<LTR1rs> {
+        LTR1_W::new(self, 0)
+    }
+}
+/**ADC watchdog threshold register 1
+
+You can [`read`](crate::Reg::read) this register and get [`ltr1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ltr1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
+
+See register [structure](https://stm32-rs.github.io/stm32-rs/STM32U535.html#ADC1:LTR1)*/
+pub struct LTR1rs;
+impl crate::RegisterSpec for LTR1rs {
+    type Ux = u32;
+}
+///`read()` method returns [`ltr1::R`](R) reader structure
+impl crate::Readable for LTR1rs {}
+///`write(|w| ..)` method takes [`ltr1::W`](W) writer structure
+impl crate::Writable for LTR1rs {
+    type Safety = crate::Unsafe;
+}
+///`reset()` method sets LTR1 to value 0
+impl crate::Resettable for LTR1rs {}

### external/vendor/stm32u5/src/stm32u535/adc1/ltr2.rs
@@ -0,0 +1,44 @@
+///Register `LTR2` reader
+pub type R = crate::R<LTR2rs>;
+///Register `LTR2` writer
+pub type W = crate::W<LTR2rs>;
+///Field `LTR2` reader - LTR2
+pub type LTR2_R = crate::FieldReader<u32>;
+///Field `LTR2` writer - LTR2
+pub type LTR2_W<'a, REG> = crate::FieldWriter<'a, REG, 25, u32, crate::Safe>;
+impl R {
+    ///Bits 0:24 - LTR2
+    #[inline(always)]
+    pub fn ltr2(&self) -> LTR2_R {
+        LTR2_R::new(self.bits & 0x01ff_ffff)
+    }
+}
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("LTR2").field("ltr2", &self.ltr2()).finish()
+    }
+}
+impl W {
+    ///Bits 0:24 - LTR2
+    #[inline(always)]
+    pub fn ltr2(&mut self) -> LTR2_W<LTR2rs> {
+        LTR2_W::new(self, 0)
+    }
+}
+/**ADC watchdog lower threshold register 2
+
+You can [`read`](crate::Reg::read) this register and get [`ltr2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ltr2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
+
+See register [structure](https://stm32-rs.github.io/stm32-rs/STM32U535.html#ADC1:LTR2)*/
+pub struct LTR2rs;
+impl crate::RegisterSpec for LTR2rs {
+    type Ux = u32;
+}
+///`read()` method returns [`ltr2::R`](R) reader structure
+impl crate::Readable for LTR2rs {}
+///`write(|w| ..)` method takes [`ltr2::W`](W) writer structure
+impl crate::Writable for LTR2rs {
+    type Safety = crate::Unsafe;
+}
+///`reset()` method sets LTR2 to value 0
+impl crate::Resettable for LTR2rs {}

### external/vendor/stm32u5/src/stm32u535/adc1/ltr3.rs
@@ -0,0 +1,44 @@
+///Register `LTR3` reader
+pub type R = crate::R<LTR3rs>;
+///Register `LTR3` writer
+pub type W = crate::W<LTR3rs>;
+///Field `LTR3` reader - LTR3
+pub type LTR3_R = crate::FieldReader<u32>;
+///Field `LTR3` writer - LTR3
+pub type LTR3_W<'a, REG> = crate::FieldWriter<'a, REG, 25, u32, crate::Safe>;
+impl R {
+    ///Bits 0:24 - LTR3
+    #[inline(always)]
+    pub fn ltr3(&self) -> LTR3_R {
+        LTR3_R::new(self.bits & 0x01ff_ffff)
+    }
+}
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("LTR3").field("ltr3", &self.ltr3()).finish()
+    }
+}
+impl W {
+    ///Bits 0:24 - LTR3
+    #[inline(always)]
+    pub fn ltr3(&mut self) -> LTR3_W<LTR3rs> {
+        LTR3_W::new(self, 0)
+    }
+}
+/**ADC watchdog lower threshold register 3
+
+You can [`read`](crate::Reg::read) this register and get [`ltr3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ltr3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
+
+See register [structure](https://stm32-rs.github.io/stm32-rs/STM32U535.html#ADC1:LTR3)*/
+pub struct LTR3rs;
+impl crate::RegisterSpec for LTR3rs {
+    type Ux = u32;
+}
+///`read()` method returns [`ltr3::R`](R) reader structure
+impl crate::Readable for LTR3rs {}
+///`write(|w| ..)` method takes [`ltr3::W`](W) writer structure
+impl crate::Writable for LTR3rs {
+    type Safety = crate::Unsafe;
+}
+///`reset()` method sets LTR3 to value 0
+impl crate::Resettable for LTR3rs {}

### external/vendor/stm32u5/src/stm32u535/adc1/ofr.rs
@@ -0,0 +1,262 @@
+///Register `OFR%s` reader
+pub type R = crate::R<OFRrs>;
+///Register `OFR%s` writer
+pub type W = crate::W<OFRrs>;
+///Field `OFFSET` reader - OFFSET
+pub type OFFSET_R = crate::FieldReader<u32>;
+///Field `OFFSET` writer - OFFSET
+pub type OFFSET_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32, crate::Safe>;
+/**POSOFF
+
+Value on reset: 0*/
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub enum POSOFF {
+    ///0: Negative offset
+    Negative = 0,
+    ///1: Positive offset
+    Positive = 1,
+}
+impl From<POSOFF> for bool {
+    #[inline(always)]
+    fn from(variant: POSOFF) -> Self {
+        variant as u8 != 0
+    }
+}
+///Field `POSOFF` reader - POSOFF
+pub type POSOFF_R = crate::BitReader<POSOFF>;
+impl POSOFF_R {
+    ///Get enumerated values variant
+    #[inline(always)]
+    pub const fn variant(&self) -> POSOFF {
+        match self.bits {
+            false => POSOFF::Negative,
+            true => POSOFF::Positive,
+        }
+    }
+    ///Negative offset
+    #[inline(always)]
+    pub fn is_negative(&self) -> bool {
+        *self == POSOFF::Negative
+    }
+    ///Positive offset
+    #[inline(always)]
+    pub fn is_positive(&self) -> bool {
+        *self == POSOFF::Positive
+    }
+}
+///Field `POSOFF` writer - POSOFF
+pub type POSOFF_W<'a, REG> = crate::BitWriter<'a, REG, POSOFF>;
+impl<'a, REG> POSOFF_W<'a, REG>
+where
+    REG: crate::Writable + crate::RegisterSpec,
+{
+    ///Negative offset
+    #[inline(always)]
+    pub fn negative(self) -> &'a mut crate::W<REG> {
+        self.variant(POSOFF::Negative)
+    }
+    ///Positive offset
+    #[inline(always)]
+    pub fn positive(self) -> &'a mut crate::W<REG> {
+        self.variant(POSOFF::Positive)
+    }
+}
+/**USAT
+
+Value on reset: 0*/
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub enum USAT {
+    ///0: Offset is subtracted maintaining data integrity and keeping converted data size
+    Disabled = 0,
+    ///1: Offset is subtracted and result is saturated to maintain converted data size
+    Enabled = 1,
+}
+impl From<USAT> for bool {
+    #[inline(always)]
+    fn from(variant: USAT) -> Self {
+        variant as u8 != 0
+    }
+}
+///Field `USAT` reader - USAT
+pub type USAT_R = crate::BitReader<USAT>;
+impl USAT_R {
+    ///Get enumerated values variant
+    #[inline(always)]
+    pub const fn variant(&self) -> USAT {
+        match self.bits {
+            false => USAT::Disabled,
+            true => USAT::Enabled,
+        }
+    }
+    ///Offset is subtracted maintaining data integrity and keeping converted data size
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == USAT::Disabled
+    }
+    ///Offset is subtracted and result is saturated to maintain converted data size
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == USAT::Enabled
+    }
+}
+///Field `USAT` writer - USAT
+pub type USAT_W<'a, REG> = crate::BitWriter<'a, REG, USAT>;
+impl<'a, REG> USAT_W<'a, REG>
+where
+    REG: crate::Writable + crate::RegisterSpec,
+{
+    ///Offset is subtracted maintaining data integrity and keeping converted data size
+    #[inline(always)]
+    pub fn disabled(self) -> &'a mut crate::W<REG> {
+        self.variant(USAT::Disabled)
+    }
+    ///Offset is subtracted and result is saturated to maintain converted data size
+    #[inline(always)]
+    pub fn enabled(self) -> &'a mut crate::W<REG> {
+        self.variant(USAT::Enabled)
+    }
+}
+/**SSAT
+
+Value on reset: 0*/
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub enum SSAT {
+    ///0: Offset is subtracted maintaining data integrity and extending converted data size (9-bit and 15-bit signed format)
+    Disabled = 0,
+    ///1: Offset is subtracted and result is saturated to maintain converted data size
+    Enabled = 1,
+}
+impl From<SSAT> for bool {
+    #[inline(always)]
+    fn from(variant: SSAT) -> Self {
+        variant as u8 != 0
+    }
+}
+///Field `SSAT` reader - SSAT
+pub type SSAT_R = crate::BitReader<SSAT>;
+impl SSAT_R {
+    ///Get enumerated values variant
+    #[inline(always)]
+    pub const fn variant(&self) -> SSAT {
+        match self.bits {
+            false => SSAT::Disabled,
+            true => SSAT::Enabled,
+        }
+    }
+    ///Offset is subtracted maintaining data integrity and extending converted data size (9-bit and 15-bit signed format)
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == SSAT::Disabled
+    }
+    ///Offset is subtracted and result is saturated to maintain converted data size
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == SSAT::Enabled
+    }
+}
+///Field `SSAT` writer - SSAT
+pub type SSAT_W<'a, REG> = crate::BitWriter<'a, REG, SSAT>;
+impl<'a, REG> SSAT_W<'a, REG>
+where
+    REG: crate::Writable + crate::RegisterSpec,
+{
+    ///Offset is subtracted maintaining data integrity and extending converted data size (9-bit and 15-bit signed format)
+    #[inline(always)]
+    pub fn disabled(self) -> &'a mut crate::W<REG> {
+        self.variant(SSAT::Disabled)
+    }
+    ///Offset is subtracted and result is saturated to maintain converted data size
+    #[inline(always)]
+    pub fn enabled(self) -> &'a mut crate::W<REG> {
+        self.variant(SSAT::Enabled)
+    }
+}
+///Field `OFFSET_CH` reader - OFFSET_CH
+pub type OFFSET_CH_R = crate::FieldReader;
+///Field `OFFSET_CH` writer - OFFSET_CH
+pub type OFFSET_CH_W<'a, REG> = crate::FieldWriter<'a, REG, 5, u8, crate::Safe>;
+impl R {
+    ///Bits 0:23 - OFFSET
+    #[inline(always)]
+    pub fn offset(&self) -> OFFSET_R {
+        OFFSET_R::new(self.bits & 0x00ff_ffff)
+    }
+    ///Bit 24 - POSOFF
+    #[inline(always)]
+    pub fn posoff(&self) -> POSOFF_R {
+        POSOFF_R::new(((self.bits >> 24) & 1) != 0)
+    }
+    ///Bit 25 - USAT
+    #[inline(always)]
+    pub fn usat(&self) -> USAT_R {
+        USAT_R::new(((self.bits >> 25) & 1) != 0)
+    }
+    ///Bit 26 - SSAT
+    #[inline(always)]
+    pub fn ssat(&self) -> SSAT_R {
+        SSAT_R::new(((self.bits >> 26) & 1) != 0)
+    }
+    ///Bits 27:31 - OFFSET_CH
+    #[inline(always)]
+    pub fn offset_ch(&self) -> OFFSET_CH_R {
+        OFFSET_CH_R::new(((self.bits >> 27) & 0x1f) as u8)
+    }
+}
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("OFR")
+            .field("offset_ch", &self.offset_ch())
+            .field("ssat", &self.ssat())
+            .field("usat", &self.usat())
+            .field("posoff", &self.posoff())
+            .field("offset", &self.offset())
+            .finish()
+    }
+}
+impl W {
+    ///Bits 0:23 - OFFSET
+    #[inline(always)]
+    pub fn offset(&mut self) -> OFFSET_W<OFRrs> {
+        OFFSET_W::new(self, 0)
+    }
+    ///Bit 24 - POSOFF
+    #[inline(always)]
+    pub fn posoff(&mut self) -> POSOFF_W<OFRrs> {
+        POSOFF_W::new(self, 24)
+    }
+    ///Bit 25 - USAT
+    #[inline(always)]
+    pub fn usat(&mut self) -> USAT_W<OFRrs> {
+        USAT_W::new(self, 25)
+    }
+    ///Bit 26 - SSAT
+    #[inline(always)]
+    pub fn ssat(&mut self) -> SSAT_W<OFRrs> {
+        SSAT_W::new(self, 26)
+    }
+    ///Bits 27:31 - OFFSET_CH
+    #[inline(always)]
+    pub fn offset_ch(&mut self) -> OFFSET_CH_W<OFRrs> {
+        OFFSET_CH_W::new(self, 27)
+    }
+}
+/**ADC offset register
+
+You can [`read`](crate::Reg::read) this register and get [`ofr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ofr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
+
+See register [structure](https://stm32-rs.github.io/stm32-rs/STM32U535.html#ADC1:OFR[1])*/
+pub struct OFRrs;
+impl crate::RegisterSpec for OFRrs {
+    type Ux = u32;
+}
+///`read()` method returns [`ofr::R`](R) reader structure
+impl crate::Readable for OFRrs {}
+///`write(|w| ..)` method takes [`ofr::W`](W) writer structure
+impl crate::Writable for OFRrs {
+    type Safety = crate::Unsafe;
+}
+///`reset()` method sets OFR%s to value 0
+impl crate::Resettable for OFRrs {}

### external/vendor/stm32u5/src/stm32u535/adc1/pcsel.rs
@@ -0,0 +1,383 @@
+///Register `PCSEL` reader
+pub type R = crate::R<PCSELrs>;
+///Register `PCSEL` writer
+pub type W = crate::W<PCSELrs>;
+/**PCSEL0
+
+Value on reset: 0*/
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub enum PCSEL0 {
+    ///0: Input channel x is not preselected for conversion, the ADC conversion of this channel shows a wrong result.
+    NotPreselected = 0,
+    ///1: Input channel x is preselected for conversion
+    Preselected = 1,
+}
+impl From<PCSEL0> for bool {
+    #[inline(always)]
+    fn from(variant: PCSEL0) -> Self {
+        variant as u8 != 0
+    }
+}
+///Field `PCSEL0` reader - PCSEL0
+pub type PCSEL0_R = crate::BitReader<PCSEL0>;
+impl PCSEL0_R {
+    ///Get enumerated values variant
+    #[inline(always)]
+    pub const fn variant(&self) -> PCSEL0 {
+        match self.bits {
+            false => PCSEL0::NotPreselected,
+            true => PCSEL0::Preselected,
+        }
+    }
+    ///Input channel x is not preselected for conversion, the ADC conversion of this channel shows a wrong result.
+    #[inline(always)]
+    pub fn is_not_preselected(&self) -> bool {
+        *self == PCSEL0::NotPreselected
+    }
+    ///Input channel x is preselected for conversion
+    #[inline(always)]
+    pub fn is_preselected(&self) -> bool {
+        *self == PCSEL0::Preselected
+    }
+}
+///Field `PCSEL0` writer - PCSEL0
+pub type PCSEL0_W<'a, REG> = crate::BitWriter<'a, REG, PCSEL0>;
+impl<'a, REG> PCSEL0_W<'a, REG>
+where
+    REG: crate::Writable + crate::RegisterSpec,
+{
+    ///Input channel x is not preselected for conversion, the ADC conversion of this channel shows a wrong result.
+    #[inline(always)]
+    pub fn not_preselected(self) -> &'a mut crate::W<REG> {
+        self.variant(PCSEL0::NotPreselected)
+    }
+    ///Input channel x is preselected for conversion
+    #[inline(always)]
+    pub fn preselected(self) -> &'a mut crate::W<REG> {
+        self.variant(PCSEL0::Preselected)
+    }
+}
+///Field `PCSEL1` reader - PCSEL1
+pub use PCSEL0_R as PCSEL1_R;
+///Field `PCSEL2` reader - PCSEL2
+pub use PCSEL0_R as PCSEL2_R;
+///Field `PCSEL3` reader - PCSEL3
+pub use PCSEL0_R as PCSEL3_R;
+///Field `PCSEL4` reader - PCSEL4
+pub use PCSEL0_R as PCSEL4_R;
+///Field `PCSEL5` reader - PCSEL5
+pub use PCSEL0_R as PCSEL5_R;
+///Field `PCSEL6` reader - PCSEL6
+pub use PCSEL0_R as PCSEL6_R;
+///Field `PCSEL7` reader - PCSEL7
+pub use PCSEL0_R as PCSEL7_R;
+///Field `PCSEL8` reader - PCSEL8
+pub use PCSEL0_R as PCSEL8_R;
+///Field `PCSEL9` reader - PCSEL9
+pub use PCSEL0_R as PCSEL9_R;
+///Field `PCSEL10` reader - PCSEL10
+pub use PCSEL0_R as PCSEL10_R;
+///Field `PCSEL11` reader - PCSEL11
+pub use PCSEL0_R as PCSEL11_R;
+///Field `PCSEL12` reader - PCSEL12
+pub use PCSEL0_R as PCSEL12_R;
+///Field `PCSEL13` reader - PCSEL13
+pub use PCSEL0_R as PCSEL13_R;
+///Field `PCSEL14` reader - PCSEL14
+pub use PCSEL0_R as PCSEL14_R;
+///Field `PCSEL15` reader - PCSEL15
+pub use PCSEL0_R as PCSEL15_R;
+///Field `PCSEL16` reader - PCSEL16
+pub use PCSEL0_R as PCSEL16_R;
+///Field `PCSEL17` reader - PCSEL17
+pub use PCSEL0_R as PCSEL17_R;
+///Field `PCSEL18` reader - PCSEL18
+pub use PCSEL0_R as PCSEL18_R;
+///Field `PCSEL19` reader - PCSEL19
+pub use PCSEL0_R as PCSEL19_R;
+///Field `PCSEL1` writer - PCSEL1
+pub use PCSEL0_W as PCSEL1_W;
+///Field `PCSEL2` writer - PCSEL2
+pub use PCSEL0_W as PCSEL2_W;
+///Field `PCSEL3` writer - PCSEL3
+pub use PCSEL0_W as PCSEL3_W;
+///Field `PCSEL4` writer - PCSEL4
+pub use PCSEL0_W as PCSEL4_W;
+///Field `PCSEL5` writer - PCSEL5
+pub use PCSEL0_W as PCSEL5_W;
+///Field `PCSEL6` writer - PCSEL6
+pub use PCSEL0_W as PCSEL6_W;
+///Field `PCSEL7` writer - PCSEL7
+pub use PCSEL0_W as PCSEL7_W;
+///Field `PCSEL8` writer - PCSEL8
+pub use PCSEL0_W as PCSEL8_W;
+///Field `PCSEL9` writer - PCSEL9
+pub use PCSEL0_W as PCSEL9_W;
+///Field `PCSEL10` writer - PCSEL10
+pub use PCSEL0_W as PCSEL10_W;
+///Field `PCSEL11` writer - PCSEL11
+pub use PCSEL0_W as PCSEL11_W;
+///Field `PCSEL12` writer - PCSEL12
+pub use PCSEL0_W as PCSEL12_W;
+///Field `PCSEL13` writer - PCSEL13
+pub use PCSEL0_W as PCSEL13_W;
+///Field `PCSEL14` writer - PCSEL14
+pub use PCSEL0_W as PCSEL14_W;
+///Field `PCSEL15` writer - PCSEL15
+pub use PCSEL0_W as PCSEL15_W;
+///Field `PCSEL16` writer - PCSEL16
+pub use PCSEL0_W as PCSEL16_W;
+///Field `PCSEL17` writer - PCSEL17
+pub use PCSEL0_W as PCSEL17_W;
+///Field `PCSEL18` writer - PCSEL18
+pub use PCSEL0_W as PCSEL18_W;
+///Field `PCSEL19` writer - PCSEL19
+pub use PCSEL0_W as PCSEL19_W;
+impl R {
+    ///Bit 0 - PCSEL0
+    #[inline(always)]
+    pub fn pcsel0(&self) -> PCSEL0_R {
+        PCSEL0_R::new((self.bits & 1) != 0)
+    }
+    ///Bit 1 - PCSEL1
+    #[inline(always)]
+    pub fn pcsel1(&self) -> PCSEL1_R {
+        PCSEL1_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    ///Bit 2 - PCSEL2
+    #[inline(always)]
+    pub fn pcsel2(&self) -> PCSEL2_R {
+        PCSEL2_R::new(((self.bits >> 2) & 1) != 0)
+    }
+    ///Bit 3 - PCSEL3
+    #[inline(always)]
+    pub fn pcsel3(&self) -> PCSEL3_R {
+        PCSEL3_R::new(((self.bits >> 3) & 1) != 0)
+    }
+    ///Bit 4 - PCSEL4
+    #[inline(always)]
+    pub fn pcsel4(&self) -> PCSEL4_R {
+        PCSEL4_R::new(((self.bits >> 4) & 1) != 0)
+    }
+    ///Bit 5 - PCSEL5
+    #[inline(always)]
+    pub fn pcsel5(&self) -> PCSEL5_R {
+        PCSEL5_R::new(((self.bits >> 5) & 1) != 0)
+    }
+    ///Bit 6 - PCSEL6
+    #[inline(always)]
+    pub fn pcsel6(&self) -> PCSEL6_R {
+        PCSEL6_R::new(((self.bits >> 6) & 1) != 0)
+    }
+    ///Bit 7 - PCSEL7
+    #[inline(always)]
+    pub fn pcsel7(&self) -> PCSEL7_R {
+        PCSEL7_R::new(((self.bits >> 7) & 1) != 0)
+    }
+    ///Bit 8 - PCSEL8
+    #[inline(always)]
+    pub fn pcsel8(&self) -> PCSEL8_R {
+        PCSEL8_R::new(((self.bits >> 8) & 1) != 0)
+    }
+    ///Bit 9 - PCSEL9
+    #[inline(always)]
+    pub fn pcsel9(&self) -> PCSEL9_R {
+        PCSEL9_R::new(((self.bits >> 9) & 1) != 0)
+    }
+    ///Bit 10 - PCSEL10
+    #[inline(always)]
+    pub fn pcsel10(&self) -> PCSEL10_R {
+        PCSEL10_R::new(((self.bits >> 10) & 1) != 0)
+    }
+    ///Bit 11 - PCSEL11
+    #[inline(always)]
+    pub fn pcsel11(&self) -> PCSEL11_R {
+        PCSEL11_R::new(((self.bits >> 11) & 1) != 0)
+    }
+    ///Bit 12 - PCSEL12
+    #[inline(always)]
+    pub fn pcsel12(&self) -> PCSEL12_R {
+        PCSEL12_R::new(((self.bits >> 12) & 1) != 0)
+    }
+    ///Bit 13 - PCSEL13
+    #[inline(always)]
+    pub fn pcsel13(&self) -> PCSEL13_R {
+        PCSEL13_R::new(((self.bits >> 13) & 1) != 0)
+    }
+    ///Bit 14 - PCSEL14
+    #[inline(always)]
+    pub fn pcsel14(&self) -> PCSEL14_R {
+        PCSEL14_R::new(((self.bits >> 14) & 1) != 0)
+    }
+    ///Bit 15 - PCSEL15
+    #[inline(always)]
+    pub fn pcsel15(&self) -> PCSEL15_R {
+        PCSEL15_R::new(((self.bits >> 15) & 1) != 0)
+    }
+    ///Bit 16 - PCSEL16
+    #[inline(always)]
+    pub fn pcsel16(&self) -> PCSEL16_R {
+        PCSEL16_R::new(((self.bits >> 16) & 1) != 0)
+    }
+    ///Bit 17 - PCSEL17
+    #[inline(always)]
+    pub fn pcsel17(&self) -> PCSEL17_R {
+        PCSEL17_R::new(((self.bits >> 17) & 1) != 0)
+    }
+    ///Bit 18 - PCSEL18
+    #[inline(always)]
+    pub fn pcsel18(&self) -> PCSEL18_R {
+        PCSEL18_R::new(((self.bits >> 18) & 1) != 0)
+    }
+    ///Bit 19 - PCSEL19
+    #[inline(always)]
+    pub fn pcsel19(&self) -> PCSEL19_R {
+        PCSEL19_R::new(((self.bits >> 19) & 1) != 0)
+    }
+}
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("PCSEL")
+            .field("pcsel0", &self.pcsel0())
+            .field("pcsel19", &self.pcsel19())
+            .field("pcsel18", &self.pcsel18())
+            .field("pcsel17", &self.pcsel17())
+            .field("pcsel16", &self.pcsel16())
+            .field("pcsel15", &self.pcsel15())
+            .field("pcsel14", &self.pcsel14())
+            .field("pcsel13", &self.pcsel13())
+            .field("pcsel12", &self.pcsel12())
+            .field("pcsel11", &self.pcsel11())
+            .field("pcsel10", &self.pcsel10())
+            .field("pcsel9", &self.pcsel9())
+            .field("pcsel8", &self.pcsel8())
+            .field("pcsel7", &self.pcsel7())
+            .field("pcsel6", &self.pcsel6())
+            .field("pcsel5", &self.pcsel5())
+            .field("pcsel4", &self.pcsel4())
+            .field("pcsel3", &self.pcsel3())
+            .field("pcsel2", &self.pcsel2())
+            .field("pcsel1", &self.pcsel1())
+            .finish()
+    }
+}
+impl W {
+    ///Bit 0 - PCSEL0
+    #[inline(always)]
+    pub fn pcsel0(&mut self) -> PCSEL0_W<PCSELrs> {
+        PCSEL0_W::new(self, 0)
+    }
+    ///Bit 1 - PCSEL1
+    #[inline(always)]
+    pub fn pcsel1(&mut self) -> PCSEL1_W<PCSELrs> {
+        PCSEL1_W::new(self, 1)
+    }
+    ///Bit 2 - PCSEL2
+    #[inline(always)]
+    pub fn pcsel2(&mut self) -> PCSEL2_W<PCSELrs> {
+        PCSEL2_W::new(self, 2)
+    }
+    ///Bit 3 - PCSEL3
+    #[inline(always)]
+    pub fn pcsel3(&mut self) -> PCSEL3_W<PCSELrs> {
+        PCSEL3_W::new(self, 3)
+    }
+    ///Bit 4 - PCSEL4
+    #[inline(always)]
+    pub fn pcsel4(&mut self) -> PCSEL4_W<PCSELrs> {
+        PCSEL4_W::new(self, 4)
+    }
+    ///Bit 5 - PCSEL5
+    #[inline(always)]
+    pub fn pcsel5(&mut self) -> PCSEL5_W<PCSELrs> {
+        PCSEL5_W::new(self, 5)
+    }
+    ///Bit 6 - PCSEL6
+    #[inline(always)]
+    pub fn pcsel6(&mut self) -> PCSEL6_W<PCSELrs> {
+        PCSEL6_W::new(self, 6)
+    }
+    ///Bit 7 - PCSEL7
+    #[inline(always)]
+    pub fn pcsel7(&mut self) -> PCSEL7_W<PCSELrs> {
+        PCSEL7_W::new(self, 7)
+    }
+    ///Bit 8 - PCSEL8
+    #[inline(always)]
+    pub fn pcsel8(&mut self) -> PCSEL8_W<PCSELrs> {
+        PCSEL8_W::new(self, 8)
+    }
+    ///Bit 9 - PCSEL9
+    #[inline(always)]
+    pub fn pcsel9(&mut self) -> PCSEL9_W<PCSELrs> {
+        PCSEL9_W::new(self, 9)
+    }
+    ///Bit 10 - PCSEL10
+    #[inline(always)]
+    pub fn pcsel10(&mut self) -> PCSEL10_W<PCSELrs> {
+        PCSEL10_W::new(self, 10)
+    }
+    ///Bit 11 - PCSEL11
+    #[inline(always)]
+    pub fn pcsel11(&mut self) -> PCSEL11_W<PCSELrs> {
+        PCSEL11_W::new(self, 11)
+    }
+    ///Bit 12 - PCSEL12
+    #[inline(always)]
+    pub fn pcsel12(&mut self) -> PCSEL12_W<PCSELrs> {
+        PCSEL12_W::new(self, 12)
+    }
+    ///Bit 13 - PCSEL13
+    #[inline(always)]
+    pub fn pcsel13(&mut self) -> PCSEL13_W<PCSELrs> {
+        PCSEL13_W::new(self, 13)
+    }
+    ///Bit 14 - PCSEL14
+    #[inline(always)]
+    pub fn pcsel14(&mut self) -> PCSEL14_W<PCSELrs> {
+        PCSEL14_W::new(self, 14)
+    }
+    ///Bit 15 - PCSEL15
+    #[inline(always)]
+    pub fn pcsel15(&mut self) -> PCSEL15_W<PCSELrs> {
+        PCSEL15_W::new(self, 15)
+    }
+    ///Bit 16 - PCSEL16
+    #[inline(always)]
+    pub fn pcsel16(&mut self) -> PCSEL16_W<PCSELrs> {
+        PCSEL16_W::new(self, 16)
+    }
+    ///Bit 17 - PCSEL17
+    #[inline(always)]
+    pub fn pcsel17(&mut self) -> PCSEL17_W<PCSELrs> {
+        PCSEL17_W::new(self, 17)
+    }
+    ///Bit 18 - PCSEL18
+    #[inline(always)]
+    pub fn pcsel18(&mut self) -> PCSEL18_W<PCSELrs> {
+        PCSEL18_W::new(self, 18)
+    }
+    ///Bit 19 - PCSEL19
+    #[inline(always)]
+    pub fn pcsel19(&mut self) -> PCSEL19_W<PCSELrs> {
+        PCSEL19_W::new(self, 19)
+    }
+}
+/**ADC channel preselection register
+
+You can [`read`](crate::Reg::read) this register and get [`pcsel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcsel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
+
+See register [structure](https://stm32-rs.github.io/stm32-rs/STM32U535.html#ADC1:PCSEL)*/
+pub struct PCSELrs;
+impl crate::RegisterSpec for PCSELrs {
+    type Ux = u32;
+}
+///`read()` method returns [`pcsel::R`](R) reader structure
+impl crate::Readable for PCSELrs {}
+///`write(|w| ..)` method takes [`pcsel::W`](W) writer structure
+impl crate::Writable for PCSELrs {
+    type Safety = crate::Unsafe;
+}
+///`reset()` method sets PCSEL to value 0
+impl crate::Resettable for PCSELrs {}

### external/vendor/stm32u5/src/stm32u535/adc1/smpr1.rs
@@ -0,0 +1,306 @@
+///Register `SMPR1` reader
+pub type R = crate::R<SMPR1rs>;
+///Register `SMPR1` writer
+pub type W = crate::W<SMPR1rs>;
+/**Channel %s sample time selection
+
+Value on reset: 0*/
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+#[repr(u8)]
+pub enum SMP0 {
+    ///0: 5 ADC clock cycles
+    Cycles5 = 0,
+    ///1: 6 ADC clock cycles
+    Cycles6 = 1,
+    ///2: 12 ADC clock cycles
+    Cycles12 = 2,
+    ///3: 20 ADC clock cycles
+    Cycles20 = 3,
+    ///4: 36 ADC clock cycles
+    Cycles36 = 4,
+    ///5: 68 ADC clock cycles
+    Cycles68 = 5,
+    ///6: 391 ADC clock cycles
+    Cycles391 = 6,
+    ///7: 814 ADC clock cycles
+    Cycles814 = 7,
+}
+impl From<SMP0> for u8 {
+    #[inline(always)]
+    fn from(variant: SMP0) -> Self {
+        variant as _
+    }
+}
+impl crate::FieldSpec for SMP0 {
+    type Ux = u8;
+}
+impl crate::IsEnum for SMP0 {}
+///Field `SMP(0-9)` reader - Channel %s sample time selection
+pub type SMP_R = crate::FieldReader<SMP0>;
+impl SMP_R {
+    ///Get enumerated values variant
+    #[inline(always)]
+    pub const fn variant(&self) -> SMP0 {
+        match self.bits {
+            0 => SMP0::Cycles5,
+            1 => SMP0::Cycles6,
+            2 => SMP0::Cycles12,
+            3 => SMP0::Cycles20,
+            4 => SMP0::Cycles36,
+            5 => SMP0::Cycles68,
+            6 => SMP0::Cycles391,
+            7 => SMP0::Cycles814,
+            _ => unreachable!(),
+        }
+    }
+    ///5 ADC clock cycles
+    #[inline(always)]
+    pub fn is_cycles5(&self) -> bool {
+        *self == SMP0::Cycles5
+    }
+    ///6 ADC clock cycles
+    #[inline(always)]
+    pub fn is_cycles6(&self) -> bool {
+        *self == SMP0::Cycles6
+    }
+    ///12 ADC clock cycles
+    #[inline(always)]
+    pub fn is_cycles12(&self) -> bool {
+        *self == SMP0::Cycles12
+    }
+    ///20 ADC clock cycles
+    #[inline(always)]
+    pub fn is_cycles20(&self) -> bool {
+        *self == SMP0::Cycles20
+    }
+    ///36 ADC clock cycles
+    #[inline(always)]
+    pub fn is_cycles36(&self) -> bool {
+        *self == SMP0::Cycles36
+    }
+    ///68 ADC clock cycles
+    #[inline(always)]
+    pub fn is_cycles68(&self) -> bool {
+        *self == SMP0::Cycles68
+    }
+    ///391 ADC clock cycles
+    #[inline(always)]
+    pub fn is_cycles391(&self) -> bool {
+        *self == SMP0::Cycles391
+    }
+    ///814 ADC clock cycles
+    #[inline(always)]
+    pub fn is_cycles814(&self) -> bool {
+        *self == SMP0::Cycles814
+    }
+}
+///Field `SMP(0-9)` writer - Channel %s sample time selection
+pub type SMP_W<'a, REG> = crate::FieldWriter<'a, REG, 3, SMP0, crate::Safe>;
+impl<'a, REG> SMP_W<'a, REG>
+where
+    REG: crate::Writable + crate::RegisterSpec,
+    REG::Ux: From<u8>,
+{
+    ///5 ADC clock cycles
+    #[inline(always)]
+    pub fn cycles5(self) -> &'a mut crate::W<REG> {
+        self.variant(SMP0::Cycles5)
+    }
+    ///6 ADC clock cycles
+    #[inline(always)]
+    pub fn cycles6(self) -> &'a mut crate::W<REG> {
+        self.variant(SMP0::Cycles6)
+    }
+    ///12 ADC clock cycles
+    #[inline(always)]
+    pub fn cycles12(self) -> &'a mut crate::W<REG> {
+        self.variant(SMP0::Cycles12)
+    }
+    ///20 ADC clock cycles
+    #[inline(always)]
+    pub fn cycles20(self) -> &'a mut crate::W<REG> {
+        self.variant(SMP0::Cycles20)
+    }
+    ///36 ADC clock cycles
+    #[inline(always)]
+    pub fn cycles36(self) -> &'a mut crate::W<REG> {
+        self.variant(SMP0::Cycles36)
+    }
+    ///68 ADC clock cycles
+    #[inline(always)]
+    pub fn cycles68(self) -> &'a mut crate::W<REG> {
+        self.variant(SMP0::Cycles68)
+    }
+    ///391 ADC clock cycles
+    #[inline(always)]
+    pub fn cycles391(self) -> &'a mut crate::W<REG> {
+        self.variant(SMP0::Cycles391)
+    }
+    ///814 ADC clock cycles
+    #[inline(always)]
+    pub fn cycles814(self) -> &'a mut crate::W<REG> {
+        self.variant(SMP0::Cycles814)
+    }
+}
+impl R {
+    ///Channel (0-9) sample time selection
+    ///
+    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `SMP0` field.</div>
+    #[inline(always)]
+    pub fn smp(&self, n: u8) -> SMP_R {
+        #[allow(clippy::no_effect)]
+        [(); 10][n as usize];
+        SMP_R::new(((self.bits >> (n * 3)) & 7) as u8)
+    }
+    ///Iterator for array of:
+    ///Channel (0-9) sample time selection
+    #[inline(always)]
+    pub fn smp_iter(&self) -> impl Iterator<Item = SMP_R> + '_ {
+        (0..10).map(move |n| SMP_R::new(((self.bits >> (n * 3)) & 7) as u8))
+    }
+    ///Bits 0:2 - Channel 0 sample time selection
+    #[inline(always)]
+    pub fn smp0(&self) -> SMP_R {
+        SMP_R::new((self.bits & 7) as u8)
+    }
+    ///Bits 3:5 - Channel 1 sample time selection
+    #[inline(always)]
+    pub fn smp1(&self) -> SMP_R {
+        SMP_R::new(((self.bits >> 3) & 7) as u8)
+    }
+    ///Bits 6:8 - Channel 2 sample time selection
+    #[inline(always)]
+    pub fn smp2(&self) -> SMP_R {
+        SMP_R::new(((self.bits >> 6) & 7) as u8)
+    }
+    ///Bits 9:11 - Channel 3 sample time selection
+    #[inline(always)]
+    pub fn smp3(&self) -> SMP_R {
+        SMP_R::new(((self.bits >> 9) & 7) as u8)
+    }
+    ///Bits 12:14 - Channel 4 sample time selection
+    #[inline(always)]
+    pub fn smp4(&self) -> SMP_R {
+        SMP_R::new(((self.bits >> 12) & 7) as u8)
+    }
+    ///Bits 15:17 - Channel 5 sample time selection
+    #[inline(always)]
+    pub fn smp5(&self) -> SMP_R {
+        SMP_R::new(((self.bits >> 15) & 7) as u8)
+    }
+    ///Bits 18:20 - Channel 6 sample time selection
+    #[inline(always)]
+    pub fn smp6(&self) -> SMP_R {
+        SMP_R::new(((self.bits >> 18) & 7) as u8)
+    }
+    ///Bits 21:23 - Channel 7 sample time selection
+    #[inline(always)]
+    pub fn smp7(&self) -> SMP_R {
+        SMP_R::new(((self.bits >> 21) & 7) as u8)
+    }
+    ///Bits 24:26 - Channel 8 sample time selection
+    #[inline(always)]
+    pub fn smp8(&self) -> SMP_R {
+        SMP_R::new(((self.bits >> 24) & 7) as u8)
+    }
+    ///Bits 27:29 - Channel 9 sample time selection
+    #[inline(always)]
+    pub fn smp9(&self) -> SMP_R {
+        SMP_R::new(((self.bits >> 27) & 7) as u8)
+    }
+}
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("SMPR1")
+            .field("smp0", &self.smp0())
+            .field("smp1", &self.smp1())
+            .field("smp2", &self.smp2())
+            .field("smp3", &self.smp3())
+            .field("smp4", &self.smp4())
+            .field("smp5", &self.smp5())
+            .field("smp6", &self.smp6())
+            .field("smp7", &self.smp7())
+            .field("smp8", &self.smp8())
+            .field("smp9", &self.smp9())
+            .finish()
+    }
+}
+impl W {
+    ///Channel (0-9) sample time selection
+    ///
+    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `SMP0` field.</div>
+    #[inline(always)]
+    pub fn smp(&mut self, n: u8) -> SMP_W<SMPR1rs> {
+        #[allow(clippy::no_effect)]
+        [(); 10][n as usize];
+        SMP_W::new(self, n * 3)
+    }
+    ///Bits 0:2 - Channel 0 sample time selection
+    #[inline(always)]
+    pub fn smp0(&mut self) -> SMP_W<SMPR1rs> {
+        SMP_W::new(self, 0)
+    }
+    ///Bits 3:5 - Channel 1 sample time selection
+    #[inline(always)]
+    pub fn smp1(&mut self) -> SMP_W<SMPR1rs> {
+        SMP_W::new(self, 3)
+    }
+    ///Bits 6:8 - Channel 2 sample time selection
+    #[inline(always)]
+    pub fn smp2(&mut self) -> SMP_W<SMPR1rs> {
+        SMP_W::new(self, 6)
+    }
+    ///Bits 9:11 - Channel 3 sample time selection
+    #[inline(always)]
+    pub fn smp3(&mut self) -> SMP_W<SMPR1rs> {
+        SMP_W::new(self, 9)
+    }
+    ///Bits 12:14 - Channel 4 sample time selection
+    #[inline(always)]
+    pub fn smp4(&mut self) -> SMP_W<SMPR1rs> {
+        SMP_W::new(self, 12)
+    }
+    ///Bits 15:17 - Channel 5 sample time selection
+    #[inline(always)]
+    pub fn smp5(&mut self) -> SMP_W<SMPR1rs> {
+        SMP_W::new(self, 15)
+    }
+    ///Bits 18:20 - Channel 6 sample time selection
+    #[inline(always)]
+    pub fn smp6(&mut self) -> SMP_W<SMPR1rs> {
+        SMP_W::new(self, 18)
+    }
+    ///Bits 21:23 - Channel 7 sample time selection
+    #[inline(always)]
+    pub fn smp7(&mut self) -> SMP_W<SMPR1rs> {
+        SMP_W::new(self, 21)
+    }
+    ///Bits 24:26 - Channel 8 sample time selection
+    #[inline(always)]
+    pub fn smp8(&mut self) -> SMP_W<SMPR1rs> {
+        SMP_W::new(self, 24)
+    }
+    ///Bits 27:29 - Channel 9 sample time selection
+    #[inline(always)]
+    pub fn smp9(&mut self) -> SMP_W<SMPR1rs> {
+        SMP_W::new(self, 27)
+    }
+}
+/**ADC sample time register 1
+
+You can [`read`](crate::Reg::read) this register and get [`smpr1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`smpr1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
+
+See register [structure](https://stm32-rs.github.io/stm32-rs/STM32U535.html#ADC1:SMPR1)*/
+pub struct SMPR1rs;
+impl crate::RegisterSpec for SMPR1rs {
+    type Ux = u32;
+}
+///`read()` method returns [`smpr1::R`](R) reader structure
+impl crate::Readable for SMPR1rs {}
+///`write(|w| ..)` method takes [`smpr1::W`](W) writer structure
+impl crate::Writable for SMPR1rs {
+    type Safety = crate::Unsafe;
+}
+///`reset()` method sets SMPR1 to value 0
+impl crate::Resettable for SMPR1rs {}

### external/vendor/stm32u5/src/stm32u535/adc1/smpr2.rs
@@ -0,0 +1,171 @@
+///Register `SMPR2` reader
+pub type R = crate::R<SMPR2rs>;
+///Register `SMPR2` writer
+pub type W = crate::W<SMPR2rs>;
+///Channel %s sample time selection
+pub use super::smpr1::SMP0;
+///Field `SMP(10-19)` reader - Channel %s sample time selection
+pub use super::smpr1::SMP_R;
+///Field `SMP(10-19)` writer - Channel %s sample time selection
+pub use super::smpr1::SMP_W;
+impl R {
+    ///Channel (10-19) sample time selection
+    ///
+    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `SMP10` field.</div>
+    #[inline(always)]
+    pub fn smp(&self, n: u8) -> SMP_R {
+        #[allow(clippy::no_effect)]
+        [(); 10][n as usize];
+        SMP_R::new(((self.bits >> (n * 3)) & 7) as u8)
+    }
+    ///Iterator for array of:
+    ///Channel (10-19) sample time selection
+    #[inline(always)]
+    pub fn smp_iter(&self) -> impl Iterator<Item = SMP_R> + '_ {
+        (0..10).map(move |n| SMP_R::new(((self.bits >> (n * 3)) & 7) as u8))
+    }
+    ///Bits 0:2 - Channel 10 sample time selection
+    #[inline(always)]
+    pub fn smp10(&self) -> SMP_R {
+        SMP_R::new((self.bits & 7) as u8)
+    }
+    ///Bits 3:5 - Channel 11 sample time selection
+    #[inline(always)]
+    pub fn smp11(&self) -> SMP_R {
+        SMP_R::new(((self.bits >> 3) & 7) as u8)
+    }
+    ///Bits 6:8 - Channel 12 sample time selection
+    #[inline(always)]
+    pub fn smp12(&self) -> SMP_R {
+        SMP_R::new(((self.bits >> 6) & 7) as u8)
+    }
+    ///Bits 9:11 - Channel 13 sample time selection
+    #[inline(always)]
+    pub fn smp13(&self) -> SMP_R {
+        SMP_R::new(((self.bits >> 9) & 7) as u8)
+    }
+    ///Bits 12:14 - Channel 14 sample time selection
+    #[inline(always)]
+    pub fn smp14(&self) -> SMP_R {
+        SMP_R::new(((self.bits >> 12) & 7) as u8)
+    }
+    ///Bits 15:17 - Channel 15 sample time selection
+    #[inline(always)]
+    pub fn smp15(&self) -> SMP_R {
+        SMP_R::new(((self.bits >> 15) & 7) as u8)
+    }
+    ///Bits 18:20 - Channel 16 sample time selection
+    #[inline(always)]
+    pub fn smp16(&self) -> SMP_R {
+        SMP_R::new(((self.bits >> 18) & 7) as u8)
+    }
+    ///Bits 21:23 - Channel 17 sample time selection
+    #[inline(always)]
+    pub fn smp17(&self) -> SMP_R {
+        SMP_R::new(((self.bits >> 21) & 7) as u8)
+    }
+    ///Bits 24:26 - Channel 18 sample time selection
+    #[inline(always)]
+    pub fn smp18(&self) -> SMP_R {
+        SMP_R::new(((self.bits >> 24) & 7) as u8)
+    }
+    ///Bits 27:29 - Channel 19 sample time selection
+    #[inline(always)]
+    pub fn smp19(&self) -> SMP_R {
+        SMP_R::new(((self.bits >> 27) & 7) as u8)
+    }
+}
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("SMPR2")
+            .field("smp10", &self.smp10())
+            .field("smp11", &self.smp11())
+            .field("smp12", &self.smp12())
+            .field("smp13", &self.smp13())
+            .field("smp14", &self.smp14())
+            .field("smp15", &self.smp15())
+            .field("smp16", &self.smp16())
+            .field("smp17", &self.smp17())
+            .field("smp18", &self.smp18())
+            .field("smp19", &self.smp19())
+            .finish()
+    }
+}
+impl W {
+    ///Channel (10-19) sample time selection
+    ///
+    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `SMP10` field.</div>
+    #[inline(always)]
+    pub fn smp(&mut self, n: u8) -> SMP_W<SMPR2rs> {
+        #[allow(clippy::no_effect)]
+        [(); 10][n as usize];
+        SMP_W::new(self, n * 3)
+    }
+    ///Bits 0:2 - Channel 10 sample time selection
+    #[inline(always)]
+    pub fn smp10(&mut self) -> SMP_W<SMPR2rs> {
+        SMP_W::new(self, 0)
+    }
+    ///Bits 3:5 - Channel 11 sample time selection
+    #[inline(always)]
+    pub fn smp11(&mut self) -> SMP_W<SMPR2rs> {
+        SMP_W::new(self, 3)
+    }
+    ///Bits 6:8 - Channel 12 sample time selection
+    #[inline(always)]
+    pub fn smp12(&mut self) -> SMP_W<SMPR2rs> {
+        SMP_W::new(self, 6)
+    }
+    ///Bits 9:11 - Channel 13 sample time selection
+    #[inline(always)]
+    pub fn smp13(&mut self) -> SMP_W<SMPR2rs> {
+        SMP_W::new(self, 9)
+    }
+    ///Bits 12:14 - Channel 14 sample time selection
+    #[inline(always)]
+    pub fn smp14(&mut self) -> SMP_W<SMPR2rs> {
+        SMP_W::new(self, 12)
+    }
+    ///Bits 15:17 - Channel 15 sample time selection
+    #[inline(always)]
+    pub fn smp15(&mut self) -> SMP_W<SMPR2rs> {
+        SMP_W::new(self, 15)
+    }
+    ///Bits 18:20 - Channel 16 sample time selection
+    #[inline(always)]
+    pub fn smp16(&mut self) -> SMP_W<SMPR2rs> {
+        SMP_W::new(self, 18)
+    }
+    ///Bits 21:23 - Channel 17 sample time selection
+    #[inline(always)]
+    pub fn smp17(&mut self) -> SMP_W<SMPR2rs> {
+        SMP_W::new(self, 21)
+    }
+    ///Bits 24:26 - Channel 18 sample time selection
+    #[inline(always)]
+    pub fn smp18(&mut self) -> SMP_W<SMPR2rs> {
+        SMP_W::new(self, 24)
+    }
+    ///Bits 27:29 - Channel 19 sample time selection
+    #[inline(always)]
+    pub fn smp19(&mut self) -> SMP_W<SMPR2rs> {
+        SMP_W::new(self, 27)
+    }
+}
+/**ADC sample time register 2
+
+You can [`read`](crate::Reg::read) this register and get [`smpr2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`smpr2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
+
+See register [structure](https://stm32-rs.github.io/stm32-rs/STM32U535.html#ADC1:SMPR2)*/
+pub struct SMPR2rs;
+impl crate::RegisterSpec for SMPR2rs {
+    type Ux = u32;
+}
+///`read()` method returns [`smpr2::R`](R) reader structure
+impl crate::Readable for SMPR2rs {}
+///`write(|w| ..)` method takes [`smpr2::W`](W) writer structure
+impl crate::Writable for SMPR2rs {
+    type Safety = crate::Unsafe;
+}
+///`reset()` method sets SMPR2 to value 0
+impl crate::Resettable for SMPR2rs {}

### external/vendor/stm32u5/src/stm32u535/adc1/sqr1.rs
@@ -0,0 +1,118 @@
+///Register `SQR1` reader
+pub type R = crate::R<SQR1rs>;
+///Register `SQR1` writer
+pub type W = crate::W<SQR1rs>;
+///Field `L` reader - L
+pub type L_R = crate::FieldReader;
+///Field `L` writer - L
+pub type L_W<'a, REG> = crate::FieldWriter<'a, REG, 4, u8, crate::Safe>;
+///Field `SQ(1-4)` reader - %s conversion in regular sequence
+pub type SQ_R = crate::FieldReader;
+///Field `SQ(1-4)` writer - %s conversion in regular sequence
+pub type SQ_W<'a, REG> = crate::FieldWriter<'a, REG, 5, u8, crate::Safe>;
+impl R {
+    ///Bits 0:3 - L
+    #[inline(always)]
+    pub fn l(&self) -> L_R {
+        L_R::new((self.bits & 0x0f) as u8)
+    }
+    ///(1-4) conversion in regular sequence
+    ///
+    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `SQ1` field.</div>
+    #[inline(always)]
+    pub fn sq(&self, n: u8) -> SQ_R {
+        #[allow(clippy::no_effect)]
+        [(); 4][n as usize];
+        SQ_R::new(((self.bits >> (n * 6 + 6)) & 0x1f) as u8)
+    }
+    ///Iterator for array of:
+    ///(1-4) conversion in regular sequence
+    #[inline(always)]
+    pub fn sq_iter(&self) -> impl Iterator<Item = SQ_R> + '_ {
+        (0..4).map(move |n| SQ_R::new(((self.bits >> (n * 6 + 6)) & 0x1f) as u8))
+    }
+    ///Bits 6:10 - 1 conversion in regular sequence
+    #[inline(always)]
+    pub fn sq1(&self) -> SQ_R {
+        SQ_R::new(((self.bits >> 6) & 0x1f) as u8)
+    }
+    ///Bits 12:16 - 2 conversion in regular sequence
+    #[inline(always)]
+    pub fn sq2(&self) -> SQ_R {
+        SQ_R::new(((self.bits >> 12) & 0x1f) as u8)
+    }
+    ///Bits 18:22 - 3 conversion in regular sequence
+    #[inline(always)]
+    pub fn sq3(&self) -> SQ_R {
+        SQ_R::new(((self.bits >> 18) & 0x1f) as u8)
+    }
+    ///Bits 24:28 - 4 conversion in regular sequence
+    #[inline(always)]
+    pub fn sq4(&self) -> SQ_R {
+        SQ_R::new(((self.bits >> 24) & 0x1f) as u8)
+    }
+}
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("SQR1")
+            .field("sq1", &self.sq1())
+            .field("sq2", &self.sq2())
+            .field("sq3", &self.sq3())
+            .field("sq4", &self.sq4())
+            .field("l", &self.l())
+            .finish()
+    }
+}
+impl W {
+    ///Bits 0:3 - L
+    #[inline(always)]
+    pub fn l(&mut self) -> L_W<SQR1rs> {
+        L_W::new(self, 0)
+    }
+    ///(1-4) conversion in regular sequence
+    ///
+    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `SQ1` field.</div>
+    #[inline(always)]
+    pub fn sq(&mut self, n: u8) -> SQ_W<SQR1rs> {
+        #[allow(clippy::no_effect)]
+        [(); 4][n as usize];
+        SQ_W::new(self, n * 6 + 6)
+    }
+    ///Bits 6:10 - 1 conversion in regular sequence
+    #[inline(always)]
+    pub fn sq1(&mut self) -> SQ_W<SQR1rs> {
+        SQ_W::new(self, 6)
+    }
+    ///Bits 12:16 - 2 conversion in regular sequence
+    #[inline(always)]
+    pub fn sq2(&mut self) -> SQ_W<SQR1rs> {
+        SQ_W::new(self, 12)
+    }
+    ///Bits 18:22 - 3 conversion in regular sequence
+    #[inline(always)]
+    pub fn sq3(&mut self) -> SQ_W<SQR1rs> {
+        SQ_W::new(self, 18)
+    }
+    ///Bits 24:28 - 4 conversion in regular sequence
+    #[inline(always)]
+    pub fn sq4(&mut self) -> SQ_W<SQR1rs> {
+        SQ_W::new(self, 24)
+    }
+}
+/**ADC regular sequence register 1
+
+You can [`read`](crate::Reg::read) this register and get [`sqr1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sqr1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
+
+See register [structure](https://stm32-rs.github.io/stm32-rs/STM32U535.html#ADC1:SQR1)*/
+pub struct SQR1rs;
+impl crate::RegisterSpec for SQR1rs {
+    type Ux = u32;
+}
+///`read()` method returns [`sqr1::R`](R) reader structure
+impl crate::Readable for SQR1rs {}
+///`write(|w| ..)` method takes [`sqr1::W`](W) writer structure
+impl crate::Writable for SQR1rs {
+    type Safety = crate::Unsafe;
+}
+///`reset()` method sets SQR1 to value 0
+impl crate::Resettable for SQR1rs {}

### external/vendor/stm32u5/src/stm32u535/adc1/sqr2.rs
@@ -0,0 +1,114 @@
+///Register `SQR2` reader
+pub type R = crate::R<SQR2rs>;
+///Register `SQR2` writer
+pub type W = crate::W<SQR2rs>;
+///Field `SQ(5-9)` reader - %s conversion in regular sequence
+pub type SQ_R = crate::FieldReader;
+///Field `SQ(5-9)` writer - %s conversion in regular sequence
+pub type SQ_W<'a, REG> = crate::FieldWriter<'a, REG, 5, u8, crate::Safe>;
+impl R {
+    ///(5-9) conversion in regular sequence
+    ///
+    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `SQ5` field.</div>
+    #[inline(always)]
+    pub fn sq(&self, n: u8) -> SQ_R {
+        #[allow(clippy::no_effect)]
+        [(); 5][n as usize];
+        SQ_R::new(((self.bits >> (n * 6)) & 0x1f) as u8)
+    }
+    ///Iterator for array of:
+    ///(5-9) conversion in regular sequence
+    #[inline(always)]
+    pub fn sq_iter(&self) -> impl Iterator<Item = SQ_R> + '_ {
+        (0..5).map(move |n| SQ_R::new(((self.bits >> (n * 6)) & 0x1f) as u8))
+    }
+    ///Bits 0:4 - 5 conversion in regular sequence
+    #[inline(always)]
+    pub fn sq5(&self) -> SQ_R {
+        SQ_R::new((self.bits & 0x1f) as u8)
+    }
+    ///Bits 6:10 - 6 conversion in regular sequence
+    #[inline(always)]
+    pub fn sq6(&self) -> SQ_R {
+        SQ_R::new(((self.bits >> 6) & 0x1f) as u8)
+    }
+    ///Bits 12:16 - 7 conversion in regular sequence
+    #[inline(always)]
+    pub fn sq7(&self) -> SQ_R {
+        SQ_R::new(((self.bits >> 12) & 0x1f) as u8)
+    }
+    ///Bits 18:22 - 8 conversion in regular sequence
+    #[inline(always)]
+    pub fn sq8(&self) -> SQ_R {
+        SQ_R::new(((self.bits >> 18) & 0x1f) as u8)
+    }
+    ///Bits 24:28 - 9 conversion in regular sequence
+    #[inline(always)]
+    pub fn sq9(&self) -> SQ_R {
+        SQ_R::new(((self.bits >> 24) & 0x1f) as u8)
+    }
+}
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("SQR2")
+            .field("sq5", &self.sq5())
+            .field("sq6", &self.sq6())
+            .field("sq7", &self.sq7())
+            .field("sq8", &self.sq8())
+            .field("sq9", &self.sq9())
+            .finish()
+    }
+}
+impl W {
+    ///(5-9) conversion in regular sequence
+    ///
+    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `SQ5` field.</div>
+    #[inline(always)]
+    pub fn sq(&mut self, n: u8) -> SQ_W<SQR2rs> {
+        #[allow(clippy::no_effect)]
+        [(); 5][n as usize];
+        SQ_W::new(self, n * 6)
+    }
+    ///Bits 0:4 - 5 conversion in regular sequence
+    #[inline(always)]
+    pub fn sq5(&mut self) -> SQ_W<SQR2rs> {
+        SQ_W::new(self, 0)
+    }
+    ///Bits 6:10 - 6 conversion in regular sequence
+    #[inline(always)]
+    pub fn sq6(&mut self) -> SQ_W<SQR2rs> {
+        SQ_W::new(self, 6)
+    }
+    ///Bits 12:16 - 7 conversion in regular sequence
+    #[inline(always)]
+    pub fn sq7(&mut self) -> SQ_W<SQR2rs> {
+        SQ_W::new(self, 12)
+    }
+    ///Bits 18:22 - 8 conversion in regular sequence
+    #[inline(always)]
+    pub fn sq8(&mut self) -> SQ_W<SQR2rs> {
+        SQ_W::new(self, 18)
+    }
+    ///Bits 24:28 - 9 conversion in regular sequence
+    #[inline(always)]
+    pub fn sq9(&mut self) -> SQ_W<SQR2rs> {
+        SQ_W::new(self, 24)
+    }
+}
+/**ADC regular sequence register 2
+
+You can [`read`](crate::Reg::read) this register and get [`sqr2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sqr2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
+
+See register [structure](https://stm32-rs.github.io/stm32-rs/STM32U535.html#ADC1:SQR2)*/
+pub struct SQR2rs;
+impl crate::RegisterSpec for SQR2rs {
+    type Ux = u32;
+}
+///`read()` method returns [`sqr2::R`](R) reader structure
+impl crate::Readable for SQR2rs {}
+///`write(|w| ..)` method takes [`sqr2::W`](W) writer structure
+impl crate::Writable for SQR2rs {
+    type Safety = crate::Unsafe;
+}
+///`reset()` method sets SQR2 to value 0
+impl crate::Resettable for SQR2rs {}

### external/vendor/stm32u5/src/stm32u535/adc1/sqr3.rs
@@ -0,0 +1,114 @@
+///Register `SQR3` reader
+pub type R = crate::R<SQR3rs>;
+///Register `SQR3` writer
+pub type W = crate::W<SQR3rs>;
+///Field `SQ(10-14)` reader - %s conversion in regular sequence
+pub type SQ_R = crate::FieldReader;
+///Field `SQ(10-14)` writer - %s conversion in regular sequence
+pub type SQ_W<'a, REG> = crate::FieldWriter<'a, REG, 5, u8, crate::Safe>;
+impl R {
+    ///(10-14) conversion in regular sequence
+    ///
+    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `SQ10` field.</div>
+    #[inline(always)]
+    pub fn sq(&self, n: u8) -> SQ_R {
+        #[allow(clippy::no_effect)]
+        [(); 5][n as usize];
+        SQ_R::new(((self.bits >> (n * 6)) & 0x1f) as u8)
+    }
+    ///Iterator for array of:
+    ///(10-14) conversion in regular sequence
+    #[inline(always)]
+    pub fn sq_iter(&self) -> impl Iterator<Item = SQ_R> + '_ {
+        (0..5).map(move |n| SQ_R::new(((self.bits >> (n * 6)) & 0x1f) as u8))
+    }
+    ///Bits 0:4 - 10 conversion in regular sequence
+    #[inline(always)]
+    pub fn sq10(&self) -> SQ_R {
+        SQ_R::new((self.bits & 0x1f) as u8)
+    }
+    ///Bits 6:10 - 11 conversion in regular sequence
+    #[inline(always)]
+    pub fn sq11(&self) -> SQ_R {
+        SQ_R::new(((self.bits >> 6) & 0x1f) as u8)
+    }
+    ///Bits 12:16 - 12 conversion in regular sequence
+    #[inline(always)]
+    pub fn sq12(&self) -> SQ_R {
+        SQ_R::new(((self.bits >> 12) & 0x1f) as u8)
+    }
+    ///Bits 18:22 - 13 conversion in regular sequence
+    #[inline(always)]
+    pub fn sq13(&self) -> SQ_R {
+        SQ_R::new(((self.bits >> 18) & 0x1f) as u8)
+    }
+    ///Bits 24:28 - 14 conversion in regular sequence
+    #[inline(always)]
+    pub fn sq14(&self) -> SQ_R {
+        SQ_R::new(((self.bits >> 24) & 0x1f) as u8)
+    }
+}
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("SQR3")
+            .field("sq10", &self.sq10())
+            .field("sq11", &self.sq11())
+            .field("sq12", &self.sq12())
+            .field("sq13", &self.sq13())
+            .field("sq14", &self.sq14())
+            .finish()
+    }
+}
+impl W {
+    ///(10-14) conversion in regular sequence
+    ///
+    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `SQ10` field.</div>
+    #[inline(always)]
+    pub fn sq(&mut self, n: u8) -> SQ_W<SQR3rs> {
+        #[allow(clippy::no_effect)]
+        [(); 5][n as usize];
+        SQ_W::new(self, n * 6)
+    }
+    ///Bits 0:4 - 10 conversion in regular sequence
+    #[inline(always)]
+    pub fn sq10(&mut self) -> SQ_W<SQR3rs> {
+        SQ_W::new(self, 0)
+    }
+    ///Bits 6:10 - 11 conversion in regular sequence
+    #[inline(always)]
+    pub fn sq11(&mut self) -> SQ_W<SQR3rs> {
+        SQ_W::new(self, 6)
+    }
+    ///Bits 12:16 - 12 conversion in regular sequence
+    #[inline(always)]
+    pub fn sq12(&mut self) -> SQ_W<SQR3rs> {
+        SQ_W::new(self, 12)
+    }
+    ///Bits 18:22 - 13 conversion in regular sequence
+    #[inline(always)]
+    pub fn sq13(&mut self) -> SQ_W<SQR3rs> {
+        SQ_W::new(self, 18)
+    }
+    ///Bits 24:28 - 14 conversion in regular sequence
+    #[inline(always)]
+    pub fn sq14(&mut self) -> SQ_W<SQR3rs> {
+        SQ_W::new(self, 24)
+    }
+}
+/**ADC regular sequence register 3
+
+You can [`read`](crate::Reg::read) this register and get [`sqr3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sqr3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
+
+See register [structure](https://stm32-rs.github.io/stm32-rs/STM32U535.html#ADC1:SQR3)*/
+pub struct SQR3rs;
+impl crate::RegisterSpec for SQR3rs {
+    type Ux = u32;
+}
+///`read()` method returns [`sqr3::R`](R) reader structure
+impl crate::Readable for SQR3rs {}
+///`write(|w| ..)` method takes [`sqr3::W`](W) writer structure
+impl crate::Writable for SQR3rs {
+    type Safety = crate::Unsafe;
+}
+///`reset()` method sets SQR3 to value 0
+impl crate::Resettable for SQR3rs {}

### external/vendor/stm32u5/src/stm32u535/adc1/sqr4.rs
@@ -0,0 +1,81 @@
+///Register `SQR4` reader
+pub type R = crate::R<SQR4rs>;
+///Register `SQR4` writer
+pub type W = crate::W<SQR4rs>;
+///Field `SQ(15-16)` reader - %s conversion in regular sequence
+pub type SQ_R = crate::FieldReader;
+///Field `SQ(15-16)` writer - %s conversion in regular sequence
+pub type SQ_W<'a, REG> = crate::FieldWriter<'a, REG, 5, u8, crate::Safe>;
+impl R {
+    ///(15-16) conversion in regular sequence
+    ///
+    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `SQ15` field.</div>
+    #[inline(always)]
+    pub fn sq(&self, n: u8) -> SQ_R {
+        #[allow(clippy::no_effect)]
+        [(); 2][n as usize];
+        SQ_R::new(((self.bits >> (n * 6)) & 0x1f) as u8)
+    }
+    ///Iterator for array of:
+    ///(15-16) conversion in regular sequence
+    #[inline(always)]
+    pub fn sq_iter(&self) -> impl Iterator<Item = SQ_R> + '_ {
+        (0..2).map(move |n| SQ_R::new(((self.bits >> (n * 6)) & 0x1f) as u8))
+    }
+    ///Bits 0:4 - 15 conversion in regular sequence
+    #[inline(always)]
+    pub fn sq15(&self) -> SQ_R {
+        SQ_R::new((self.bits & 0x1f) as u8)
+    }
+    ///Bits 6:10 - 16 conversion in regular sequence
+    #[inline(always)]
+    pub fn sq16(&self) -> SQ_R {
+        SQ_R::new(((self.bits >> 6) & 0x1f) as u8)
+    }
+}
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("SQR4")
+            .field("sq15", &self.sq15())
+            .field("sq16", &self.sq16())
+            .finish()
+    }
+}
+impl W {
+    ///(15-16) conversion in regular sequence
+    ///
+    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `SQ15` field.</div>
+    #[inline(always)]
+    pub fn sq(&mut self, n: u8) -> SQ_W<SQR4rs> {
+        #[allow(clippy::no_effect)]
+        [(); 2][n as usize];
+        SQ_W::new(self, n * 6)
+    }
+    ///Bits 0:4 - 15 conversion in regular sequence
+    #[inline(always)]
+    pub fn sq15(&mut self) -> SQ_W<SQR4rs> {
+        SQ_W::new(self, 0)
+    }
+    ///Bits 6:10 - 16 conversion in regular sequence
+    #[inline(always)]
+    pub fn sq16(&mut self) -> SQ_W<SQR4rs> {
+        SQ_W::new(self, 6)
+    }
+}
+/**ADC regular sequence register 4
+
+You can [`read`](crate::Reg::read) this register and get [`sqr4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sqr4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
+
+See register [structure](https://stm32-rs.github.io/stm32-rs/STM32U535.html#ADC1:SQR4)*/
+pub struct SQR4rs;
+impl crate::RegisterSpec for SQR4rs {
+    type Ux = u32;
+}
+///`read()` method returns [`sqr4::R`](R) reader structure
+impl crate::Readable for SQR4rs {}
+///`write(|w| ..)` method takes [`sqr4::W`](W) writer structure
+impl crate::Writable for SQR4rs {
+    type Safety = crate::Unsafe;
+}
+///`reset()` method sets SQR4 to value 0
+impl crate::Resettable for SQR4rs {}

### external/vendor/stm32u5/src/stm32u535/adc12_common.rs
@@ -0,0 +1,72 @@
+#[repr(C)]
+#[derive(Debug)]
+///Register block
+pub struct RegisterBlock {
+    csr: CSR,
+    _reserved1: [u8; 0x04],
+    ccr: CCR,
+    cdr: CDR,
+    cdr2: CDR2,
+}
+impl RegisterBlock {
+    ///0x00 - ADC common status register
+    #[inline(always)]
+    pub const fn csr(&self) -> &CSR {
+        &self.csr
+    }
+    ///0x08 - ADC_CCR system control register
+    #[inline(always)]
+    pub const fn ccr(&self) -> &CCR {
+        &self.ccr
+    }
+    ///0x0c - ADC common regular data register for dual mode
+    #[inline(always)]
+    pub const fn cdr(&self) -> &CDR {
+        &self.cdr
+    }
+    ///0x10 - ADC common regular data register for 32-bit dual mode
+    #[inline(always)]
+    pub const fn cdr2(&self) -> &CDR2 {
+        &self.cdr2
+    }
+}
+/**CSR (r) register accessor: ADC common status register
+
+You can [`read`](crate::Reg::read) this register and get [`csr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
+
+See register [structure](https://stm32-rs.github.io/stm32-rs/STM32U535.html#ADC12_Common:CSR)
+
+For information about available fields see [`mod@csr`] module*/
+pub type CSR = crate::Reg<csr::CSRrs>;
+///ADC common status register
+pub mod csr;
+/**CCR (rw) register accessor: ADC_CCR system control register
+
+You can [`read`](crate::Reg::read) this register and get [`ccr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
+
+See register [structure](https://stm32-rs.github.io/stm32-rs/STM32U535.html#ADC12_Common:CCR)
+
+For information about available fields see [`mod@ccr`] module*/
+pub type CCR = crate::Reg<ccr::CCRrs>;
+///ADC_CCR system control register
+pub mod ccr;
+/**CDR (r) register accessor: ADC common regular data register for dual mode
+
+You can [`read`](crate::Reg::read) this register and get [`cdr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
+
+See register [structure](https://stm32-rs.github.io/stm32-rs/STM32U535.html#ADC12_Common:CDR)
+
+For information about available fields see [`mod@cdr`] module*/
+pub type CDR = crate::Reg<cdr::CDRrs>;
+///ADC common regular data register for dual mode
+pub mod cdr;
+/**CDR2 (r) register accessor: ADC common regular data register for 32-bit dual mode
+
+You can [`read`](crate::Reg::read) this register and get [`cdr2::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
+
+See register [structure](https://stm32-rs.github.io/stm32-rs/STM32U535.html#ADC12_Common:CDR2)
+
+For information about available fields see [`mod@cdr2`] module*/
+pub type CDR2 = crate::Reg<cdr2::CDR2rs>;
+///ADC common regular data register for 32-bit dual mode
+pub mod cdr2;

### external/vendor/stm32u5/src/stm32u535/adc12_common/ccr.rs
@@ -0,0 +1,436 @@
+///Register `CCR` reader
+pub type R = crate::R<CCRrs>;
+///Register `CCR` writer
+pub type W = crate::W<CCRrs>;
+/**ADC prescaler These bits are set and cleared by software to select the frequency of the ADC clock. The clock is common to all ADCs. Others: Reserved, must not be used Note: The software is allowed to write this bit only when the ADCs are disabled (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0).
+
+Value on reset: 0*/
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+#[repr(u8)]
+pub enum PRESC {
+    ///0: Input ADC clock not divided
+    Div1 = 0,
+    ///1: Input ADC clock divided by 2
+    Div2 = 1,
+    ///2: Input ADC clock divided by 4
+    Div4 = 2,
+    ///3: Input ADC clock divided by 6
+    Div6 = 3,
+    ///4: Input ADC clock divided by 8
+    Div8 = 4,
+    ///5: Input ADC clock divided by 10
+    Div10 = 5,
+    ///6: Input ADC clock divided by 12
+    Div12 = 6,
+    ///7: Input ADC clock divided by 16
+    Div16 = 7,
+    ///8: Input ADC clock divided by 32
+    Div32 = 8,
+    ///9: Input ADC clock divided by 64
+    Div64 = 9,
+    ///10: Input ADC clock divided by 128
+    Div128 = 10,
+    ///11: Input ADC clock divided by 256
+    Div256 = 11,
+}
+impl From<PRESC> for u8 {
+    #[inline(always)]
+    fn from(variant: PRESC) -> Self {
+        variant as _
+    }
+}
+impl crate::FieldSpec for PRESC {
+    type Ux = u8;
+}
+impl crate::IsEnum for PRESC {}
+///Field `PRESC` reader - ADC prescaler These bits are set and cleared by software to select the frequency of the ADC clock. The clock is common to all ADCs. Others: Reserved, must not be used Note: The software is allowed to write this bit only when the ADCs are disabled (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0).
+pub type PRESC_R = crate::FieldReader<PRESC>;
+impl PRESC_R {
+    ///Get enumerated values variant
+    #[inline(always)]
+    pub const fn variant(&self) -> Option<PRESC> {
+        match self.bits {
+            0 => Some(PRESC::Div1),
+            1 => Some(PRESC::Div2),
+            2 => Some(PRESC::Div4),
+            3 => Some(PRESC::Div6),
+            4 => Some(PRESC::Div8),
+            5 => Some(PRESC::Div10),
+            6 => Some(PRESC::Div12),
+            7 => Some(PRESC::Div16),
+            8 => Some(PRESC::Div32),
+            9 => Some(PRESC::Div64),
+            10 => Some(PRESC::Div128),
+            11 => Some(PRESC::Div256),
+            _ => None,
+        }
+    }
+    ///Input ADC clock not divided
+    #[inline(always)]
+    pub fn is_div1(&self) -> bool {
+        *self == PRESC::Div1
+    }
+    ///Input ADC clock divided by 2
+    #[inline(always)]
+    pub fn is_div2(&self) -> bool {
+        *self == PRESC::Div2
+    }
+    ///Input ADC clock divided by 4
+    #[inline(always)]
+    pub fn is_div4(&self) -> bool {
+        *self == PRESC::Div4
+    }
+    ///Input ADC clock divided by 6
+    #[inline(always)]
+    pub fn is_div6(&self) -> bool {
+        *self == PRESC::Div6
+    }
+    ///Input ADC clock divided by 8
+    #[inline(always)]
+    pub fn is_div8(&self) -> bool {
+        *self == PRESC::Div8
+    }
+    ///Input ADC clock divided by 10
+    #[inline(always)]
+    pub fn is_div10(&self) -> bool {
+        *self == PRESC::Div10
+    }
+    ///Input ADC clock divided by 12
+    #[inline(always)]
+    pub fn is_div12(&self) -> bool {
+        *self == PRESC::Div12
+    }
+    ///Input ADC clock divided by 16
+    #[inline(always)]
+    pub fn is_div16(&self) -> bool {
+        *self == PRESC::Div16
+    }
+    ///Input ADC clock divided by 32
+    #[inline(always)]
+    pub fn is_div32(&self) -> bool {
+        *self == PRESC::Div32
+    }
+    ///Input ADC clock divided by 64
+    #[inline(always)]
+    pub fn is_div64(&self) -> bool {
+        *self == PRESC::Div64
+    }
+    ///Input ADC clock divided by 128
+    #[inline(always)]
+    pub fn is_div128(&self) -> bool {
+        *self == PRESC::Div128
+    }
+    ///Input ADC clock divided by 256
+    #[inline(always)]
+    pub fn is_div256(&self) -> bool {
+        *self == PRESC::Div256
+    }
+}
+///Field `PRESC` writer - ADC prescaler These bits are set and cleared by software to select the frequency of the ADC clock. The clock is common to all ADCs. Others: Reserved, must not be used Note: The software is allowed to write this bit only when the ADCs are disabled (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0).
+pub type PRESC_W<'a, REG> = crate::FieldWriter<'a, REG, 4, PRESC>;
+impl<'a, REG> PRESC_W<'a, REG>
+where
+    REG: crate::Writable + crate::RegisterSpec,
+    REG::Ux: From<u8>,
+{
+    ///Input ADC clock not divided
+    #[inline(always)]
+    pub fn div1(self) -> &'a mut crate::W<REG> {
+        self.variant(PRESC::Div1)
+    }
+    ///Input ADC clock divided by 2
+    #[inline(always)]
+    pub fn div2(self) -> &'a mut crate::W<REG> {
+        self.variant(PRESC::Div2)
+    }
+    ///Input ADC clock divided by 4
+    #[inline(always)]
+    pub fn div4(self) -> &'a mut crate::W<REG> {
+        self.variant(PRESC::Div4)
+    }
+    ///Input ADC clock divided by 6
+    #[inline(always)]
+    pub fn div6(self) -> &'a mut crate::W<REG> {
+        self.variant(PRESC::Div6)
+    }
+    ///Input ADC clock divided by 8
+    #[inline(always)]
+    pub fn div8(self) -> &'a mut crate::W<REG> {
+        self.variant(PRESC::Div8)
+    }
+    ///Input ADC clock divided by 10
+    #[inline(always)]
+    pub fn div10(self) -> &'a mut crate::W<REG> {
+        self.variant(PRESC::Div10)
+    }
+    ///Input ADC clock divided by 12
+    #[inline(always)]
+    pub fn div12(self) -> &'a mut crate::W<REG> {
+        self.variant(PRESC::Div12)
+    }
+    ///Input ADC clock divided by 16
+    #[inline(always)]
+    pub fn div16(self) -> &'a mut crate::W<REG> {
+        self.variant(PRESC::Div16)
+    }
+    ///Input ADC clock divided by 32
+    #[inline(always)]
+    pub fn div32(self) -> &'a mut crate::W<REG> {
+        self.variant(PRESC::Div32)
+    }
+    ///Input ADC clock divided by 64
+    #[inline(always)]
+    pub fn div64(self) -> &'a mut crate::W<REG> {
+        self.variant(PRESC::Div64)
+    }
+    ///Input ADC clock divided by 128
+    #[inline(always)]
+    pub fn div128(self) -> &'a mut crate::W<REG> {
+        self.variant(PRESC::Div128)
+    }
+    ///Input ADC clock divided by 256
+    #[inline(always)]
+    pub fn div256(self) -> &'a mut crate::W<REG> {
+        self.variant(PRESC::Div256)
+    }
+}
+/**VREFINT enable This bit is set and cleared by software to enable/disable the VREFINT buffer. Note: The software is allowed to write this bit only when the ADCs are disabled (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0).
+
+Value on reset: 0*/
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub enum VREFEN {
+    ///0: VREFINT channel disabled
+    Disabled = 0,
+    ///1: VREFINT channel enabled
+    Enabled = 1,
+}
+impl From<VREFEN> for bool {
+    #[inline(always)]
+    fn from(variant: VREFEN) -> Self {
+        variant as u8 != 0
+    }
+}
+///Field `VREFEN` reader - VREFINT enable This bit is set and cleared by software to enable/disable the VREFINT buffer. Note: The software is allowed to write this bit only when the ADCs are disabled (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0).
+pub type VREFEN_R = crate::BitReader<VREFEN>;
+impl VREFEN_R {
+    ///Get enumerated values variant
+    #[inline(always)]
+    pub const fn variant(&self) -> VREFEN {
+        match self.bits {
+            false => VREFEN::Disabled,
+            true => VREFEN::Enabled,
+        }
+    }
+    ///VREFINT channel disabled
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == VREFEN::Disabled
+    }
+    ///VREFINT channel enabled
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == VREFEN::Enabled
+    }
+}
+///Field `VREFEN` writer - VREFINT enable This bit is set and cleared by software to enable/disable the VREFINT buffer. Note: The software is allowed to write this bit only when the ADCs are disabled (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0).
+pub type VREFEN_W<'a, REG> = crate::BitWriter<'a, REG, VREFEN>;
+impl<'a, REG> VREFEN_W<'a, REG>
+where
+    REG: crate::Writable + crate::RegisterSpec,
+{
+    ///VREFINT channel disabled
+    #[inline(always)]
+    pub fn disabled(self) -> &'a mut crate::W<REG> {
+        self.variant(VREFEN::Disabled)
+    }
+    ///VREFINT channel enabled
+    #[inline(always)]
+    pub fn enabled(self) -> &'a mut crate::W<REG> {
+        self.variant(VREFEN::Enabled)
+    }
+}
+/**Temperature sensor voltage selection This bit is set and cleared by software to control the temperature sensor channel. Note: The software is allowed to write this bit only when the ADCs are disabled (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0).
+
+Value on reset: 0*/
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub enum VSENSESEL {
+    ///0: Temperature sensor channel disabled
+    Disabled = 0,
+    ///1: Temperature sensor channel enabled
+    Enabled = 1,
+}
+impl From<VSENSESEL> for bool {
+    #[inline(always)]
+    fn from(variant: VSENSESEL) -> Self {
+        variant as u8 != 0
+    }
+}
+///Field `VSENSESEL` reader - Temperature sensor voltage selection This bit is set and cleared by software to control the temperature sensor channel. Note: The software is allowed to write this bit only when the ADCs are disabled (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0).
+pub type VSENSESEL_R = crate::BitReader<VSENSESEL>;
+impl VSENSESEL_R {
+    ///Get enumerated values variant
+    #[inline(always)]
+    pub const fn variant(&self) -> VSENSESEL {
+        match self.bits {
+            false => VSENSESEL::Disabled,
+            true => VSENSESEL::Enabled,
+        }
+    }
+    ///Temperature sensor channel disabled
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == VSENSESEL::Disabled
+    }
+    ///Temperature sensor channel enabled
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == VSENSESEL::Enabled
+    }
+}
+///Field `VSENSESEL` writer - Temperature sensor voltage selection This bit is set and cleared by software to control the temperature sensor channel. Note: The software is allowed to write this bit only when the ADCs are disabled (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0).
+pub type VSENSESEL_W<'a, REG> = crate::BitWriter<'a, REG, VSENSESEL>;
+impl<'a, REG> VSENSESEL_W<'a, REG>
+where
+    REG: crate::Writable + crate::RegisterSpec,
+{
+    ///Temperature sensor channel disabled
+    #[inline(always)]
+    pub fn disabled(self) -> &'a mut crate::W<REG> {
+        self.variant(VSENSESEL::Disabled)
+    }
+    ///Temperature sensor channel enabled
+    #[inline(always)]
+    pub fn enabled(self) -> &'a mut crate::W<REG> {
+        self.variant(VSENSESEL::Enabled)
+    }
+}
+/**VBAT enable This bit is set and cleared by software to control the VBAT channel. Note: The software is allowed to write this bit only when the ADCs are disabled (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0).
+
+Value on reset: 0*/
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub enum VBATEN {
+    ///0: VBAT channel disabled
+    Disabled = 0,
+    ///1: VBAT channel enabled
+    Enabled = 1,
+}
+impl From<VBATEN> for bool {
+    #[inline(always)]
+    fn from(variant: VBATEN) -> Self {
+        variant as u8 != 0
+    }
+}
+///Field `VBATEN` reader - VBAT enable This bit is set and cleared by software to control the VBAT channel. Note: The software is allowed to write this bit only when the ADCs are disabled (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0).
+pub type VBATEN_R = crate::BitReader<VBATEN>;
+impl VBATEN_R {
+    ///Get enumerated values variant
+    #[inline(always)]
+    pub const fn variant(&self) -> VBATEN {
+        match self.bits {
+            false => VBATEN::Disabled,
+            true => VBATEN::Enabled,
+        }
+    }
+    ///VBAT channel disabled
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == VBATEN::Disabled
+    }
+    ///VBAT channel enabled
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == VBATEN::Enabled
+    }
+}
+///Field `VBATEN` writer - VBAT enable This bit is set and cleared by software to control the VBAT channel. Note: The software is allowed to write this bit only when the ADCs are disabled (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0).
+pub type VBATEN_W<'a, REG> = crate::BitWriter<'a, REG, VBATEN>;
+impl<'a, REG> VBATEN_W<'a, REG>
+where
+    REG: crate::Writable + crate::RegisterSpec,
+{
+    ///VBAT channel disabled
+    #[inline(always)]
+    pub fn disabled(self) -> &'a mut crate::W<REG> {
+        self.variant(VBATEN::Disabled)
+    }
+    ///VBAT channel enabled
+    #[inline(always)]
+    pub fn enabled(self) -> &'a mut crate::W<REG> {
+        self.variant(VBATEN::Enabled)
+    }
+}
+impl R {
+    ///Bits 18:21 - ADC prescaler These bits are set and cleared by software to select the frequency of the ADC clock. The clock is common to all ADCs. Others: Reserved, must not be used Note: The software is allowed to write this bit only when the ADCs are disabled (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0).
+    #[inline(always)]
+    pub fn presc(&self) -> PRESC_R {
+        PRESC_R::new(((self.bits >> 18) & 0x0f) as u8)
+    }
+    ///Bit 22 - VREFINT enable This bit is set and cleared by software to enable/disable the VREFINT buffer. Note: The software is allowed to write this bit only when the ADCs are disabled (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0).
+    #[inline(always)]
+    pub fn vrefen(&self) -> VREFEN_R {
+        VREFEN_R::new(((self.bits >> 22) & 1) != 0)
+    }
+    ///Bit 23 - Temperature sensor voltage selection This bit is set and cleared by software to control the temperature sensor channel. Note: The software is allowed to write this bit only when the ADCs are disabled (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0).
+    #[inline(always)]
+    pub fn vsensesel(&self) -> VSENSESEL_R {
+        VSENSESEL_R::new(((self.bits >> 23) & 1) != 0)
+    }
+    ///Bit 24 - VBAT enable This bit is set and cleared by software to control the VBAT channel. Note: The software is allowed to write this bit only when the ADCs are disabled (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0).
+    #[inline(always)]
+    pub fn vbaten(&self) -> VBATEN_R {
+        VBATEN_R::new(((self.bits >> 24) & 1) != 0)
+    }
+}
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CCR")
+            .field("presc", &self.presc())
+            .field("vrefen", &self.vrefen())
+            .field("vsensesel", &self.vsensesel())
+            .field("vbaten", &self.vbaten())
+            .finish()
+    }
+}
+impl W {
+    ///Bits 18:21 - ADC prescaler These bits are set and cleared by software to select the frequency of the ADC clock. The clock is common to all ADCs. Others: Reserved, must not be used Note: The software is allowed to write this bit only when the ADCs are disabled (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0).
+    #[inline(always)]
+    pub fn presc(&mut self) -> PRESC_W<CCRrs> {
+        PRESC_W::new(self, 18)
+    }
+    ///Bit 22 - VREFINT enable This bit is set and cleared by software to enable/disable the VREFINT buffer. Note: The software is allowed to write this bit only when the ADCs are disabled (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0).
+    #[inline(always)]
+    pub fn vrefen(&mut self) -> VREFEN_W<CCRrs> {
+        VREFEN_W::new(self, 22)
+    }
+    ///Bit 23 - Temperature sensor voltage selection This bit is set and cleared by software to control the temperature sensor channel. Note: The software is allowed to write this bit only when the ADCs are disabled (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0).
+    #[inline(always)]
+    pub fn vsensesel(&mut self) -> VSENSESEL_W<CCRrs> {
+        VSENSESEL_W::new(self, 23)
+    }
+    ///Bit 24 - VBAT enable This bit is set and cleared by software to control the VBAT channel. Note: The software is allowed to write this bit only when the ADCs are disabled (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0).
+    #[inline(always)]
+    pub fn vbaten(&mut self) -> VBATEN_W<CCRrs> {
+        VBATEN_W::new(self, 24)
+    }
+}
+/**ADC_CCR system control register
+
+You can [`read`](crate::Reg::read) this register and get [`ccr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
+
+See register [structure](https://stm32-rs.github.io/stm32-rs/STM32U535.html#ADC12_Common:CCR)*/
+pub struct CCRrs;
+impl crate::RegisterSpec for CCRrs {
+    type Ux = u32;
+}
+///`read()` method returns [`ccr::R`](R) reader structure
+impl crate::Readable for CCRrs {}
+///`write(|w| ..)` method takes [`ccr::W`](W) writer structure
+impl crate::Writable for CCRrs {
+    type Safety = crate::Unsafe;
+}
+///`reset()` method sets CCR to value 0
+impl crate::Resettable for CCRrs {}

### external/vendor/stm32u5/src/stm32u535/adc12_common/cdr.rs
@@ -0,0 +1,39 @@
+///Register `CDR` reader
+pub type R = crate::R<CDRrs>;
+///Field `RDATA_MST` reader - Regular data of the master ADC. In dual mode, these bits contain the regular data of the master ADC. Refer to . The data alignment is applied as described in offset (ADC_DR, ADC_JDRy, OFFSETy, OFFSETy_CH, OVSS, LSHIFT, USAT, SSAT)) In DAMDF\[1:0\] = 11 mode, bits 15:8 contains SLV_ADC_DR\[7:0\], bits 7:0 contains MST_ADC_DR\[7:0\].
+pub type RDATA_MST_R = crate::FieldReader<u16>;
+///Field `RDATA_SLV` reader - Regular data of the slave ADC In dual mode, these bits contain the regular data of the slave ADC. Refer to Dual ADC modes. The data alignment is applied as described in offset (ADC_DR, ADC_JDRy, OFFSETy, OFFSETy_CH, OVSS, LSHIFT, USAT, SSAT))
+pub type RDATA_SLV_R = crate::FieldReader<u16>;
+impl R {
+    ///Bits 0:15 - Regular data of the master ADC. In dual mode, these bits contain the regular data of the master ADC. Refer to . The data alignment is applied as described in offset (ADC_DR, ADC_JDRy, OFFSETy, OFFSETy_CH, OVSS, LSHIFT, USAT, SSAT)) In DAMDF\[1:0\] = 11 mode, bits 15:8 contains SLV_ADC_DR\[7:0\], bits 7:0 contains MST_ADC_DR\[7:0\].
+    #[inline(always)]
+    pub fn rdata_mst(&self) -> RDATA_MST_R {
+        RDATA_MST_R::new((self.bits & 0xffff) as u16)
+    }
+    ///Bits 16:31 - Regular data of the slave ADC In dual mode, these bits contain the regular data of the slave ADC. Refer to Dual ADC modes. The data alignment is applied as described in offset (ADC_DR, ADC_JDRy, OFFSETy, OFFSETy_CH, OVSS, LSHIFT, USAT, SSAT))
+    #[inline(always)]
+    pub fn rdata_slv(&self) -> RDATA_SLV_R {
+        RDATA_SLV_R::new(((self.bits >> 16) & 0xffff) as u16)
+    }
+}
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CDR")
+            .field("rdata_mst", &self.rdata_mst())
+            .field("rdata_slv", &self.rdata_slv())
+            .finish()
+    }
+}
+/**ADC common regular data register for dual mode
+
+You can [`read`](crate::Reg::read) this register and get [`cdr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
+
+See register [structure](https://stm32-rs.github.io/stm32-rs/STM32U535.html#ADC12_Common:CDR)*/
+pub struct CDRrs;
+impl crate::RegisterSpec for CDRrs {
+    type Ux = u32;
+}
+///`read()` method returns [`cdr::R`](R) reader structure
+impl crate::Readable for CDRrs {}
+///`reset()` method sets CDR to value 0
+impl crate::Resettable for CDRrs {}

### external/vendor/stm32u5/src/stm32u535/adc12_common/cdr2.rs
@@ -0,0 +1,31 @@
+///Register `CDR2` reader
+pub type R = crate::R<CDR2rs>;
+///Field `RDATA_ALT` reader - Regular data of the master/slave alternated ADCs In dual mode, these bits alternatively contains the regular 32-bit data of the master and the slave ADC. Refer to . The data alignment is applied as described in (ADC_DR, ADC_JDRy, OFFSETy, OFFSETy_CH, OVSS, LSHIFT, USAT, SSAT).
+pub type RDATA_ALT_R = crate::FieldReader<u32>;
+impl R {
+    ///Bits 0:31 - Regular data of the master/slave alternated ADCs In dual mode, these bits alternatively contains the regular 32-bit data of the master and the slave ADC. Refer to . The data alignment is applied as described in (ADC_DR, ADC_JDRy, OFFSETy, OFFSETy_CH, OVSS, LSHIFT, USAT, SSAT).
+    #[inline(always)]
+    pub fn rdata_alt(&self) -> RDATA_ALT_R {
+        RDATA_ALT_R::new(self.bits)
+    }
+}
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CDR2")
+            .field("rdata_alt", &self.rdata_alt())
+            .finish()
+    }
+}
+/**ADC common regular data register for 32-bit dual mode
+
+You can [`read`](crate::Reg::read) this register and get [`cdr2::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
+
+See register [structure](https://stm32-rs.github.io/stm32-rs/STM32U535.html#ADC12_Common:CDR2)*/
+pub struct CDR2rs;
+impl crate::RegisterSpec for CDR2rs {
+    type Ux = u32;
+}
+///`read()` method returns [`cdr2::R`](R) reader structure
+impl crate::Readable for CDR2rs {}
+///`reset()` method sets CDR2 to value 0
+impl crate::Resettable for CDR2rs {}

### external/vendor/stm32u5/src/stm32u535/adc12_common/csr.rs
@@ -0,0 +1,199 @@
+///Register `CSR` reader
+pub type R = crate::R<CSRrs>;
+///Field `ADRDY_MST` reader - Master ADC ready This bit is a copy of the ADRDY bit in the corresponding ADC_ISR register.
+pub type ADRDY_MST_R = crate::BitReader;
+///Field `EOSMP_MST` reader - End of Sampling phase flag of the master ADC This bit is a copy of the EOSMP bit in the corresponding ADC_ISR register.
+pub type EOSMP_MST_R = crate::BitReader;
+///Field `EOC_MST` reader - End of regular conversion of the master ADC This bit is a copy of the EOC bit in the corresponding ADC_ISR register.
+pub type EOC_MST_R = crate::BitReader;
+///Field `EOS_MST` reader - End of regular sequence flag of the master ADC This bit is a copy of the EOS bit in the corresponding ADC_ISR register.
+pub type EOS_MST_R = crate::BitReader;
+///Field `OVR_MST` reader - Overrun flag of the master ADC This bit is a copy of the OVR bit in the corresponding ADC_ISR register.
+pub type OVR_MST_R = crate::BitReader;
+///Field `JEOC_MST` reader - End of injected conversion flag of the master ADC This bit is a copy of the JEOC bit in the corresponding ADC_ISR register.
+pub type JEOC_MST_R = crate::BitReader;
+///Field `JEOS_MST` reader - End of injected sequence flag of the master ADC This bit is a copy of the JEOS bit in the corresponding ADC_ISR register.
+pub type JEOS_MST_R = crate::BitReader;
+///Field `AWD1_MST` reader - Analog watchdog 1 flag of the master ADC This bit is a copy of the AWD1 bit in the corresponding ADC_ISR register.
+pub type AWD1_MST_R = crate::BitReader;
+///Field `AWD2_MST` reader - Analog watchdog 2 flag of the master ADC This bit is a copy of the AWD2 bit in the corresponding ADC_ISR register.
+pub type AWD2_MST_R = crate::BitReader;
+///Field `AWD3_MST` reader - Analog watchdog 3 flag of the master ADC This bit is a copy of the AWD3 bit in the corresponding ADC_ISR register.
+pub type AWD3_MST_R = crate::BitReader;
+///Field `LDORDY_MST` reader - ADC voltage regulator ready flag of the master ADC This bit is a copy of the LDORDY bit of the corresponding ADC_ISR register.
+pub type LDORDY_MST_R = crate::BitReader;
+///Field `ADRDY_SLV` reader - Slave ADC ready This bit is a copy of the ADRDY bit in the corresponding ADCx+1_ISR register.
+pub type ADRDY_SLV_R = crate::BitReader;
+///Field `EOSMP_SLV` reader - End of Sampling phase flag of the slave ADC This bit is a copy of the EOSMP2 bit in the corresponding ADCx+1_ISR register.
+pub type EOSMP_SLV_R = crate::BitReader;
+///Field `EOC_SLV` reader - End of regular conversion of the slave ADC This bit is a copy of the EOC bit in the corresponding ADCx+1_ISR register.
+pub type EOC_SLV_R = crate::BitReader;
+///Field `EOS_SLV` reader - End of regular sequence flag of the slave ADC This bit is a copy of the EOS bit in the corresponding ADCx+1_ISR register.
+pub type EOS_SLV_R = crate::BitReader;
+///Field `OVR_SLV` reader - Overrun flag of the slave ADC This bit is a copy of the OVR bit in the corresponding ADCx+1_ISR register.
+pub type OVR_SLV_R = crate::BitReader;
+///Field `JEOC_SLV` reader - End of injected conversion flag of the slave ADC This bit is a copy of the JEOC bit in the corresponding ADCx+1_ISR register.
+pub type JEOC_SLV_R = crate::BitReader;
+///Field `JEOS_SLV` reader - End of injected sequence flag of the slave ADC This bit is a copy of the JEOS bit in the corresponding ADCx+1_ISR register.
+pub type JEOS_SLV_R = crate::BitReader;
+///Field `AWD1_SLV` reader - Analog watchdog 1 flag of the slave ADC This bit is a copy of the AWD1 bit in the corresponding ADCx+1_ISR register.
+pub type AWD1_SLV_R = crate::BitReader;
+///Field `AWD2_SLV` reader - Analog watchdog 2 flag of the slave ADC This bit is a copy of the AWD2 bit in the corresponding ADCx+1_ISR register.
+pub type AWD2_SLV_R = crate::BitReader;
+///Field `AWD3_SLV` reader - Analog watchdog 3 flag of the slave ADC This bit is a copy of the AWD3 bit in the corresponding ADCx+1_ISR register.
+pub type AWD3_SLV_R = crate::BitReader;
+///Field `LDORDY_SLV` reader - ADC voltage regulator ready flag of the slave ADC This bit is a copy of the LDORDY bit of the corresponding ADCx+1_ISR register.
+pub type LDORDY_SLV_R = crate::BitReader;
+impl R {
+    ///Bit 0 - Master ADC ready This bit is a copy of the ADRDY bit in the corresponding ADC_ISR register.
+    #[inline(always)]
+    pub fn adrdy_mst(&self) -> ADRDY_MST_R {
+        ADRDY_MST_R::new((self.bits & 1) != 0)
+    }
+    ///Bit 1 - End of Sampling phase flag of the master ADC This bit is a copy of the EOSMP bit in the corresponding ADC_ISR register.
+    #[inline(always)]
+    pub fn eosmp_mst(&self) -> EOSMP_MST_R {
+        EOSMP_MST_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    ///Bit 2 - End of regular conversion of the master ADC This bit is a copy of the EOC bit in the corresponding ADC_ISR register.
+    #[inline(always)]
+    pub fn eoc_mst(&self) -> EOC_MST_R {
+        EOC_MST_R::new(((self.bits >> 2) & 1) != 0)
+    }
+    ///Bit 3 - End of regular sequence flag of the master ADC This bit is a copy of the EOS bit in the corresponding ADC_ISR register.
+    #[inline(always)]
+    pub fn eos_mst(&self) -> EOS_MST_R {
+        EOS_MST_R::new(((self.bits >> 3) & 1) != 0)
+    }
+    ///Bit 4 - Overrun flag of the master ADC This bit is a copy of the OVR bit in the corresponding ADC_ISR register.
+    #[inline(always)]
+    pub fn ovr_mst(&self) -> OVR_MST_R {
+        OVR_MST_R::new(((self.bits >> 4) & 1) != 0)
+    }
+    ///Bit 5 - End of injected conversion flag of the master ADC This bit is a copy of the JEOC bit in the corresponding ADC_ISR register.
+    #[inline(always)]
+    pub fn jeoc_mst(&self) -> JEOC_MST_R {
+        JEOC_MST_R::new(((self.bits >> 5) & 1) != 0)
+    }
+    ///Bit 6 - End of injected sequence flag of the master ADC This bit is a copy of the JEOS bit in the corresponding ADC_ISR register.
+    #[inline(always)]
+    pub fn jeos_mst(&self) -> JEOS_MST_R {
+        JEOS_MST_R::new(((self.bits >> 6) & 1) != 0)
+    }
+    ///Bit 7 - Analog watchdog 1 flag of the master ADC This bit is a copy of the AWD1 bit in the corresponding ADC_ISR register.
+    #[inline(always)]
+    pub fn awd1_mst(&self) -> AWD1_MST_R {
+        AWD1_MST_R::new(((self.bits >> 7) & 1) != 0)
+    }
+    ///Bit 8 - Analog watchdog 2 flag of the master ADC This bit is a copy of the AWD2 bit in the corresponding ADC_ISR register.
+    #[inline(always)]
+    pub fn awd2_mst(&self) -> AWD2_MST_R {
+        AWD2_MST_R::new(((self.bits >> 8) & 1) != 0)
+    }
+    ///Bit 9 - Analog watchdog 3 flag of the master ADC This bit is a copy of the AWD3 bit in the corresponding ADC_ISR register.
+    #[inline(always)]
+    pub fn awd3_mst(&self) -> AWD3_MST_R {
+        AWD3_MST_R::new(((self.bits >> 9) & 1) != 0)
+    }
+    ///Bit 12 - ADC voltage regulator ready flag of the master ADC This bit is a copy of the LDORDY bit of the corresponding ADC_ISR register.
+    #[inline(always)]
+    pub fn ldordy_mst(&self) -> LDORDY_MST_R {
+        LDORDY_MST_R::new(((self.bits >> 12) & 1) != 0)
+    }
+    ///Bit 16 - Slave ADC ready This bit is a copy of the ADRDY bit in the corresponding ADCx+1_ISR register.
+    #[inline(always)]
+    pub fn adrdy_slv(&self) -> ADRDY_SLV_R {
+        ADRDY_SLV_R::new(((self.bits >> 16) & 1) != 0)
+    }
+    ///Bit 17 - End of Sampling phase flag of the slave ADC This bit is a copy of the EOSMP2 bit in the corresponding ADCx+1_ISR register.
+    #[inline(always)]
+    pub fn eosmp_slv(&self) -> EOSMP_SLV_R {
+        EOSMP_SLV_R::new(((self.bits >> 17) & 1) != 0)
+    }
+    ///Bit 18 - End of regular conversion of the slave ADC This bit is a copy of the EOC bit in the corresponding ADCx+1_ISR register.
+    #[inline(always)]
+    pub fn eoc_slv(&self) -> EOC_SLV_R {
+        EOC_SLV_R::new(((self.bits >> 18) & 1) != 0)
+    }
+    ///Bit 19 - End of regular sequence flag of the slave ADC This bit is a copy of the EOS bit in the corresponding ADCx+1_ISR register.
+    #[inline(always)]
+    pub fn eos_slv(&self) -> EOS_SLV_R {
+        EOS_SLV_R::new(((self.bits >> 19) & 1) != 0)
+    }
+    ///Bit 20 - Overrun flag of the slave ADC This bit is a copy of the OVR bit in the corresponding ADCx+1_ISR register.
+    #[inline(always)]
+    pub fn ovr_slv(&self) -> OVR_SLV_R {
+        OVR_SLV_R::new(((self.bits >> 20) & 1) != 0)
+    }
+    ///Bit 21 - End of injected conversion flag of the slave ADC This bit is a copy of the JEOC bit in the corresponding ADCx+1_ISR register.
+    #[inline(always)]
+    pub fn jeoc_slv(&self) -> JEOC_SLV_R {
+        JEOC_SLV_R::new(((self.bits >> 21) & 1) != 0)
+    }
+    ///Bit 22 - End of injected sequence flag of the slave ADC This bit is a copy of the JEOS bit in the corresponding ADCx+1_ISR register.
+    #[inline(always)]
+    pub fn jeos_slv(&self) -> JEOS_SLV_R {
+        JEOS_SLV_R::new(((self.bits >> 22) & 1) != 0)
+    }
+    ///Bit 23 - Analog watchdog 1 flag of the slave ADC This bit is a copy of the AWD1 bit in the corresponding ADCx+1_ISR register.
+    #[inline(always)]
+    pub fn awd1_slv(&self) -> AWD1_SLV_R {
+        AWD1_SLV_R::new(((self.bits >> 23) & 1) != 0)
+    }
+    ///Bit 24 - Analog watchdog 2 flag of the slave ADC This bit is a copy of the AWD2 bit in the corresponding ADCx+1_ISR register.
+    #[inline(always)]
+    pub fn awd2_slv(&self) -> AWD2_SLV_R {
+        AWD2_SLV_R::new(((self.bits >> 24) & 1) != 0)
+    }
+    ///Bit 25 - Analog watchdog 3 flag of the slave ADC This bit is a copy of the AWD3 bit in the corresponding ADCx+1_ISR register.
+    #[inline(always)]
+    pub fn awd3_slv(&self) -> AWD3_SLV_R {
+        AWD3_SLV_R::new(((self.bits >> 25) & 1) != 0)
+    }
+    ///Bit 28 - ADC voltage regulator ready flag of the slave ADC This bit is a copy of the LDORDY bit of the corresponding ADCx+1_ISR register.
+    #[inline(always)]
+    pub fn ldordy_slv(&self) -> LDORDY_SLV_R {
+        LDORDY_SLV_R::new(((self.bits >> 28) & 1) != 0)
+    }
+}
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CSR")
+            .field("adrdy_mst", &self.adrdy_mst())
+            .field("eosmp_mst", &self.eosmp_mst())
+            .field("eoc_mst", &self.eoc_mst())
+            .field("eos_mst", &self.eos_mst())
+            .field("ovr_mst", &self.ovr_mst())
+            .field("jeoc_mst", &self.jeoc_mst())
+            .field("jeos_mst", &self.jeos_mst())
+            .field("awd1_mst", &self.awd1_mst())
+            .field("awd2_mst", &self.awd2_mst())
+            .field("awd3_mst", &self.awd3_mst())
+            .field("ldordy_mst", &self.ldordy_mst())
+            .field("adrdy_slv", &self.adrdy_slv())
+            .field("eosmp_slv", &self.eosmp_slv())
+            .field("eoc_slv", &self.eoc_slv())
+            .field("eos_slv", &self.eos_slv())
+            .field("ovr_slv", &self.ovr_slv())
+            .field("jeoc_slv", &self.jeoc_slv())
+            .field("jeos_slv", &self.jeos_slv())
+            .field("awd1_slv", &self.awd1_slv())
+            .field("awd2_slv", &self.awd2_slv())
+            .field("awd3_slv", &self.awd3_slv())
+            .field("ldordy_slv", &self.ldordy_slv())
+            .finish()
+    }
+}
+/**ADC common status register
+
+You can [`read`](crate::Reg::read) this register and get [`csr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
+
+See register [structure](https://stm32-rs.github.io/stm32-rs/STM32U535.html#ADC12_Common:CSR)*/
+pub struct CSRrs;
+impl crate::RegisterSpec for CSRrs {
+    type Ux = u32;
+}
+///`read()` method returns [`csr::R`](R) reader structure
+impl crate::Readable for CSRrs {}
+///`reset()` method sets CSR to value 0
+impl crate::Resettable for CSRrs {}

### external/vendor/stm32u5/src/stm32u535/adc4.rs
@@ -0,0 +1,300 @@
+#[repr(C)]
+#[derive(Debug)]
+///Register block
+pub struct RegisterBlock {
+    isr: ISR,
+    ier: IER,
+    cr: CR,
+    cfgr1: CFGR1,
+    cfgr2: CFGR2,
+    smpr: SMPR,
+    _reserved6: [u8; 0x08],
+    awd1tr: AWD1TR,
+    awd2tr: AWD2TR,
+    _reserved_8_chselr0: [u8; 0x04],
+    awd3tr: AWD3TR,
+    _reserved10: [u8; 0x10],
+    dr: DR,
+    pwrr: PWRR,
+    _reserved12: [u8; 0x58],
+    awd2cr: AWD2CR,
+    awd3cr: AWD3CR,
+    _reserved14: [u8; 0x0c],
+    calfact: CALFACT,
+    _reserved15: [u8; 0x18],
+    or: OR,
+    _reserved16: [u8; 0x0234],
+    ccr: CCR,
+}
+impl RegisterBlock {
+    ///0x00 - ADC interrupt and status register
+    #[inline(always)]
+    pub const fn isr(&self) -> &ISR {
+        &self.isr
+    }
+    ///0x04 - ADC interrupt enable register
+    #[inline(always)]
+    pub const fn ier(&self) -> &IER {
+        &self.ier
+    }
+    ///0x08 - ADC control register
+    #[inline(always)]
+    pub const fn cr(&self) -> &CR {
+        &self.cr
+    }
+    ///0x0c - ADC configuration register
+    #[inline(always)]
+    pub const fn cfgr1(&self) -> &CFGR1 {
+        &self.cfgr1
+    }
+    ///0x10 - ADC configuration register 2
+    #[inline(always)]
+    pub const fn cfgr2(&self) -> &CFGR2 {
+        &self.cfgr2
+    }
+    ///0x14 - ADC sample time register
+    #[inline(always)]
+    pub const fn smpr(&self) -> &SMPR {
+        &self.smpr
+    }
+    ///0x20 - ADC watchdog threshold register
+    #[inline(always)]
+    pub const fn awd1tr(&self) -> &AWD1TR {
+        &self.awd1tr
+    }
+    ///0x24 - ADC watchdog threshold register
+    #[inline(always)]
+    pub const fn awd2tr(&self) -> &AWD2TR {
+        &self.awd2tr
+    }
+    ///0x28 - ADC channel selection register \[alternate\]
+    #[inline(always)]
+    pub const fn chselr1(&self) -> &CHSELR1 {
+        unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(40).cast() }
+    }
+    ///0x28 - ADC channel selection register \[alternate\]
+    #[inline(always)]
+    pub const fn chselr0(&self) -> &CHSELR0 {
+        unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(40).cast() }
+    }
+    ///0x2c - ADC watchdog threshold register
+    #[inline(always)]
+    pub const fn awd3tr(&self) -> &AWD3TR {
+        &self.awd3tr
+    }
+    ///0x40 - ADC data register
+    #[inline(always)]
+    pub const fn dr(&self) -> &DR {
+        &self.dr
+    }
+    ///0x44 - ADC data register
+    #[inline(always)]
+    pub const fn pwrr(&self) -> &PWRR {
+        &self.pwrr
+    }
+    ///0xa0 - ADC Analog Watchdog 2 Configuration register
+    #[inline(always)]
+    pub const fn awd2cr(&self) -> &AWD2CR {
+        &self.awd2cr
+    }
+    ///0xa4 - ADC Analog Watchdog 3 Configuration register
+    #[inline(always)]
+    pub const fn awd3cr(&self) -> &AWD3CR {
+        &self.awd3cr
+    }
+    ///0xb4 - ADC Calibration factor
+    #[inline(always)]
+    pub const fn calfact(&self) -> &CALFACT {
+        &self.calfact
+    }
+    ///0xd0 - ADC option register
+    #[inline(always)]
+    pub const fn or(&self) -> &OR {
+        &self.or
+    }
+    ///0x308 - ADC common configuration register
+    #[inline(always)]
+    pub const fn ccr(&self) -> &CCR {
+        &self.ccr
+    }
+}
+/**ISR (rw) register accessor: ADC interrupt and status register
+
+You can [`read`](crate::Reg::read) this register and get [`isr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`isr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
+
+See register [structure](https://stm32-rs.github.io/stm32-rs/STM32U535.html#ADC4:ISR)
+
+For information about available fields see [`mod@isr`] module*/
+pub type ISR = crate::Reg<isr::ISRrs>;
+///ADC interrupt and status register
+pub mod isr;
+/**IER (rw) register accessor: ADC interrupt enable register
+
+You can [`read`](crate::Reg::read) this register and get [`ier::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ier::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
+
+See register [structure](https://stm32-rs.github.io/stm32-rs/STM32U535.html#ADC4:IER)
+
+For information about available fields see [`mod@ier`] module*/
+pub type IER = crate::Reg<ier::IERrs>;
+///ADC interrupt enable register
+pub mod ier;
+/**CR (rw) register accessor: ADC control register
+
+You can [`read`](crate::Reg::read) this register and get [`cr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
+
+See register [structure](https://stm32-rs.github.io/stm32-rs/STM32U535.html#ADC4:CR)
+
+For information about available fields see [`mod@cr`] module*/
+pub type CR = crate::Reg<cr::CRrs>;
+///ADC control register
+pub mod cr;
+/**CFGR1 (rw) register accessor: ADC configuration register
+
+You can [`read`](crate::Reg::read) this register and get [`cfgr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfgr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
+
+See register [structure](https://stm32-rs.github.io/stm32-rs/STM32U535.html#ADC4:CFGR1)
+
+For information about available fields see [`mod@cfgr1`] module*/
+pub type CFGR1 = crate::Reg<cfgr1::CFGR1rs>;
+///ADC configuration register
+pub mod cfgr1;
+/**CFGR2 (rw) register accessor: ADC configuration register 2
+
+You can [`read`](crate::Reg::read) this register and get [`cfgr2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfgr2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
+
+See register [structure](https://stm32-rs.github.io/stm32-rs/STM32U535.html#ADC4:CFGR2)
+
+For information about available fields see [`mod@cfgr2`] module*/
+pub type CFGR2 = crate::Reg<cfgr2::CFGR2rs>;
+///ADC configuration register 2
+pub mod cfgr2;
+/**SMPR (rw) register accessor: ADC sample time register
+
+You can [`read`](crate::Reg::read) this register and get [`smpr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`smpr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
+
+See register [structure](https://stm32-rs.github.io/stm32-rs/STM32U535.html#ADC4:SMPR)
+
+For information about available fields see [`mod@smpr`] module*/
+pub type SMPR = crate::Reg<smpr::SMPRrs>;
+///ADC sample time register
+pub mod smpr;
+/**AWD1TR (rw) register accessor: ADC watchdog threshold register
+
+You can [`read`](crate::Reg::read) this register and get [`awd1tr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`awd1tr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
+
+See register [structure](https://stm32-rs.github.io/stm32-rs/STM32U535.html#ADC4:AWD1TR)
+
+For information about available fields see [`mod@awd1tr`] module*/
+pub type AWD1TR = crate::Reg<awd1tr::AWD1TRrs>;
+///ADC watchdog threshold register
+pub mod awd1tr;
+/**AWD2TR (rw) register accessor: ADC watchdog threshold register
+
+You can [`read`](crate::Reg::read) this register and get [`awd2tr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`awd2tr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
+
+See register [structure](https://stm32-rs.github.io/stm32-rs/STM32U535.html#ADC4:AWD2TR)
+
+For information about available fields see [`mod@awd2tr`] module*/
+pub type AWD2TR = crate::Reg<awd2tr::AWD2TRrs>;
+///ADC watchdog threshold register
+pub mod awd2tr;
+/**CHSELR0 (rw) register accessor: ADC channel selection register \[alternate\]
+
+You can [`read`](crate::Reg::read) this register and get [`chselr0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`chselr0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
+
+See register [structure](https://stm32-rs.github.io/stm32-rs/STM32U535.html#ADC4:CHSELR0)
+
+For information about available fields see [`mod@chselr0`] module*/
+pub type CHSELR0 = crate::Reg<chselr0::CHSELR0rs>;
+///ADC channel selection register \[alternate\]
+pub mod chselr0;
+/**CHSELR1 (rw) register accessor: ADC channel selection register \[alternate\]
+
+You can [`read`](crate::Reg::read) this register and get [`chselr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`chselr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
+
+See register [structure](https://stm32-rs.github.io/stm32-rs/STM32U535.html#ADC4:CHSELR1)
+
+For information about available fields see [`mod@chselr1`] module*/
+pub type CHSELR1 = crate::Reg<chselr1::CHSELR1rs>;
+///ADC channel selection register \[alternate\]
+pub mod chselr1;
+/**AWD3TR (rw) register accessor: ADC watchdog threshold register
+
+You can [`read`](crate::Reg::read) this register and get [`awd3tr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`awd3tr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
+
+See register [structure](https://stm32-rs.github.io/stm32-rs/STM32U535.html#ADC4:AWD3TR)
+
+For information about available fields see [`mod@awd3tr`] module*/
+pub type AWD3TR = crate::Reg<awd3tr::AWD3TRrs>;
+///ADC watchdog threshold register
+pub mod awd3tr;
+/**DR (r) register accessor: ADC data register
+
+You can [`read`](crate::Reg::read) this register and get [`dr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
+
+See register [structure](https://stm32-rs.github.io/stm32-rs/STM32U535.html#ADC4:DR)
+
+For information about available fields see [`mod@dr`] module*/
+pub type DR = crate::Reg<dr::DRrs>;
+///ADC data register
+pub mod dr;
+/**PWRR (rw) register accessor: ADC data register
+
+You can [`read`](crate::Reg::read) this register and get [`pwrr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwrr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
+
+See register [structure](https://stm32-rs.github.io/stm32-rs/STM32U535.html#ADC4:PWRR)
+
+For information about available fields see [`mod@pwrr`] module*/
+pub type PWRR = crate::Reg<pwrr::PWRRrs>;
+///ADC data register
+pub mod pwrr;
+/**AWD2CR (rw) register accessor: ADC Analog Watchdog 2 Configuration register
+
+You can [`read`](crate::Reg::read) this register and get [`awd2cr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`awd2cr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
+
+See register [structure](https://stm32-rs.github.io/stm32-rs/STM32U535.html#ADC4:AWD2CR)
+
+For information about available fields see [`mod@awd2cr`] module*/
+pub type AWD2CR = crate::Reg<awd2cr::AWD2CRrs>;
+///ADC Analog Watchdog 2 Configuration register
+pub mod awd2cr;
+/**AWD3CR (rw) register accessor: ADC Analog Watchdog 3 Configuration register
+
+You can [`read`](crate::Reg::read) this register and get [`awd3cr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`awd3cr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
+
+See register [structure](https://stm32-rs.github.io/stm32-rs/STM32U535.html#ADC4:AWD3CR)
+
+For information about available fields see [`mod@awd3cr`] module*/
+pub type AWD3CR = crate::Reg<awd3cr::AWD3CRrs>;
+///ADC Analog Watchdog 3 Configuration register
+pub mod awd3cr;
+/**CALFACT (rw) register accessor: ADC Calibration factor
+
+You can [`read`](crate::Reg::read) this register and get [`calfact::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`calfact::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
+
+See register [structure](https://stm32-rs.github.io/stm32-rs/STM32U535.html#ADC4:CALFACT)
+
+For information about available fields see [`mod@calfact`] module*/
+pub type CALFACT = crate::Reg<calfact::CALFACTrs>;
+///ADC Calibration factor
+pub mod calfact;
+/**OR (rw) register accessor: ADC option register
+
+You can [`read`](crate::Reg::read) this register and get [`or::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`or::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
+
+See register [structure](https://stm32-rs.github.io/stm32-rs/STM32U535.html#ADC4:OR)
+
+For information about available fields see [`mod@or`] module*/
+pub type OR = crate::Reg<or::ORrs>;
+///ADC option register
+pub mod or;
+/**CCR (rw) register accessor: ADC common configuration register
+
+You can [`read`](crate::Reg::read) this register and get [`ccr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
+
+See register [structure](https://stm32-rs.github.io/stm32-rs/STM32U535.html#ADC4:CCR)
+
+For information about available fields see [`mod@ccr`] module*/
+pub type CCR = crate::Reg<ccr::CCRrs>;
+///ADC common configuration register
+pub mod ccr;

### external/vendor/stm32u5/src/stm32u535/adc4/awd1tr.rs
@@ -0,0 +1,63 @@
+///Register `AWD1TR` reader
+pub type R = crate::R<AWD1TRrs>;
+///Register `AWD1TR` writer
+pub type W = crate::W<AWD1TRrs>;
+///Field `LT1` reader - LT1
+pub type LT1_R = crate::FieldReader<u16>;
+///Field `LT1` writer - LT1
+pub type LT1_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16, crate::Safe>;
+///Field `HT1` reader - HT1
+pub type HT1_R = crate::FieldReader<u16>;
+///Field `HT1` writer - HT1
+pub type HT1_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16, crate::Safe>;
+impl R {
+    ///Bits 0:11 - LT1
+    #[inline(always)]
+    pub fn lt1(&self) -> LT1_R {
+        LT1_R::new((self.bits & 0x0fff) as u16)
+    }
+    ///Bits 16:27 - HT1
+    #[inline(always)]
+    pub fn ht1(&self) -> HT1_R {
+        HT1_R::new(((self.bits >> 16) & 0x0fff) as u16)
+    }
+}
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("AWD1TR")
+            .field("ht1", &self.ht1())
+            .field("lt1", &self.lt1())
+            .finish()
+    }
+}
+impl W {
+    ///Bits 0:11 - LT1
+    #[inline(always)]
+    pub fn lt1(&mut self) -> LT1_W<AWD1TRrs> {
+        LT1_W::new(self, 0)
+    }
+    ///Bits 16:27 - HT1
+    #[inline(always)]
+    pub fn ht1(&mut self) -> HT1_W<AWD1TRrs> {
+        HT1_W::new(self, 16)
+    }
+}
+/**ADC watchdog threshold register
+
+You can [`read`](crate::Reg::read) this register and get [`awd1tr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`awd1tr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
+
+See register [structure](https://stm32-rs.github.io/stm32-rs/STM32U535.html#ADC4:AWD1TR)*/
+pub struct AWD1TRrs;
+impl crate::RegisterSpec for AWD1TRrs {
+    type Ux = u32;
+}
+///`read()` method returns [`awd1tr::R`](R) reader structure
+impl crate::Readable for AWD1TRrs {}
+///`write(|w| ..)` method takes [`awd1tr::W`](W) writer structure
+impl crate::Writable for AWD1TRrs {
+    type Safety = crate::Unsafe;
+}
+///`reset()` method sets AWD1TR to value 0x0fff_0000
+impl crate::Resettable for AWD1TRrs {
+    const RESET_VALUE: u32 = 0x0fff_0000;
+}

### external/vendor/stm32u5/src/stm32u535/adc4/awd2cr.rs
@@ -0,0 +1,375 @@
+///Register `AWD2CR` reader
+pub type R = crate::R<AWD2CRrs>;
+///Register `AWD2CR` writer
+pub type W = crate::W<AWD2CRrs>;
+/**AWD2CH%s
+
+Value on reset: 0*/
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub enum AWD2CH0 {
+    ///0: ADC analog input channel x is not monitored by AWDy
+    Disabled = 0,
+    ///1: ADC analog input channel x is monitored by AWDy
+    Enabled = 1,
+}
+impl From<AWD2CH0> for bool {
+    #[inline(always)]
+    fn from(variant: AWD2CH0) -> Self {
+        variant as u8 != 0
+    }
+}
+///Field `AWD2CH(0-23)` reader - AWD2CH%s
+pub type AWD2CH_R = crate::BitReader<AWD2CH0>;
+impl AWD2CH_R {
+    ///Get enumerated values variant
+    #[inline(always)]
+    pub const fn variant(&self) -> AWD2CH0 {
+        match self.bits {
+            false => AWD2CH0::Disabled,
+            true => AWD2CH0::Enabled,
+        }
+    }
+    ///ADC analog input channel x is not monitored by AWDy
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == AWD2CH0::Disabled
+    }
+    ///ADC analog input channel x is monitored by AWDy
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == AWD2CH0::Enabled
+    }
+}
+///Field `AWD2CH(0-23)` writer - AWD2CH%s
+pub type AWD2CH_W<'a, REG> = crate::BitWriter<'a, REG, AWD2CH0>;
+impl<'a, REG> AWD2CH_W<'a, REG>
+where
+    REG: crate::Writable + crate::RegisterSpec,
+{
+    ///ADC analog input channel x is not monitored by AWDy
+    #[inline(always)]
+    pub fn disabled(self) -> &'a mut crate::W<REG> {
+        self.variant(AWD2CH0::Disabled)
+    }
+    ///ADC analog input channel x is monitored by AWDy
+    #[inline(always)]
+    pub fn enabled(self) -> &'a mut crate::W<REG> {
+        self.variant(AWD2CH0::Enabled)
+    }
+}
+impl R {
+    ///AWD2CH(0-23)
+    ///
+    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `AWD2CH0` field.</div>
+    #[inline(always)]
+    pub fn awd2ch(&self, n: u8) -> AWD2CH_R {
+        #[allow(clippy::no_effect)]
+        [(); 24][n as usize];
+        AWD2CH_R::new(((self.bits >> n) & 1) != 0)
+    }
+    ///Iterator for array of:
+    ///AWD2CH(0-23)
+    #[inline(always)]
+    pub fn awd2ch_iter(&self) -> impl Iterator<Item = AWD2CH_R> + '_ {
+        (0..24).map(move |n| AWD2CH_R::new(((self.bits >> n) & 1) != 0))
+    }
+    ///Bit 0 - AWD2CH0
+    #[inline(always)]
+    pub fn awd2ch0(&self) -> AWD2CH_R {
+        AWD2CH_R::new((self.bits & 1) != 0)
+    }
+    ///Bit 1 - AWD2CH1
+    #[inline(always)]
+    pub fn awd2ch1(&self) -> AWD2CH_R {
+        AWD2CH_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    ///Bit 2 - AWD2CH2
+    #[inline(always)]
+    pub fn awd2ch2(&self) -> AWD2CH_R {
+        AWD2CH_R::new(((self.bits >> 2) & 1) != 0)
+    }
+    ///Bit 3 - AWD2CH3
+    #[inline(always)]
+    pub fn awd2ch3(&self) -> AWD2CH_R {
+        AWD2CH_R::new(((self.bits >> 3) & 1) != 0)
+    }
+    ///Bit 4 - AWD2CH4
+    #[inline(always)]
+    pub fn awd2ch4(&self) -> AWD2CH_R {
+        AWD2CH_R::new(((self.bits >> 4) & 1) != 0)
+    }
+    ///Bit 5 - AWD2CH5
+    #[inline(always)]
+    pub fn awd2ch5(&self) -> AWD2CH_R {
+        AWD2CH_R::new(((self.bits >> 5) & 1) != 0)
+    }
+    ///Bit 6 - AWD2CH6
+    #[inline(always)]
+    pub fn awd2ch6(&self) -> AWD2CH_R {
+        AWD2CH_R::new(((self.bits >> 6) & 1) != 0)
+    }
+    ///Bit 7 - AWD2CH7
+    #[inline(always)]
+    pub fn awd2ch7(&self) -> AWD2CH_R {
+        AWD2CH_R::new(((self.bits >> 7) & 1) != 0)
+    }
+    ///Bit 8 - AWD2CH8
+    #[inline(always)]
+    pub fn awd2ch8(&self) -> AWD2CH_R {
+        AWD2CH_R::new(((self.bits >> 8) & 1) != 0)
+    }
+    ///Bit 9 - AWD2CH9
+    #[inline(always)]
+    pub fn awd2ch9(&self) -> AWD2CH_R {
+        AWD2CH_R::new(((self.bits >> 9) & 1) != 0)
+    }
+    ///Bit 10 - AWD2CH10
+    #[inline(always)]
+    pub fn awd2ch10(&self) -> AWD2CH_R {
+        AWD2CH_R::new(((self.bits >> 10) & 1) != 0)
+    }
+    ///Bit 11 - AWD2CH11
+    #[inline(always)]
+    pub fn awd2ch11(&self) -> AWD2CH_R {
+        AWD2CH_R::new(((self.bits >> 11) & 1) != 0)
+    }
+    ///Bit 12 - AWD2CH12
+    #[inline(always)]
+    pub fn awd2ch12(&self) -> AWD2CH_R {
+        AWD2CH_R::new(((self.bits >> 12) & 1) != 0)
+    }
+    ///Bit 13 - AWD2CH13
+    #[inline(always)]
+    pub fn awd2ch13(&self) -> AWD2CH_R {
+        AWD2CH_R::new(((self.bits >> 13) & 1) != 0)
+    }
+    ///Bit 14 - AWD2CH14
+    #[inline(always)]
+    pub fn awd2ch14(&self) -> AWD2CH_R {
+        AWD2CH_R::new(((self.bits >> 14) & 1) != 0)
+    }
+    ///Bit 15 - AWD2CH15
+    #[inline(always)]
+    pub fn awd2ch15(&self) -> AWD2CH_R {
+        AWD2CH_R::new(((self.bits >> 15) & 1) != 0)
+    }
+    ///Bit 16 - AWD2CH16
+    #[inline(always)]
+    pub fn awd2ch16(&self) -> AWD2CH_R {
+        AWD2CH_R::new(((self.bits >> 16) & 1) != 0)
+    }
+    ///Bit 17 - AWD2CH17
+    #[inline(always)]
+    pub fn awd2ch17(&self) -> AWD2CH_R {
+        AWD2CH_R::new(((self.bits >> 17) & 1) != 0)
+    }
+    ///Bit 18 - AWD2CH18
+    #[inline(always)]
+    pub fn awd2ch18(&self) -> AWD2CH_R {
+        AWD2CH_R::new(((self.bits >> 18) & 1) != 0)
+    }
+    ///Bit 19 - AWD2CH19
+    #[inline(always)]
+    pub fn awd2ch19(&self) -> AWD2CH_R {
+        AWD2CH_R::new(((self.bits >> 19) & 1) != 0)
+    }
+    ///Bit 20 - AWD2CH20
+    #[inline(always)]
+    pub fn awd2ch20(&self) -> AWD2CH_R {
+        AWD2CH_R::new(((self.bits >> 20) & 1) != 0)
+    }
+    ///Bit 21 - AWD2CH21
+    #[inline(always)]
+    pub fn awd2ch21(&self) -> AWD2CH_R {
+        AWD2CH_R::new(((self.bits >> 21) & 1) != 0)
+    }
+    ///Bit 22 - AWD2CH22
+    #[inline(always)]
+    pub fn awd2ch22(&self) -> AWD2CH_R {
+        AWD2CH_R::new(((self.bits >> 22) & 1) != 0)
+    }
+    ///Bit 23 - AWD2CH23
+    #[inline(always)]
+    pub fn awd2ch23(&self) -> AWD2CH_R {
+        AWD2CH_R::new(((self.bits >> 23) & 1) != 0)
+    }
+}
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("AWD2CR")
+            .field("awd2ch0", &self.awd2ch0())
+            .field("awd2ch1", &self.awd2ch1())
+            .field("awd2ch2", &self.awd2ch2())
+            .field("awd2ch3", &self.awd2ch3())
+            .field("awd2ch4", &self.awd2ch4())
+            .field("awd2ch5", &self.awd2ch5())
+            .field("awd2ch6", &self.awd2ch6())
+            .field("awd2ch7", &self.awd2ch7())
+            .field("awd2ch8", &self.awd2ch8())
+            .field("awd2ch9", &self.awd2ch9())
+            .field("awd2ch10", &self.awd2ch10())
+            .field("awd2ch11", &self.awd2ch11())
+            .field("awd2ch12", &self.awd2ch12())
+            .field("awd2ch13", &self.awd2ch13())
+            .field("awd2ch14", &self.awd2ch14())
+            .field("awd2ch15", &self.awd2ch15())
+            .field("awd2ch16", &self.awd2ch16())
+            .field("awd2ch17", &self.awd2ch17())
+            .field("awd2ch18", &self.awd2ch18())
+            .field("awd2ch19", &self.awd2ch19())
+            .field("awd2ch20", &self.awd2ch20())
+            .field("awd2ch21", &self.awd2ch21())
+            .field("awd2ch22", &self.awd2ch22())
+            .field("awd2ch23", &self.awd2ch23())
+            .finish()
+    }
+}
+impl W {
+    ///AWD2CH(0-23)
+    ///
+    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `AWD2CH0` field.</div>
+    #[inline(always)]
+    pub fn awd2ch(&mut self, n: u8) -> AWD2CH_W<AWD2CRrs> {
+        #[allow(clippy::no_effect)]
+        [(); 24][n as usize];
+        AWD2CH_W::new(self, n)
+    }
+    ///Bit 0 - AWD2CH0
+    #[inline(always)]
+    pub fn awd2ch0(&mut self) -> AWD2CH_W<AWD2CRrs> {
+        AWD2CH_W::new(self, 0)
+    }
+    ///Bit 1 - AWD2CH1
+    #[inline(always)]
+    pub fn awd2ch1(&mut self) -> AWD2CH_W<AWD2CRrs> {
+        AWD2CH_W::new(self, 1)
+    }
+    ///Bit 2 - AWD2CH2
+    #[inline(always)]
+    pub fn awd2ch2(&mut self) -> AWD2CH_W<AWD2CRrs> {
+        AWD2CH_W::new(self, 2)
+    }
+    ///Bit 3 - AWD2CH3
+    #[inline(always)]
+    pub fn awd2ch3(&mut self) -> AWD2CH_W<AWD2CRrs> {
+        AWD2CH_W::new(self, 3)
+    }
+    ///Bit 4 - AWD2CH4
+    #[inline(always)]
+    pub fn awd2ch4(&mut self) -> AWD2CH_W<AWD2CRrs> {
+        AWD2CH_W::new(self, 4)
+    }
+    ///Bit 5 - AWD2CH5
+    #[inline(always)]
+    pub fn awd2ch5(&mut self) -> AWD2CH_W<AWD2CRrs> {
+        AWD2CH_W::new(self, 5)
+    }
+    ///Bit 6 - AWD2CH6
+    #[inline(always)]
+    pub fn awd2ch6(&mut self) -> AWD2CH_W<AWD2CRrs> {
+        AWD2CH_W::new(self, 6)
+    }
+    ///Bit 7 - AWD2CH7
+    #[inline(always)]
+    pub fn awd2ch7(&mut self) -> AWD2CH_W<AWD2CRrs> {
+        AWD2CH_W::new(self, 7)
+    }
+    ///Bit 8 - AWD2CH8
+    #[inline(always)]
+    pub fn awd2ch8(&mut self) -> AWD2CH_W<AWD2CRrs> {
+        AWD2CH_W::new(self, 8)
+    }
+    ///Bit 9 - AWD2CH9
+    #[inline(always)]
+    pub fn awd2ch9(&mut self) -> AWD2CH_W<AWD2CRrs> {
+        AWD2CH_W::new(self, 9)
+    }
+    ///Bit 10 - AWD2CH10
+    #[inline(always)]
+    pub fn awd2ch10(&mut self) -> AWD2CH_W<AWD2CRrs> {
+        AWD2CH_W::new(self, 10)
+    }
+    ///Bit 11 - AWD2CH11
+    #[inline(always)]
+    pub fn awd2ch11(&mut self) -> AWD2CH_W<AWD2CRrs> {
+        AWD2CH_W::new(self, 11)
+    }
+    ///Bit 12 - AWD2CH12
+    #[inline(always)]
+    pub fn awd2ch12(&mut self) -> AWD2CH_W<AWD2CRrs> {
+        AWD2CH_W::new(self, 12)
+    }
+    ///Bit 13 - AWD2CH13
+    #[inline(always)]
+    pub fn awd2ch13(&mut self) -> AWD2CH_W<AWD2CRrs> {
+        AWD2CH_W::new(self, 13)
+    }
+    ///Bit 14 - AWD2CH14
+    #[inline(always)]
+    pub fn awd2ch14(&mut self) -> AWD2CH_W<AWD2CRrs> {
+        AWD2CH_W::new(self, 14)
+    }
+    ///Bit 15 - AWD2CH15
+    #[inline(always)]
+    pub fn awd2ch15(&mut self) -> AWD2CH_W<AWD2CRrs> {
+        AWD2CH_W::new(self, 15)
+    }
+    ///Bit 16 - AWD2CH16
+    #[inline(always)]
+    pub fn awd2ch16(&mut self) -> AWD2CH_W<AWD2CRrs> {
+        AWD2CH_W::new(self, 16)
+    }
+    ///Bit 17 - AWD2CH17
+    #[inline(always)]
+    pub fn awd2ch17(&mut self) -> AWD2CH_W<AWD2CRrs> {
+        AWD2CH_W::new(self, 17)
+    }
+    ///Bit 18 - AWD2CH18
+    #[inline(always)]
+    pub fn awd2ch18(&mut self) -> AWD2CH_W<AWD2CRrs> {
+        AWD2CH_W::new(self, 18)
+    }
+    ///Bit 19 - AWD2CH19
+    #[inline(always)]
+    pub fn awd2ch19(&mut self) -> AWD2CH_W<AWD2CRrs> {
+        AWD2CH_W::new(self, 19)
+    }
+    ///Bit 20 - AWD2CH20
+    #[inline(always)]
+    pub fn awd2ch20(&mut self) -> AWD2CH_W<AWD2CRrs> {
+        AWD2CH_W::new(self, 20)
+    }
+    ///Bit 21 - AWD2CH21
+    #[inline(always)]
+    pub fn awd2ch21(&mut self) -> AWD2CH_W<AWD2CRrs> {
+        AWD2CH_W::new(self, 21)
+    }
+    ///Bit 22 - AWD2CH22
+    #[inline(always)]
+    pub fn awd2ch22(&mut self) -> AWD2CH_W<AWD2CRrs> {
+        AWD2CH_W::new(self, 22)
+    }
+    ///Bit 23 - AWD2CH23
+    #[inline(always)]
+    pub fn awd2ch23(&mut self) -> AWD2CH_W<AWD2CRrs> {
+        AWD2CH_W::new(self, 23)
+    }
+}
+/**ADC Analog Watchdog 2 Configuration register
+
+You can [`read`](crate::Reg::read) this register and get [`awd2cr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`awd2cr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
+
+See register [structure](https://stm32-rs.github.io/stm32-rs/STM32U535.html#ADC4:AWD2CR)*/
+pub struct AWD2CRrs;
+impl crate::RegisterSpec for AWD2CRrs {
+    type Ux = u32;
+}
+///`read()` method returns [`awd2cr::R`](R) reader structure
+impl crate::Readable for AWD2CRrs {}
+///`write(|w| ..)` method takes [`awd2cr::W`](W) writer structure
+impl crate::Writable for AWD2CRrs {
+    type Safety = crate::Unsafe;
+}
+///`reset()` method sets AWD2CR to value 0
+impl crate::Resettable for AWD2CRrs {}

### external/vendor/stm32u5/src/stm32u535/adc4/awd2tr.rs
@@ -0,0 +1,63 @@
+///Register `AWD2TR` reader
+pub type R = crate::R<AWD2TRrs>;
+///Register `AWD2TR` writer
+pub type W = crate::W<AWD2TRrs>;
+///Field `LT2` reader - LT2
+pub type LT2_R = crate::FieldReader<u16>;
+///Field `LT2` writer - LT2
+pub type LT2_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16, crate::Safe>;
+///Field `HT2` reader - HT2
+pub type HT2_R = crate::FieldReader<u16>;
+///Field `HT2` writer - HT2
+pub type HT2_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16, crate::Safe>;
+impl R {
+    ///Bits 0:11 - LT2
+    #[inline(always)]
+    pub fn lt2(&self) -> LT2_R {
+        LT2_R::new((self.bits & 0x0fff) as u16)
+    }
+    ///Bits 16:27 - HT2
+    #[inline(always)]
+    pub fn ht2(&self) -> HT2_R {
+        HT2_R::new(((self.bits >> 16) & 0x0fff) as u16)
+    }
+}
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("AWD2TR")
+            .field("ht2", &self.ht2())
+            .field("lt2", &self.lt2())
+            .finish()
+    }
+}
+impl W {
+    ///Bits 0:11 - LT2
+    #[inline(always)]
+    pub fn lt2(&mut self) -> LT2_W<AWD2TRrs> {
+        LT2_W::new(self, 0)
+    }
+    ///Bits 16:27 - HT2
+    #[inline(always)]
+    pub fn ht2(&mut self) -> HT2_W<AWD2TRrs> {
+        HT2_W::new(self, 16)
+    }
+}
+/**ADC watchdog threshold register
+
+You can [`read`](crate::Reg::read) this register and get [`awd2tr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`awd2tr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
+
+See register [structure](https://stm32-rs.github.io/stm32-rs/STM32U535.html#ADC4:AWD2TR)*/
+pub struct AWD2TRrs;
+impl crate::RegisterSpec for AWD2TRrs {
+    type Ux = u32;
+}
+///`read()` method returns [`awd2tr::R`](R) reader structure
+impl crate::Readable for AWD2TRrs {}
+///`write(|w| ..)` method takes [`awd2tr::W`](W) writer structure
+impl crate::Writable for AWD2TRrs {
+    type Safety = crate::Unsafe;
+}
+///`reset()` method sets AWD2TR to value 0x0fff_0000
+impl crate::Resettable for AWD2TRrs {
+    const RESET_VALUE: u32 = 0x0fff_0000;
+}

### external/vendor/stm32u5/src/stm32u535/adc4/awd3cr.rs
@@ -0,0 +1,375 @@
+///Register `AWD3CR` reader
+pub type R = crate::R<AWD3CRrs>;
+///Register `AWD3CR` writer
+pub type W = crate::W<AWD3CRrs>;
+/**AWD3CH%s
+
+Value on reset: 0*/
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub enum AWD3CH0 {
+    ///0: ADC analog input channel x is not monitored by AWDy
+    Disabled = 0,
+    ///1: ADC analog input channel x is monitored by AWDy
+    Enabled = 1,
+}
+impl From<AWD3CH0> for bool {
+    #[inline(always)]
+    fn from(variant: AWD3CH0) -> Self {
+        variant as u8 != 0
+    }
+}
+///Field `AWD3CH(0-23)` reader - AWD3CH%s
+pub type AWD3CH_R = crate::BitReader<AWD3CH0>;
+impl AWD3CH_R {
+    ///Get enumerated values variant
+    #[inline(always)]
+    pub const fn variant(&self) -> AWD3CH0 {
+        match self.bits {
+            false => AWD3CH0::Disabled,
+            true => AWD3CH0::Enabled,
+        }
+    }
+    ///ADC analog input channel x is not monitored by AWDy
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == AWD3CH0::Disabled
+    }
+    ///ADC analog input channel x is monitored by AWDy
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == AWD3CH0::Enabled
+    }
+}
+///Field `AWD3CH(0-23)` writer - AWD3CH%s
+pub type AWD3CH_W<'a, REG> = crate::BitWriter<'a, REG, AWD3CH0>;
+impl<'a, REG> AWD3CH_W<'a, REG>
+where
+    REG: crate::Writable + crate::RegisterSpec,
+{
+    ///ADC analog input channel x is not monitored by AWDy
+    #[inline(always)]
+    pub fn disabled(self) -> &'a mut crate::W<REG> {
+        self.variant(AWD3CH0::Disabled)
+    }
+    ///ADC analog input channel x is monitored by AWDy
+    #[inline(always)]
+    pub fn enabled(self) -> &'a mut crate::W<REG> {
+        self.variant(AWD3CH0::Enabled)
+    }
+}
+impl R {
+    ///AWD3CH(0-23)
+    ///
+    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `AWD3CH0` field.</div>
+    #[inline(always)]
+    pub fn awd3ch(&self, n: u8) -> AWD3CH_R {
+        #[allow(clippy::no_effect)]
+        [(); 24][n as usize];
+        AWD3CH_R::new(((self.bits >> n) & 1) != 0)
+    }
+    ///Iterator for array of:
+    ///AWD3CH(0-23)
+    #[inline(always)]
+    pub fn awd3ch_iter(&self) -> impl Iterator<Item = AWD3CH_R> + '_ {
+        (0..24).map(move |n| AWD3CH_R::new(((self.bits >> n) & 1) != 0))
+    }
+    ///Bit 0 - AWD3CH0
+    #[inline(always)]
+    pub fn awd3ch0(&self) -> AWD3CH_R {
+        AWD3CH_R::new((self.bits & 1) != 0)
+    }
+    ///Bit 1 - AWD3CH1
+    #[inline(always)]
+    pub fn awd3ch1(&self) -> AWD3CH_R {
+        AWD3CH_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    ///Bit 2 - AWD3CH2
+    #[inline(always)]
+    pub fn awd3ch2(&self) -> AWD3CH_R {
+        AWD3CH_R::new(((self.bits >> 2) & 1) != 0)
+    }
+    ///Bit 3 - AWD3CH3
+    #[inline(always)]
+    pub fn awd3ch3(&self) -> AWD3CH_R {
+        AWD3CH_R::new(((self.bits >> 3) & 1) != 0)
+    }
+    ///Bit 4 - AWD3CH4
+    #[inline(always)]
+    pub fn awd3ch4(&self) -> AWD3CH_R {
+        AWD3CH_R::new(((self.bits >> 4) & 1) != 0)
+    }
+    ///Bit 5 - AWD3CH5
+    #[inline(always)]
+    pub fn awd3ch5(&self) -> AWD3CH_R {
+        AWD3CH_R::new(((self.bits >> 5) & 1) != 0)
+    }
+    ///Bit 6 - AWD3CH6
+    #[inline(always)]
+    pub fn awd3ch6(&self) -> AWD3CH_R {
+        AWD3CH_R::new(((self.bits >> 6) & 1) != 0)
+    }
+    ///Bit 7 - AWD3CH7
+    #[inline(always)]
+    pub fn awd3ch7(&self) -> AWD3CH_R {
+        AWD3CH_R::new(((self.bits >> 7) & 1) != 0)
+    }
+    ///Bit 8 - AWD3CH8
+    #[inline(always)]
+    pub fn awd3ch8(&self) -> AWD3CH_R {
+        AWD3CH_R::new(((self.bits >> 8) & 1) != 0)
+    }
+    ///Bit 9 - AWD3CH9
+    #[inline(always)]
+    pub fn awd3ch9(&self) -> AWD3CH_R {
+        AWD3CH_R::new(((self.bits >> 9) & 1) != 0)
+    }
+    ///Bit 10 - AWD3CH10
+    #[inline(always)]
+    pub fn awd3ch10(&self) -> AWD3CH_R {
+        AWD3CH_R::new(((self.bits >> 10) & 1) != 0)
+    }
+    ///Bit 11 - AWD3CH11
+    #[inline(always)]
+    pub fn awd3ch11(&self) -> AWD3CH_R {
+        AWD3CH_R::new(((self.bits >> 11) & 1) != 0)
+    }
+    ///Bit 12 - AWD3CH12
+    #[inline(always)]
+    pub fn awd3ch12(&self) -> AWD3CH_R {
+        AWD3CH_R::new(((self.bits >> 12) & 1) != 0)
+    }
+    ///Bit 13 - AWD3CH13
+    #[inline(always)]
+    pub fn awd3ch13(&self) -> AWD3CH_R {
+        AWD3CH_R::new(((self.bits >> 13) & 1) != 0)
+    }
+    ///Bit 14 - AWD3CH14
+    #[inline(always)]
+    pub fn awd3ch14(&self) -> AWD3CH_R {
+        AWD3CH_R::new(((self.bits >> 14) & 1) != 0)
+    }
+    ///Bit 15 - AWD3CH15
+    #[inline(always)]
+    pub fn awd3ch15(&self) -> AWD3CH_R {
+        AWD3CH_R::new(((self.bits >> 15) & 1) != 0)
+    }
+    ///Bit 16 - AWD3CH16
+    #[inline(always)]
+    pub fn awd3ch16(&self) -> AWD3CH_R {
+        AWD3CH_R::new(((self.bits >> 16) & 1) != 0)
+    }
+    ///Bit 17 - AWD3CH17
+    #[inline(always)]
+    pub fn awd3ch17(&self) -> AWD3CH_R {
+        AWD3CH_R::new(((self.bits >> 17) & 1) != 0)
+    }
+    ///Bit 18 - AWD3CH18
+    #[inline(always)]
+    pub fn awd3ch18(&self) -> AWD3CH_R {
+        AWD3CH_R::new(((self.bits >> 18) & 1) != 0)
+    }
+    ///Bit 19 - AWD3CH19
+    #[inline(always)]
+    pub fn awd3ch19(&self) -> AWD3CH_R {
+        AWD3CH_R::new(((self.bits >> 19) & 1) != 0)
+    }
+    ///Bit 20 - AWD3CH20
+    #[inline(always)]
+    pub fn awd3ch20(&self) -> AWD3CH_R {
+        AWD3CH_R::new(((self.bits >> 20) & 1) != 0)
+    }
+    ///Bit 21 - AWD3CH21
+    #[inline(always)]
+    pub fn awd3ch21(&self) -> AWD3CH_R {
+        AWD3CH_R::new(((self.bits >> 21) & 1) != 0)
+    }
+    ///Bit 22 - AWD3CH22
+    #[inline(always)]
+    pub fn awd3ch22(&self) -> AWD3CH_R {
+        AWD3CH_R::new(((self.bits >> 22) & 1) != 0)
+    }
+    ///Bit 23 - AWD3CH23
+    #[inline(always)]
+    pub fn awd3ch23(&self) -> AWD3CH_R {
+        AWD3CH_R::new(((self.bits >> 23) & 1) != 0)
+    }
+}
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("AWD3CR")
+            .field("awd3ch0", &self.awd3ch0())
+            .field("awd3ch1", &self.awd3ch1())
+            .field("awd3ch2", &self.awd3ch2())
+            .field("awd3ch3", &self.awd3ch3())
+            .field("awd3ch4", &self.awd3ch4())
+            .field("awd3ch5", &self.awd3ch5())
+            .field("awd3ch6", &self.awd3ch6())
+            .field("awd3ch7", &self.awd3ch7())
+            .field("awd3ch8", &self.awd3ch8())
+            .field("awd3ch9", &self.awd3ch9())
+            .field("awd3ch10", &self.awd3ch10())
+            .field("awd3ch11", &self.awd3ch11())
+            .field("awd3ch12", &self.awd3ch12())
+            .field("awd3ch13", &self.awd3ch13())
+            .field("awd3ch14", &self.awd3ch14())
+            .field("awd3ch15", &self.awd3ch15())
+            .field("awd3ch16", &self.awd3ch16())
+            .field("awd3ch17", &self.awd3ch17())
+            .field("awd3ch18", &self.awd3ch18())
+            .field("awd3ch19", &self.awd3ch19())
+            .field("awd3ch20", &self.awd3ch20())
+            .field("awd3ch21", &self.awd3ch21())
+            .field("awd3ch22", &self.awd3ch22())
+            .field("awd3ch23", &self.awd3ch23())
+            .finish()
+    }
+}
+impl W {
+    ///AWD3CH(0-23)
+    ///
+    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `AWD3CH0` field.</div>
+    #[inline(always)]
+    pub fn awd3ch(&mut self, n: u8) -> AWD3CH_W<AWD3CRrs> {
+        #[allow(clippy::no_effect)]
+        [(); 24][n as usize];
+        AWD3CH_W::new(self, n)
+    }
+    ///Bit 0 - AWD3CH0
+    #[inline(always)]
+    pub fn awd3ch0(&mut self) -> AWD3CH_W<AWD3CRrs> {
+        AWD3CH_W::new(self, 0)
+    }
+    ///Bit 1 - AWD3CH1
+    #[inline(always)]
+    pub fn awd3ch1(&mut self) -> AWD3CH_W<AWD3CRrs> {
+        AWD3CH_W::new(self, 1)
+    }
+    ///Bit 2 - AWD3CH2
+    #[inline(always)]
+    pub fn awd3ch2(&mut self) -> AWD3CH_W<AWD3CRrs> {
+        AWD3CH_W::new(self, 2)
+    }
+    ///Bit 3 - AWD3CH3
+    #[inline(always)]
+    pub fn awd3ch3(&mut self) -> AWD3CH_W<AWD3CRrs> {
+        AWD3CH_W::new(self, 3)
+    }
+    ///Bit 4 - AWD3CH4
+    #[inline(always)]
+    pub fn awd3ch4(&mut self) -> AWD3CH_W<AWD3CRrs> {
+        AWD3CH_W::new(self, 4)
+    }
+    ///Bit 5 - AWD3CH5
+    #[inline(always)]
+    pub fn awd3ch5(&mut self) -> AWD3CH_W<AWD3CRrs> {
+        AWD3CH_W::new(self, 5)
+    }
+    ///Bit 6 - AWD3CH6
+    #[inline(always)]
+    pub fn awd3ch6(&mut self) -> AWD3CH_W<AWD3CRrs> {
+        AWD3CH_W::new(self, 6)
+    }
+    ///Bit 7 - AWD3CH7
+    #[inline(always)]
+    pub fn awd3ch7(&mut self) -> AWD3CH_W<AWD3CRrs> {
+        AWD3CH_W::new(self, 7)
+    }
+    ///Bit 8 - AWD3CH8
+    #[inline(always)]
+    pub fn awd3ch8(&mut self) -> AWD3CH_W<AWD3CRrs> {
+        AWD3CH_W::new(self, 8)
+    }
+    ///Bit 9 - AWD3CH9
+    #[inline(always)]
+    pub fn awd3ch9(&mut self) -> AWD3CH_W<AWD3CRrs> {
+        AWD3CH_W::new(self, 9)
+    }
+    ///Bit 10 - AWD3CH10
+    #[inline(always)]
+    pub fn awd3ch10(&mut self) -> AWD3CH_W<AWD3CRrs> {
+        AWD3CH_W::new(self, 10)
+    }
+    ///Bit 11 - AWD3CH11
+    #[inline(always)]
+    pub fn awd3ch11(&mut self) -> AWD3CH_W<AWD3CRrs> {
+        AWD3CH_W::new(self, 11)
+    }
+    ///Bit 12 - AWD3CH12
+    #[inline(always)]
+    pub fn awd3ch12(&mut self) -> AWD3CH_W<AWD3CRrs> {
+        AWD3CH_W::new(self, 12)
+    }
+    ///Bit 13 - AWD3CH13
+    #[inline(always)]
+    pub fn awd3ch13(&mut self) -> AWD3CH_W<AWD3CRrs> {
+        AWD3CH_W::new(self, 13)
+    }
+    ///Bit 14 - AWD3CH14
+    #[inline(always)]
+    pub fn awd3ch14(&mut self) -> AWD3CH_W<AWD3CRrs> {
+        AWD3CH_W::new(self, 14)
+    }
+    ///Bit 15 - AWD3CH15
+    #[inline(always)]
+    pub fn awd3ch15(&mut self) -> AWD3CH_W<AWD3CRrs> {
+        AWD3CH_W::new(self, 15)
+    }
+    ///Bit 16 - AWD3CH16
+    #[inline(always)]
+    pub fn awd3ch16(&mut self) -> AWD3CH_W<AWD3CRrs> {
+        AWD3CH_W::new(self, 16)
+    }
+    ///Bit 17 - AWD3CH17
+    #[inline(always)]
+    pub fn awd3ch17(&mut self) -> AWD3CH_W<AWD3CRrs> {
+        AWD3CH_W::new(self, 17)
+    }
+    ///Bit 18 - AWD3CH18
+    #[inline(always)]
+    pub fn awd3ch18(&mut self) -> AWD3CH_W<AWD3CRrs> {
+        AWD3CH_W::new(self, 18)
+    }
+    ///Bit 19 - AWD3CH19
+    #[inline(always)]
+    pub fn awd3ch19(&mut self) -> AWD3CH_W<AWD3CRrs> {
+        AWD3CH_W::new(self, 19)
+    }
+    ///Bit 20 - AWD3CH20
+    #[inline(always)]
+    pub fn awd3ch20(&mut self) -> AWD3CH_W<AWD3CRrs> {
+        AWD3CH_W::new(self, 20)
+    }
+    ///Bit 21 - AWD3CH21
+    #[inline(always)]
+    pub fn awd3ch21(&mut self) -> AWD3CH_W<AWD3CRrs> {
+        AWD3CH_W::new(self, 21)
+    }
+    ///Bit 22 - AWD3CH22
+    #[inline(always)]
+    pub fn awd3ch22(&mut self) -> AWD3CH_W<AWD3CRrs> {
+        AWD3CH_W::new(self, 22)
+    }
+    ///Bit 23 - AWD3CH23
+    #[inline(always)]
+    pub fn awd3ch23(&mut self) -> AWD3CH_W<AWD3CRrs> {
+        AWD3CH_W::new(self, 23)
+    }
+}
+/**ADC Analog Watchdog 3 Configuration register
+
+You can [`read`](crate::Reg::read) this register and get [`awd3cr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`awd3cr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
+
+See register [structure](https://stm32-rs.github.io/stm32-rs/STM32U535.html#ADC4:AWD3CR)*/
+pub struct AWD3CRrs;
+impl crate::RegisterSpec for AWD3CRrs {
+    type Ux = u32;
+}
+///`read()` method returns [`awd3cr::R`](R) reader structure
+impl crate::Readable for AWD3CRrs {}
+///`write(|w| ..)` method takes [`awd3cr::W`](W) writer structure
+impl crate::Writable for AWD3CRrs {
+    type Safety = crate::Unsafe;
+}
+///`reset()` method sets AWD3CR to value 0
+impl crate::Resettable for AWD3CRrs {}

### external/vendor/stm32u5/src/stm32u535/adc4/awd3tr.rs
@@ -0,0 +1,63 @@
+///Register `AWD3TR` reader
+pub type R = crate::R<AWD3TRrs>;
+///Register `AWD3TR` writer
+pub type W = crate::W<AWD3TRrs>;
+///Field `LT3` reader - LT3
+pub type LT3_R = crate::FieldReader<u16>;
+///Field `LT3` writer - LT3
+pub type LT3_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16, crate::Safe>;
+///Field `HT3` reader - HT3
+pub type HT3_R = crate::FieldReader<u16>;
+///Field `HT3` writer - HT3
+pub type HT3_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16, crate::Safe>;
+impl R {
+    ///Bits 0:11 - LT3
+    #[inline(always)]
+    pub fn lt3(&self) -> LT3_R {
+        LT3_R::new((self.bits & 0x0fff) as u16)
+    }
+    ///Bits 16:27 - HT3
+    #[inline(always)]
+    pub fn ht3(&self) -> HT3_R {
+        HT3_R::new(((self.bits >> 16) & 0x0fff) as u16)
+    }
+}
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("AWD3TR")
+            .field("ht3", &self.ht3())
+            .field("lt3", &self.lt3())
+            .finish()
+    }
+}
+impl W {
+    ///Bits 0:11 - LT3
+    #[inline(always)]
+    pub fn lt3(&mut self) -> LT3_W<AWD3TRrs> {
+        LT3_W::new(self, 0)
+    }
+    ///Bits 16:27 - HT3
+    #[inline(always)]
+    pub fn ht3(&mut self) -> HT3_W<AWD3TRrs> {
+        HT3_W::new(self, 16)
+    }
+}
+/**ADC watchdog threshold register
+
+You can [`read`](crate::Reg::read) this register and get [`awd3tr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`awd3tr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
+
+See register [structure](https://stm32-rs.github.io/stm32-rs/STM32U535.html#ADC4:AWD3TR)*/
+pub struct AWD3TRrs;
+impl crate::RegisterSpec for AWD3TRrs {
+    type Ux = u32;
+}
+///`read()` method returns [`awd3tr::R`](R) reader structure
+impl crate::Readable for AWD3TRrs {}
+///`write(|w| ..)` method takes [`awd3tr::W`](W) writer structure
+impl crate::Writable for AWD3TRrs {
+    type Safety = crate::Unsafe;
+}
+///`reset()` method sets AWD3TR to value 0x0fff_0000
+impl crate::Resettable for AWD3TRrs {
+    const RESET_VALUE: u32 = 0x0fff_0000;
+}

### external/vendor/stm32u5/src/stm32u535/adc4/calfact.rs
@@ -0,0 +1,46 @@
+///Register `CALFACT` reader
+pub type R = crate::R<CALFACTrs>;
+///Register `CALFACT` writer
+pub type W = crate::W<CALFACTrs>;
+///Field `CALFACT` reader - CALFACT
+pub type CALFACT_R = crate::FieldReader;
+///Field `CALFACT` writer - CALFACT
+pub type CALFACT_W<'a, REG> = crate::FieldWriter<'a, REG, 7, u8, crate::Safe>;
+impl R {
+    ///Bits 0:6 - CALFACT
+    #[inline(always)]
+    pub fn calfact(&self) -> CALFACT_R {
+        CALFACT_R::new((self.bits & 0x7f) as u8)
+    }
+}
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CALFACT")
+            .field("calfact", &self.calfact())
+            .finish()
+    }
+}
+impl W {
+    ///Bits 0:6 - CALFACT
+    #[inline(always)]
+    pub fn calfact(&mut self) -> CALFACT_W<CALFACTrs> {
+        CALFACT_W::new(self, 0)
+    }
+}
+/**ADC Calibration factor
+
+You can [`read`](crate::Reg::read) this register and get [`calfact::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`calfact::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
+
+See register [structure](https://stm32-rs.github.io/stm32-rs/STM32U535.html#ADC4:CALFACT)*/
+pub struct CALFACTrs;
+impl crate::RegisterSpec for CALFACTrs {
+    type Ux = u32;
+}
+///`read()` method returns [`calfact::R`](R) reader structure
+impl crate::Readable for CALFACTrs {}
+///`write(|w| ..)` method takes [`calfact::W`](W) writer structure
+impl crate::Writable for CALFACTrs {
+    type Safety = crate::Unsafe;
+}
+///`reset()` method sets CALFACT to value 0
+impl crate::Resettable for CALFACTrs {}

### external/vendor/stm32u5/src/stm32u535/adc4/ccr.rs
@@ -0,0 +1,436 @@
+///Register `CCR` reader
+pub type R = crate::R<CCRrs>;
+///Register `CCR` writer
+pub type W = crate::W<CCRrs>;
+/**PRESC
+
+Value on reset: 0*/
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+#[repr(u8)]
+pub enum PRESC {
+    ///0: Input ADC clock not divided
+    Div1 = 0,
+    ///1: Input ADC clock divided by 2
+    Div2 = 1,
+    ///2: Input ADC clock divided by 4
+    Div4 = 2,
+    ///3: Input ADC clock divided by 6
+    Div6 = 3,
+    ///4: Input ADC clock divided by 8
+    Div8 = 4,
+    ///5: Input ADC clock divided by 10
+    Div10 = 5,
+    ///6: Input ADC clock divided by 12
+    Div12 = 6,
+    ///7: Input ADC clock divided by 16
+    Div16 = 7,
+    ///8: Input ADC clock divided by 32
+    Div32 = 8,
+    ///9: Input ADC clock divided by 64
+    Div64 = 9,
+    ///10: Input ADC clock divided by 128
+    Div128 = 10,
+    ///11: Input ADC clock divided by 256
+    Div256 = 11,
+}
+impl From<PRESC> for u8 {
+    #[inline(always)]
+    fn from(variant: PRESC) -> Self {
+        variant as _
+    }
+}
+impl crate::FieldSpec for PRESC {
+    type Ux = u8;
+}
+impl crate::IsEnum for PRESC {}
+///Field `PRESC` reader - PRESC
+pub type PRESC_R = crate::FieldReader<PRESC>;
+impl PRESC_R {
+    ///Get enumerated values variant
+    #[inline(always)]
+    pub const fn variant(&self) -> Option<PRESC> {
+        match self.bits {
+            0 => Some(PRESC::Div1),
+            1 => Some(PRESC::Div2),
+            2 => Some(PRESC::Div4),
+            3 => Some(PRESC::Div6),
+            4 => Some(PRESC::Div8),
+            5 => Some(PRESC::Div10),
+            6 => Some(PRESC::Div12),
+            7 => Some(PRESC::Div16),
+            8 => Some(PRESC::Div32),
+            9 => Some(PRESC::Div64),
+            10 => Some(PRESC::Div128),
+            11 => Some(PRESC::Div256),
+            _ => None,
+        }
+    }
+    ///Input ADC clock not divided
+    #[inline(always)]
+    pub fn is_div1(&self) -> bool {
+        *self == PRESC::Div1
+    }
+    ///Input ADC clock divided by 2
+    #[inline(always)]
+    pub fn is_div2(&self) -> bool {
+        *self == PRESC::Div2
+    }
+    ///Input ADC clock divided by 4
+    #[inline(always)]
+    pub fn is_div4(&self) -> bool {
+        *self == PRESC::Div4
+    }
+    ///Input ADC clock divided by 6
+    #[inline(always)]
+    pub fn is_div6(&self) -> bool {
+        *self == PRESC::Div6
+    }
+    ///Input ADC clock divided by 8
+    #[inline(always)]
+    pub fn is_div8(&self) -> bool {
+        *self == PRESC::Div8
+    }
+    ///Input ADC clock divided by 10
+    #[inline(always)]
+    pub fn is_div10(&self) -> bool {
+        *self == PRESC::Div10
+    }
+    ///Input ADC clock divided by 12
+    #[inline(always)]
+    pub fn is_div12(&self) -> bool {
+        *self == PRESC::Div12
+    }
+    ///Input ADC clock divided by 16
+    #[inline(always)]
+    pub fn is_div16(&self) -> bool {
+        *self == PRESC::Div16
+    }
+    ///Input ADC clock divided by 32
+    #[inline(always)]
+    pub fn is_div32(&self) -> bool {
+        *self == PRESC::Div32
+    }
+    ///Input ADC clock divided by 64
+    #[inline(always)]
+    pub fn is_div64(&self) -> bool {
+        *self == PRESC::Div64
+    }
+    ///Input ADC clock divided by 128
+    #[inline(always)]
+    pub fn is_div128(&self) -> bool {
+        *self == PRESC::Div128
+    }
+    ///Input ADC clock divided by 256
+    #[inline(always)]
+    pub fn is_div256(&self) -> bool {
+        *self == PRESC::Div256
+    }
+}
+///Field `PRESC` writer - PRESC
+pub type PRESC_W<'a, REG> = crate::FieldWriter<'a, REG, 4, PRESC>;
+impl<'a, REG> PRESC_W<'a, REG>
+where
+    REG: crate::Writable + crate::RegisterSpec,
+    REG::Ux: From<u8>,
+{
+    ///Input ADC clock not divided
+    #[inline(always)]
+    pub fn div1(self) -> &'a mut crate::W<REG> {
+        self.variant(PRESC::Div1)
+    }
+    ///Input ADC clock divided by 2
+    #[inline(always)]
+    pub fn div2(self) -> &'a mut crate::W<REG> {
+        self.variant(PRESC::Div2)
+    }
+    ///Input ADC clock divided by 4
+    #[inline(always)]
+    pub fn div4(self) -> &'a mut crate::W<REG> {
+        self.variant(PRESC::Div4)
+    }
+    ///Input ADC clock divided by 6
+    #[inline(always)]
+    pub fn div6(self) -> &'a mut crate::W<REG> {
+        self.variant(PRESC::Div6)
+    }
+    ///Input ADC clock divided by 8
+    #[inline(always)]
+    pub fn div8(self) -> &'a mut crate::W<REG> {
+        self.variant(PRESC::Div8)
+    }
+    ///Input ADC clock divided by 10
+    #[inline(always)]
+    pub fn div10(self) -> &'a mut crate::W<REG> {
+        self.variant(PRESC::Div10)
+    }
+    ///Input ADC clock divided by 12
+    #[inline(always)]
+    pub fn div12(self) -> &'a mut crate::W<REG> {
+        self.variant(PRESC::Div12)
+    }
+    ///Input ADC clock divided by 16
+    #[inline(always)]
+    pub fn div16(self) -> &'a mut crate::W<REG> {
+        self.variant(PRESC::Div16)
+    }
+    ///Input ADC clock divided by 32
+    #[inline(always)]
+    pub fn div32(self) -> &'a mut crate::W<REG> {
+        self.variant(PRESC::Div32)
+    }
+    ///Input ADC clock divided by 64
+    #[inline(always)]
+    pub fn div64(self) -> &'a mut crate::W<REG> {
+        self.variant(PRESC::Div64)
+    }
+    ///Input ADC clock divided by 128
+    #[inline(always)]
+    pub fn div128(self) -> &'a mut crate::W<REG> {
+        self.variant(PRESC::Div128)
+    }
+    ///Input ADC clock divided by 256
+    #[inline(always)]
+    pub fn div256(self) -> &'a mut crate::W<REG> {
+        self.variant(PRESC::Div256)
+    }
+}
+/**VREFEN
+
+Value on reset: 0*/
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub enum VREFEN {
+    ///0: VREFINT channel disabled
+    Disabled = 0,
+    ///1: VREFINT channel enabled
+    Enabled = 1,
+}
+impl From<VREFEN> for bool {
+    #[inline(always)]
+    fn from(variant: VREFEN) -> Self {
+        variant as u8 != 0
+    }
+}
+///Field `VREFEN` reader - VREFEN
+pub type VREFEN_R = crate::BitReader<VREFEN>;
+impl VREFEN_R {
+    ///Get enumerated values variant
+    #[inline(always)]
+    pub const fn variant(&self) -> VREFEN {
+        match self.bits {
+            false => VREFEN::Disabled,
+            true => VREFEN::Enabled,
+        }
+    }
+    ///VREFINT channel disabled
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == VREFEN::Disabled
+    }
+    ///VREFINT channel enabled
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == VREFEN::Enabled
+    }
+}
+///Field `VREFEN` writer - VREFEN
+pub type VREFEN_W<'a, REG> = crate::BitWriter<'a, REG, VREFEN>;
+impl<'a, REG> VREFEN_W<'a, REG>
+where
+    REG: crate::Writable + crate::RegisterSpec,
+{
+    ///VREFINT channel disabled
+    #[inline(always)]
+    pub fn disabled(self) -> &'a mut crate::W<REG> {
+        self.variant(VREFEN::Disabled)
+    }
+    ///VREFINT channel enabled
+    #[inline(always)]
+    pub fn enabled(self) -> &'a mut crate::W<REG> {
+        self.variant(VREFEN::Enabled)
+    }
+}
+/**TSEN
+
+Value on reset: 0*/
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub enum VSENSESEL {
+    ///0: Temperature sensor channel disabled
+    Disabled = 0,
+    ///1: Temperature sensor channel enabled
+    Enabled = 1,
+}
+impl From<VSENSESEL> for bool {
+    #[inline(always)]
+    fn from(variant: VSENSESEL) -> Self {
+        variant as u8 != 0
+    }
+}
+///Field `VSENSESEL` reader - TSEN
+pub type VSENSESEL_R = crate::BitReader<VSENSESEL>;
+impl VSENSESEL_R {
+    ///Get enumerated values variant
+    #[inline(always)]
+    pub const fn variant(&self) -> VSENSESEL {
+        match self.bits {
+            false => VSENSESEL::Disabled,
+            true => VSENSESEL::Enabled,
+        }
+    }
+    ///Temperature sensor channel disabled
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == VSENSESEL::Disabled
+    }
+    ///Temperature sensor channel enabled
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == VSENSESEL::Enabled
+    }
+}
+///Field `VSENSESEL` writer - TSEN
+pub type VSENSESEL_W<'a, REG> = crate::BitWriter<'a, REG, VSENSESEL>;
+impl<'a, REG> VSENSESEL_W<'a, REG>
+where
+    REG: crate::Writable + crate::RegisterSpec,
+{
+    ///Temperature sensor channel disabled
+    #[inline(always)]
+    pub fn disabled(self) -> &'a mut crate::W<REG> {
+        self.variant(VSENSESEL::Disabled)
+    }
+    ///Temperature sensor channel enabled
+    #[inline(always)]
+    pub fn enabled(self) -> &'a mut crate::W<REG> {
+        self.variant(VSENSESEL::Enabled)
+    }
+}
+/**VBATEN
+
+Value on reset: 0*/
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub enum VBATEN {
+    ///0: VBAT channel disabled
+    Disabled = 0,
+    ///1: VBAT channel enabled
+    Enabled = 1,
+}
+impl From<VBATEN> for bool {
+    #[inline(always)]
+    fn from(variant: VBATEN) -> Self {
+        variant as u8 != 0
+    }
+}
+///Field `VBATEN` reader - VBATEN
+pub type VBATEN_R = crate::BitReader<VBATEN>;
+impl VBATEN_R {
+    ///Get enumerated values variant
+    #[inline(always)]
+    pub const fn variant(&self) -> VBATEN {
+        match self.bits {
+            false => VBATEN::Disabled,
+            true => VBATEN::Enabled,
+        }
+    }
+    ///VBAT channel disabled
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == VBATEN::Disabled
+    }
+    ///VBAT channel enabled
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == VBATEN::Enabled
+    }
+}
+///Field `VBATEN` writer - VBATEN
+pub type VBATEN_W<'a, REG> = crate::BitWriter<'a, REG, VBATEN>;
+impl<'a, REG> VBATEN_W<'a, REG>
+where
+    REG: crate::Writable + crate::RegisterSpec,
+{
+    ///VBAT channel disabled
+    #[inline(always)]
+    pub fn disabled(self) -> &'a mut crate::W<REG> {
+        self.variant(VBATEN::Disabled)
+    }
+    ///VBAT channel enabled
+    #[inline(always)]
+    pub fn enabled(self) -> &'a mut crate::W<REG> {
+        self.variant(VBATEN::Enabled)
+    }
+}
+impl R {
+    ///Bits 18:21 - PRESC
+    #[inline(always)]
+    pub fn presc(&self) -> PRESC_R {
+        PRESC_R::new(((self.bits >> 18) & 0x0f) as u8)
+    }
+    ///Bit 22 - VREFEN
+    #[inline(always)]
+    pub fn vrefen(&self) -> VREFEN_R {
+        VREFEN_R::new(((self.bits >> 22) & 1) != 0)
+    }
+    ///Bit 23 - TSEN
+    #[inline(always)]
+    pub fn vsensesel(&self) -> VSENSESEL_R {
+        VSENSESEL_R::new(((self.bits >> 23) & 1) != 0)
+    }
+    ///Bit 24 - VBATEN
+    #[inline(always)]
+    pub fn vbaten(&self) -> VBATEN_R {
+        VBATEN_R::new(((self.bits >> 24) & 1) != 0)
+    }
+}
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CCR")
+            .field("vbaten", &self.vbaten())
+            .field("vsensesel", &self.vsensesel())
+            .field("vrefen", &self.vrefen())
+            .field("presc", &self.presc())
+            .finish()
+    }
+}
+impl W {
+    ///Bits 18:21 - PRESC
+    #[inline(always)]
+    pub fn presc(&mut self) -> PRESC_W<CCRrs> {
+        PRESC_W::new(self, 18)
+    }
+    ///Bit 22 - VREFEN
+    #[inline(always)]
+    pub fn vrefen(&mut self) -> VREFEN_W<CCRrs> {
+        VREFEN_W::new(self, 22)
+    }
+    ///Bit 23 - TSEN
+    #[inline(always)]
+    pub fn vsensesel(&mut self) -> VSENSESEL_W<CCRrs> {
+        VSENSESEL_W::new(self, 23)
+    }
+    ///Bit 24 - VBATEN
+    #[inline(always)]
+    pub fn vbaten(&mut self) -> VBATEN_W<CCRrs> {
+        VBATEN_W::new(self, 24)
+    }
+}
+/**ADC common configuration register
+
+You can [`read`](crate::Reg::read) this register and get [`ccr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
+
+See register [structure](https://stm32-rs.github.io/stm32-rs/STM32U535.html#ADC4:CCR)*/
+pub struct CCRrs;
+impl crate::RegisterSpec for CCRrs {
+    type Ux = u32;
+}
+///`read()` method returns [`ccr::R`](R) reader structure
+impl crate::Readable for CCRrs {}
+///`write(|w| ..)` method takes [`ccr::W`](W) writer structure
+impl crate::Writable for CCRrs {
+    type Safety = crate::Unsafe;
+}
+///`reset()` method sets CCR to value 0
+impl crate::Resettable for CCRrs {}

### external/vendor/stm32u5/src/stm32u535/adc4/cfgr1.rs
@@ -0,0 +1,1135 @@
+///Register `CFGR1` reader
+pub type R = crate::R<CFGR1rs>;
+///Register `CFGR1` writer
+pub type W = crate::W<CFGR1rs>;
+/**DMAEN
+
+Value on reset: 0*/
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub enum DMAEN {
+    ///0: DMA disabled
+    Disabled = 0,
+    ///1: DMA enabled
+    Enabled = 1,
+}
+impl From<DMAEN> for bool {
+    #[inline(always)]
+    fn from(variant: DMAEN) -> Self {
+        variant as u8 != 0
+    }
+}
+///Field `DMAEN` reader - DMAEN
+pub type DMAEN_R = crate::BitReader<DMAEN>;
+impl DMAEN_R {
+    ///Get enumerated values variant
+    #[inline(always)]
+    pub const fn variant(&self) -> DMAEN {
+        match self.bits {
+            false => DMAEN::Disabled,
+            true => DMAEN::Enabled,
+        }
+    }
+    ///DMA disabled
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == DMAEN::Disabled
+    }
+    ///DMA enabled
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == DMAEN::Enabled
+    }
+}
+///Field `DMAEN` writer - DMAEN
+pub type DMAEN_W<'a, REG> = crate::BitWriter<'a, REG, DMAEN>;
+impl<'a, REG> DMAEN_W<'a, REG>
+where
+    REG: crate::Writable + crate::RegisterSpec,
+{
+    ///DMA disabled
+    #[inline(always)]
+    pub fn disabled(self) -> &'a mut crate::W<REG> {
+        self.variant(DMAEN::Disabled)
+    }
+    ///DMA enabled
+    #[inline(always)]
+    pub fn enabled(self) -> &'a mut crate::W<REG> {
+        self.variant(DMAEN::Enabled)
+    }
+}
+/**DMACFG
+
+Value on reset: 0*/
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub enum DMACFG {
+    ///0: One-shot mode selected
+    OneShot = 0,
+    ///1: Circular mode selected
+    Circular = 1,
+}
+impl From<DMACFG> for bool {
+    #[inline(always)]
+    fn from(variant: DMACFG) -> Self {
+        variant as u8 != 0
+    }
+}
+///Field `DMACFG` reader - DMACFG
+pub type DMACFG_R = crate::BitReader<DMACFG>;
+impl DMACFG_R {
+    ///Get enumerated values variant
+    #[inline(always)]
+    pub const fn variant(&self) -> DMACFG {
+        match self.bits {
+            false => DMACFG::OneShot,
+            true => DMACFG::Circular,
+        }
+    }
+    ///One-shot mode selected
+    #[inline(always)]
+    pub fn is_one_shot(&self) -> bool {
+        *self == DMACFG::OneShot
+    }
+    ///Circular mode selected
+    #[inline(always)]
+    pub fn is_circular(&self) -> bool {
+        *self == DMACFG::Circular
+    }
+}
+///Field `DMACFG` writer - DMACFG
+pub type DMACFG_W<'a, REG> = crate::BitWriter<'a, REG, DMACFG>;
+impl<'a, REG> DMACFG_W<'a, REG>
+where
+    REG: crate::Writable + crate::RegisterSpec,
+{
+    ///One-shot mode selected
+    #[inline(always)]
+    pub fn one_shot(self) -> &'a mut crate::W<REG> {
+        self.variant(DMACFG::OneShot)
+    }
+    ///Circular mode selected
+    #[inline(always)]
+    pub fn circular(self) -> &'a mut crate::W<REG> {
+        self.variant(DMACFG::Circular)
+    }
+}
+/**RES
+
+Value on reset: 0*/
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+#[repr(u8)]
+pub enum RES {
+    ///0: 12 bits
+    TwelveBit = 0,
+    ///1: 10 bits
+    TenBit = 1,
+    ///2: 8 bits
+    EightBit = 2,
+    ///3: 6 bits
+    SixBit = 3,
+}
+impl From<RES> for u8 {
+    #[inline(always)]
+    fn from(variant: RES) -> Self {
+        variant as _
+    }
+}
+impl crate::FieldSpec for RES {
+    type Ux = u8;
+}
+impl crate::IsEnum for RES {}
+///Field `RES` reader - RES
+pub type RES_R = crate::FieldReader<RES>;
+impl RES_R {
+    ///Get enumerated values variant
+    #[inline(always)]
+    pub const fn variant(&self) -> RES {
+        match self.bits {
+            0 => RES::TwelveBit,
+            1 => RES::TenBit,
+            2 => RES::EightBit,
+            3 => RES::SixBit,
+            _ => unreachable!(),
+        }
+    }
+    ///12 bits
+    #[inline(always)]
+    pub fn is_twelve_bit(&self) -> bool {
+        *self == RES::TwelveBit
+    }
+    ///10 bits
+    #[inline(always)]
+    pub fn is_ten_bit(&self) -> bool {
+        *self == RES::TenBit
+    }
+    ///8 bits
+    #[inline(always)]
+    pub fn is_eight_bit(&self) -> bool {
+        *self == RES::EightBit
+    }
+    ///6 bits
+    #[inline(always)]
+    pub fn is_six_bit(&self) -> bool {
+        *self == RES::SixBit
+    }
+}
+///Field `RES` writer - RES
+pub type RES_W<'a, REG> = crate::FieldWriter<'a, REG, 2, RES, crate::Safe>;
+impl<'a, REG> RES_W<'a, REG>
+where
+    REG: crate::Writable + crate::RegisterSpec,
+    REG::Ux: From<u8>,
+{
+    ///12 bits
+    #[inline(always)]
+    pub fn twelve_bit(self) -> &'a mut crate::W<REG> {
+        self.variant(RES::TwelveBit)
+    }
+    ///10 bits
+    #[inline(always)]
+    pub fn ten_bit(self) -> &'a mut crate::W<REG> {
+        self.variant(RES::TenBit)
+    }
+    ///8 bits
+    #[inline(always)]
+    pub fn eight_bit(self) -> &'a mut crate::W<REG> {
+        self.variant(RES::EightBit)
+    }
+    ///6 bits
+    #[inline(always)]
+    pub fn six_bit(self) -> &'a mut crate::W<REG> {
+        self.variant(RES::SixBit)
+    }
+}
+/**SCANDIR
+
+Value on reset: 0*/
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub enum SCANDIR {
+    ///0: Upward scan sequence (from CHSEL0 to CHSEL23)
+    Upward = 0,
+    ///1: Downward scan sequence (from CHSEL23 to CHSEL0)
+    Downward = 1,
+}
+impl From<SCANDIR> for bool {
+    #[inline(always)]
+    fn from(variant: SCANDIR) -> Self {
+        variant as u8 != 0
+    }
+}
+///Field `SCANDIR` reader - SCANDIR
+pub type SCANDIR_R = crate::BitReader<SCANDIR>;
+impl SCANDIR_R {
+    ///Get enumerated values variant
+    #[inline(always)]
+    pub const fn variant(&self) -> SCANDIR {
+        match self.bits {
+            false => SCANDIR::Upward,
+            true => SCANDIR::Downward,
+        }
+    }
+    ///Upward scan sequence (from CHSEL0 to CHSEL23)
+    #[inline(always)]
+    pub fn is_upward(&self) -> bool {
+        *self == SCANDIR::Upward
+    }
+    ///Downward scan sequence (from CHSEL23 to CHSEL0)
+    #[inline(always)]
+    pub fn is_downward(&self) -> bool {
+        *self == SCANDIR::Downward
+    }
+}
+///Field `SCANDIR` writer - SCANDIR
+pub type SCANDIR_W<'a, REG> = crate::BitWriter<'a, REG, SCANDIR>;
+impl<'a, REG> SCANDIR_W<'a, REG>
+where
+    REG: crate::Writable + crate::RegisterSpec,
+{
+    ///Upward scan sequence (from CHSEL0 to CHSEL23)
+    #[inline(always)]
+    pub fn upward(self) -> &'a mut crate::W<REG> {
+        self.variant(SCANDIR::Upward)
+    }
+    ///Downward scan sequence (from CHSEL23 to CHSEL0)
+    #[inline(always)]
+    pub fn downward(self) -> &'a mut crate::W<REG> {
+        self.variant(SCANDIR::Downward)
+    }
+}
+/**ALIGN
+
+Value on reset: 0*/
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub enum ALIGN {
+    ///0: Right alignment
+    Right = 0,
+    ///1: Left alignment
+    Left = 1,
+}
+impl From<ALIGN> for bool {
+    #[inline(always)]
+    fn from(variant: ALIGN) -> Self {
+        variant as u8 != 0
+    }
+}
+///Field `ALIGN` reader - ALIGN
+pub type ALIGN_R = crate::BitReader<ALIGN>;
+impl ALIGN_R {
+    ///Get enumerated values variant
+    #[inline(always)]
+    pub const fn variant(&self) -> ALIGN {
+        match self.bits {
+            false => ALIGN::Right,
+            true => ALIGN::Left,
+        }
+    }
+    ///Right alignment
+    #[inline(always)]
+    pub fn is_right(&self) -> bool {
+        *self == ALIGN::Right
+    }
+    ///Left alignment
+    #[inline(always)]
+    pub fn is_left(&self) -> bool {
+        *self == ALIGN::Left
+    }
+}
+///Field `ALIGN` writer - ALIGN
+pub type ALIGN_W<'a, REG> = crate::BitWriter<'a, REG, ALIGN>;
+impl<'a, REG> ALIGN_W<'a, REG>
+where
+    REG: crate::Writable + crate::RegisterSpec,
+{
+    ///Right alignment
+    #[inline(always)]
+    pub fn right(self) -> &'a mut crate::W<REG> {
+        self.variant(ALIGN::Right)
+    }
+    ///Left alignment
+    #[inline(always)]
+    pub fn left(self) -> &'a mut crate::W<REG> {
+        self.variant(ALIGN::Left)
+    }
+}
+/**EXTSEL
+
+Value on reset: 0*/
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+#[repr(u8)]
+pub enum EXTSEL {
+    ///0: tim1_trgo2
+    Tim1Trgo2 = 0,
+    ///1: tim1_oc4
+    Tim1Oc4 = 1,
+    ///2: tim2_trgo
+    Tim2Trgo = 2,
+    ///3: tim15_trgo
+    Tim15Trgo = 3,
+    ///4: tim6_trgo
+    Tim6Trgo = 4,
+    ///5: lptim1_ch1
+    Lptim1Ch1 = 5,
+    ///6: lptim3_ch2
+    Lptim3Ch2 = 6,
+    ///7: exti15
+    Exti15 = 7,
+}
+impl From<EXTSEL> for u8 {
+    #[inline(always)]
+    fn from(variant: EXTSEL) -> Self {
+        variant as _
+    }
+}
+impl crate::FieldSpec for EXTSEL {
+    type Ux = u8;
+}
+impl crate::IsEnum for EXTSEL {}
+///Field `EXTSEL` reader - EXTSEL
+pub type EXTSEL_R = crate::FieldReader<EXTSEL>;
+impl EXTSEL_R {
+    ///Get enumerated values variant
+    #[inline(always)]
+    pub const fn variant(&self) -> EXTSEL {
+        match self.bits {
+            0 => EXTSEL::Tim1Trgo2,
+            1 => EXTSEL::Tim1Oc4,
+            2 => EXTSEL::Tim2Trgo,
+            3 => EXTSEL::Tim15Trgo,
+            4 => EXTSEL::Tim6Trgo,
+            5 => EXTSEL::Lptim1Ch1,
+            6 => EXTSEL::Lptim3Ch2,
+            7 => EXTSEL::Exti15,
+            _ => unreachable!(),
+        }
+    }
+    ///tim1_trgo2
+    #[inline(always)]
+    pub fn is_tim1_trgo2(&self) -> bool {
+        *self == EXTSEL::Tim1Trgo2
+    }
+    ///tim1_oc4
+    #[inline(always)]
+    pub fn is_tim1_oc4(&self) -> bool {
+        *self == EXTSEL::Tim1Oc4
+    }
+    ///tim2_trgo
+    #[inline(always)]
+    pub fn is_tim2_trgo(&self) -> bool {
+        *self == EXTSEL::Tim2Trgo
+    }
+    ///tim15_trgo
+    #[inline(always)]
+    pub fn is_tim15_trgo(&self) -> bool {
+        *self == EXTSEL::Tim15Trgo
+    }
+    ///tim6_trgo
+    #[inline(always)]
+    pub fn is_tim6_trgo(&self) -> bool {
+        *self == EXTSEL::Tim6Trgo
+    }
+    ///lptim1_ch1
+    #[inline(always)]
+    pub fn is_lptim1_ch1(&self) -> bool {
+        *self == EXTSEL::Lptim1Ch1
+    }
+    ///lptim3_ch2
+    #[inline(always)]
+    pub fn is_lptim3_ch2(&self) -> bool {
+        *self == EXTSEL::Lptim3Ch2
+    }
+    ///exti15
+    #[inline(always)]
+    pub fn is_exti15(&self) -> bool {
+        *self == EXTSEL::Exti15
+    }
+}
+///Field `EXTSEL` writer - EXTSEL
+pub type EXTSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3, EXTSEL, crate::Safe>;
+impl<'a, REG> EXTSEL_W<'a, REG>
+where
+    REG: crate::Writable + crate::RegisterSpec,
+    REG::Ux: From<u8>,
+{
+    ///tim1_trgo2
+    #[inline(always)]
+    pub fn tim1_trgo2(self) -> &'a mut crate::W<REG> {
+        self.variant(EXTSEL::Tim1Trgo2)
+    }
+    ///tim1_oc4
+    #[inline(always)]
+    pub fn tim1_oc4(self) -> &'a mut crate::W<REG> {
+        self.variant(EXTSEL::Tim1Oc4)
+    }
+    ///tim2_trgo
+    #[inline(always)]
+    pub fn tim2_trgo(self) -> &'a mut crate::W<REG> {
+        self.variant(EXTSEL::Tim2Trgo)
+    }
+    ///tim15_trgo
+    #[inline(always)]
+    pub fn tim15_trgo(self) -> &'a mut crate::W<REG> {
+        self.variant(EXTSEL::Tim15Trgo)
+    }
+    ///tim6_trgo
+    #[inline(always)]
+    pub fn tim6_trgo(self) -> &'a mut crate::W<REG> {
+        self.variant(EXTSEL::Tim6Trgo)
+    }
+    ///lptim1_ch1
+    #[inline(always)]
+    pub fn lptim1_ch1(self) -> &'a mut crate::W<REG> {
+        self.variant(EXTSEL::Lptim1Ch1)
+    }
+    ///lptim3_ch2
+    #[inline(always)]
+    pub fn lptim3_ch2(self) -> &'a mut crate::W<REG> {
+        self.variant(EXTSEL::Lptim3Ch2)
+    }
+    ///exti15
+    #[inline(always)]
+    pub fn exti15(self) -> &'a mut crate::W<REG> {
+        self.variant(EXTSEL::Exti15)
+    }
+}
+/**EXTEN
+
+Value on reset: 0*/
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+#[repr(u8)]
+pub enum EXTEN {
+    ///0: Hardware trigger detection disabled (conversions can be launched by software)
+    Disabled = 0,
+    ///1: Hardware trigger detection on the rising edge
+    RisingEdge = 1,
+    ///2: Hardware trigger detection on the falling edge
+    FallingEdge = 2,
+    ///3: Hardware trigger detection on both the rising and falling edges
+    BothEdges = 3,
+}
+impl From<EXTEN> for u8 {
+    #[inline(always)]
+    fn from(variant: EXTEN) -> Self {
+        variant as _
+    }
+}
+impl crate::FieldSpec for EXTEN {
+    type Ux = u8;
+}
+impl crate::IsEnum for EXTEN {}
+///Field `EXTEN` reader - EXTEN
+pub type EXTEN_R = crate::FieldReader<EXTEN>;
+impl EXTEN_R {
+    ///Get enumerated values variant
+    #[inline(always)]
+    pub const fn variant(&self) -> EXTEN {
+        match self.bits {
+            0 => EXTEN::Disabled,
+            1 => EXTEN::RisingEdge,
+            2 => EXTEN::FallingEdge,
+            3 => EXTEN::BothEdges,
+            _ => unreachable!(),
+        }
+    }
+    ///Hardware trigger detection disabled (conversions can be launched by software)
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == EXTEN::Disabled
+    }
+    ///Hardware trigger detection on the rising edge
+    #[inline(always)]
+    pub fn is_rising_edge(&self) -> bool {
+        *self == EXTEN::RisingEdge
+    }
+    ///Hardware trigger detection on the falling edge
+    #[inline(always)]
+    pub fn is_falling_edge(&self) -> bool {
+        *self == EXTEN::FallingEdge
+    }
+    ///Hardware trigger detection on both the rising and falling edges
+    #[inline(always)]
+    pub fn is_both_edges(&self) -> bool {
+        *self == EXTEN::BothEdges
+    }
+}
+///Field `EXTEN` writer - EXTEN
+pub type EXTEN_W<'a, REG> = crate::FieldWriter<'a, REG, 2, EXTEN, crate::Safe>;
+impl<'a, REG> EXTEN_W<'a, REG>
+where
+    REG: crate::Writable + crate::RegisterSpec,
+    REG::Ux: From<u8>,
+{
+    ///Hardware trigger detection disabled (conversions can be launched by software)
+    #[inline(always)]
+    pub fn disabled(self) -> &'a mut crate::W<REG> {
+        self.variant(EXTEN::Disabled)
+    }
+    ///Hardware trigger detection on the rising edge
+    #[inline(always)]
+    pub fn rising_edge(self) -> &'a mut crate::W<REG> {
+        self.variant(EXTEN::RisingEdge)
+    }
+    ///Hardware trigger detection on the falling edge
+    #[inline(always)]
+    pub fn falling_edge(self) -> &'a mut crate::W<REG> {
+        self.variant(EXTEN::FallingEdge)
+    }
+    ///Hardware trigger detection on both the rising and falling edges
+    #[inline(always)]
+    pub fn both_edges(self) -> &'a mut crate::W<REG> {
+        self.variant(EXTEN::BothEdges)
+    }
+}
+/**OVRMOD
+
+Value on reset: 0*/
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub enum OVRMOD {
+    ///0: ADC_DR register is preserved with the old data when an overrun is detected
+    Preserve = 0,
+    ///1: ADC_DR register is overwritten with the last conversion result when an overrun is detected
+    Overwrite = 1,
+}
+impl From<OVRMOD> for bool {
+    #[inline(always)]
+    fn from(variant: OVRMOD) -> Self {
+        variant as u8 != 0
+    }
+}
+///Field `OVRMOD` reader - OVRMOD
+pub type OVRMOD_R = crate::BitReader<OVRMOD>;
+impl OVRMOD_R {
+    ///Get enumerated values variant
+    #[inline(always)]
+    pub const fn variant(&self) -> OVRMOD {
+        match self.bits {
+            false => OVRMOD::Preserve,
+            true => OVRMOD::Overwrite,
+        }
+    }
+    ///ADC_DR register is preserved with the old data when an overrun is detected
+    #[inline(always)]
+    pub fn is_preserve(&self) -> bool {
+        *self == OVRMOD::Preserve
+    }
+    ///ADC_DR register is overwritten with the last conversion result when an overrun is detected
+    #[inline(always)]
+    pub fn is_overwrite(&self) -> bool {
+        *self == OVRMOD::Overwrite
+    }
+}
+///Field `OVRMOD` writer - OVRMOD
+pub type OVRMOD_W<'a, REG> = crate::BitWriter<'a, REG, OVRMOD>;
+impl<'a, REG> OVRMOD_W<'a, REG>
+where
+    REG: crate::Writable + crate::RegisterSpec,
+{
+    ///ADC_DR register is preserved with the old data when an overrun is detected
+    #[inline(always)]
+    pub fn preserve(self) -> &'a mut crate::W<REG> {
+        self.variant(OVRMOD::Preserve)
+    }
+    ///ADC_DR register is overwritten with the last conversion result when an overrun is detected
+    #[inline(always)]
+    pub fn overwrite(self) -> &'a mut crate::W<REG> {
+        self.variant(OVRMOD::Overwrite)
+    }
+}
+/**CONT
+
+Value on reset: 0*/
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub enum CONT {
+    ///0: Single conversion mode
+    Single = 0,
+    ///1: Continuous conversion mode
+    Continuous = 1,
+}
+impl From<CONT> for bool {
+    #[inline(always)]
+    fn from(variant: CONT) -> Self {
+        variant as u8 != 0
+    }
+}
+///Field `CONT` reader - CONT
+pub type CONT_R = crate::BitReader<CONT>;
+impl CONT_R {
+    ///Get enumerated values variant
+    #[inline(always)]
+    pub const fn variant(&self) -> CONT {
+        match self.bits {
+            false => CONT::Single,
+            true => CONT::Continuous,
+        }
+    }
+    ///Single conversion mode
+    #[inline(always)]
+    pub fn is_single(&self) -> bool {
+        *self == CONT::Single
+    }
+    ///Continuous conversion mode
+    #[inline(always)]
+    pub fn is_continuous(&self) -> bool {
+        *self == CONT::Continuous
+    }
+}
+///Field `CONT` writer - CONT
+pub type CONT_W<'a, REG> = crate::BitWriter<'a, REG, CONT>;
+impl<'a, REG> CONT_W<'a, REG>
+where
+    REG: crate::Writable + crate::RegisterSpec,
+{
+    ///Single conversion mode
+    #[inline(always)]
+    pub fn single(self) -> &'a mut crate::W<REG> {
+        self.variant(CONT::Single)
+    }
+    ///Continuous conversion mode
+    #[inline(always)]
+    pub fn continuous(self) -> &'a mut crate::W<REG> {
+        self.variant(CONT::Continuous)
+    }
+}
+/**WAIT
+
+Value on reset: 0*/
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub enum WAIT {
+    ///0: Wait conversion mode off
+    Disabled = 0,
+    ///1: Wait conversion mode on
+    Enabled = 1,
+}
+impl From<WAIT> for bool {
+    #[inline(always)]
+    fn from(variant: WAIT) -> Self {
+        variant as u8 != 0
+    }
+}
+///Field `WAIT` reader - WAIT
+pub type WAIT_R = crate::BitReader<WAIT>;
+impl WAIT_R {
+    ///Get enumerated values variant
+    #[inline(always)]
+    pub const fn variant(&self) -> WAIT {
+        match self.bits {
+            false => WAIT::Disabled,
+            true => WAIT::Enabled,
+        }
+    }
+    ///Wait conversion mode off
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == WAIT::Disabled
+    }
+    ///Wait conversion mode on
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == WAIT::Enabled
+    }
+}
+///Field `WAIT` writer - WAIT
+pub type WAIT_W<'a, REG> = crate::BitWriter<'a, REG, WAIT>;
+impl<'a, REG> WAIT_W<'a, REG>
+where
+    REG: crate::Writable + crate::RegisterSpec,
+{
+    ///Wait conversion mode off
+    #[inline(always)]
+    pub fn disabled(self) -> &'a mut crate::W<REG> {
+        self.variant(WAIT::Disabled)
+    }
+    ///Wait conversion mode on
+    #[inline(always)]
+    pub fn enabled(self) -> &'a mut crate::W<REG> {
+        self.variant(WAIT::Enabled)
+    }
+}
+/**DISCEN
+
+Value on reset: 0*/
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub enum DISCEN {
+    ///0: Discontinuous mode for regular channels disabled
+    Disabled = 0,
+    ///1: Discontinuous mode for regular channels enabled
+    Enabled = 1,
+}
+impl From<DISCEN> for bool {
+    #[inline(always)]
+    fn from(variant: DISCEN) -> Self {
+        variant as u8 != 0
+    }
+}
+///Field `DISCEN` reader - DISCEN
+pub type DISCEN_R = crate::BitReader<DISCEN>;
+impl DISCEN_R {
+    ///Get enumerated values variant
+    #[inline(always)]
+    pub const fn variant(&self) -> DISCEN {
+        match self.bits {
+            false => DISCEN::Disabled,
+            true => DISCEN::Enabled,
+        }
+    }
+    ///Discontinuous mode for regular channels disabled
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == DISCEN::Disabled
+    }
+    ///Discontinuous mode for regular channels enabled
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == DISCEN::Enabled
+    }
+}
+///Field `DISCEN` writer - DISCEN
+pub type DISCEN_W<'a, REG> = crate::BitWriter<'a, REG, DISCEN>;
+impl<'a, REG> DISCEN_W<'a, REG>
+where
+    REG: crate::Writable + crate::RegisterSpec,
+{
+    ///Discontinuous mode for regular channels disabled
+    #[inline(always)]
+    pub fn disabled(self) -> &'a mut crate::W<REG> {
+        self.variant(DISCEN::Disabled)
+    }
+    ///Discontinuous mode for regular channels enabled
+    #[inline(always)]
+    pub fn enabled(self) -> &'a mut crate::W<REG> {
+        self.variant(DISCEN::Enabled)
+    }
+}
+/**CHSELRMOD
+
+Value on reset: 0*/
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub enum CHSELRMOD {
+    ///0: Each bit of the ADC_CHSELR register enables an input
+    BitPerInput = 0,
+    ///1: ADC_CHSELR register is able to sequence up to 8 channels
+    Sequence = 1,
+}
+impl From<CHSELRMOD> for bool {
+    #[inline(always)]
+    fn from(variant: CHSELRMOD) -> Self {
+        variant as u8 != 0
+    }
+}
+///Field `CHSELRMOD` reader - CHSELRMOD
+pub type CHSELRMOD_R = crate::BitReader<CHSELRMOD>;
+impl CHSELRMOD_R {
+    ///Get enumerated values variant
+    #[inline(always)]
+    pub const fn variant(&self) -> CHSELRMOD {
+        match self.bits {
+            false => CHSELRMOD::BitPerInput,
+            true => CHSELRMOD::Sequence,
+        }
+    }
+    ///Each bit of the ADC_CHSELR register enables an input
+    #[inline(always)]
+    pub fn is_bit_per_input(&self) -> bool {
+        *self == CHSELRMOD::BitPerInput
+    }
+    ///ADC_CHSELR register is able to sequence up to 8 channels
+    #[inline(always)]
+    pub fn is_sequence(&self) -> bool {
+        *self == CHSELRMOD::Sequence
+    }
+}
+///Field `CHSELRMOD` writer - CHSELRMOD
+pub type CHSELRMOD_W<'a, REG> = crate::BitWriter<'a, REG, CHSELRMOD>;
+impl<'a, REG> CHSELRMOD_W<'a, REG>
+where
+    REG: crate::Writable + crate::RegisterSpec,
+{
+    ///Each bit of the ADC_CHSELR register enables an input
+    #[inline(always)]
+    pub fn bit_per_input(self) -> &'a mut crate::W<REG> {
+        self.variant(CHSELRMOD::BitPerInput)
+    }
+    ///ADC_CHSELR register is able to sequence up to 8 channels
+    #[inline(always)]
+    pub fn sequence(self) -> &'a mut crate::W<REG> {
+        self.variant(CHSELRMOD::Sequence)
+    }
+}
+/**AWD1SGL
+
+Value on reset: 0*/
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub enum AWD1SGL {
+    ///0: Analog watchdog 1 enabled on all channels
+    AllChannels = 0,
+    ///1: Analog watchdog 1 enabled on a single channel
+    SingleChannel = 1,
+}
+impl From<AWD1SGL> for bool {
+    #[inline(always)]
+    fn from(variant: AWD1SGL) -> Self {
+        variant as u8 != 0
+    }
+}
+///Field `AWD1SGL` reader - AWD1SGL
+pub type AWD1SGL_R = crate::BitReader<AWD1SGL>;
+impl AWD1SGL_R {
+    ///Get enumerated values variant
+    #[inline(always)]
+    pub const fn variant(&self) -> AWD1SGL {
+        match self.bits {
+            false => AWD1SGL::AllChannels,
+            true => AWD1SGL::SingleChannel,
+        }
+    }
+    ///Analog watchdog 1 enabled on all channels
+    #[inline(always)]
+    pub fn is_all_channels(&self) -> bool {
+        *self == AWD1SGL::AllChannels
+    }
+    ///Analog watchdog 1 enabled on a single channel
+    #[inline(always)]
+    pub fn is_single_channel(&self) -> bool {
+        *self == AWD1SGL::SingleChannel
+    }
+}
+///Field `AWD1SGL` writer - AWD1SGL
+pub type AWD1SGL_W<'a, REG> = crate::BitWriter<'a, REG, AWD1SGL>;
+impl<'a, REG> AWD1SGL_W<'a, REG>
+where
+    REG: crate::Writable + crate::RegisterSpec,
+{
+    ///Analog watchdog 1 enabled on all channels
+    #[inline(always)]
+    pub fn all_channels(self) -> &'a mut crate::W<REG> {
+        self.variant(AWD1SGL::AllChannels)
+    }
+    ///Analog watchdog 1 enabled on a single channel
+    #[inline(always)]
+    pub fn single_channel(self) -> &'a mut crate::W<REG> {
+        self.variant(AWD1SGL::SingleChannel)
+    }
+}
+/**AWD1EN
+
+Value on reset: 0*/
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub enum AWD1EN {
+    ///0: Analog watchdog 1 disabled on regular channels
+    Disabled = 0,
+    ///1: Analog watchdog 1 enabled on regular channels
+    Enabled = 1,
+}
+impl From<AWD1EN> for bool {
+    #[inline(always)]
+    fn from(variant: AWD1EN) -> Self {
+        variant as u8 != 0
+    }
+}
+///Field `AWD1EN` reader - AWD1EN
+pub type AWD1EN_R = crate::BitReader<AWD1EN>;
+impl AWD1EN_R {
+    ///Get enumerated values variant
+    #[inline(always)]
+    pub const fn variant(&self) -> AWD1EN {
+        match self.bits {
+            false => AWD1EN::Disabled,
+            true => AWD1EN::Enabled,
+        }
+    }
+    ///Analog watchdog 1 disabled on regular channels
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == AWD1EN::Disabled
+    }
+    ///Analog watchdog 1 enabled on regular channels
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == AWD1EN::Enabled
+    }
+}
+///Field `AWD1EN` writer - AWD1EN
+pub type AWD1EN_W<'a, REG> = crate::BitWriter<'a, REG, AWD1EN>;
+impl<'a, REG> AWD1EN_W<'a, REG>
+where
+    REG: crate::Writable + crate::RegisterSpec,
+{
+    ///Analog watchdog 1 disabled on regular channels
+    #[inline(always)]
+    pub fn disabled(self) -> &'a mut crate::W<REG> {
+        self.variant(AWD1EN::Disabled)
+    }
+    ///Analog watchdog 1 enabled on regular channels
+    #[inline(always)]
+    pub fn enabled(self) -> &'a mut crate::W<REG> {
+        self.variant(AWD1EN::Enabled)
+    }
+}
+///Field `AWD1CH` reader - AWD1CH
+pub type AWD1CH_R = crate::FieldReader;
+///Field `AWD1CH` writer - AWD1CH
+pub type AWD1CH_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
+impl R {
+    ///Bit 0 - DMAEN
+    #[inline(always)]
+    pub fn dmaen(&self) -> DMAEN_R {
+        DMAEN_R::new((self.bits & 1) != 0)
+    }
+    ///Bit 1 - DMACFG
+    #[inline(always)]
+    pub fn dmacfg(&self) -> DMACFG_R {
+        DMACFG_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    ///Bits 2:3 - RES
+    #[inline(always)]
+    pub fn res(&self) -> RES_R {
+        RES_R::new(((self.bits >> 2) & 3) as u8)
+    }
+    ///Bit 4 - SCANDIR
+    #[inline(always)]
+    pub fn scandir(&self) -> SCANDIR_R {
+        SCANDIR_R::new(((self.bits >> 4) & 1) != 0)
+    }
+    ///Bit 5 - ALIGN
+    #[inline(always)]
+    pub fn align(&self) -> ALIGN_R {
+        ALIGN_R::new(((self.bits >> 5) & 1) != 0)
+    }
+    ///Bits 6:8 - EXTSEL
+    #[inline(always)]
+    pub fn extsel(&self) -> EXTSEL_R {
+        EXTSEL_R::new(((self.bits >> 6) & 7) as u8)
+    }
+    ///Bits 10:11 - EXTEN
+    #[inline(always)]
+    pub fn exten(&self) -> EXTEN_R {
+        EXTEN_R::new(((self.bits >> 10) & 3) as u8)
+    }
+    ///Bit 12 - OVRMOD
+    #[inline(always)]
+    pub fn ovrmod(&self) -> OVRMOD_R {
+        OVRMOD_R::new(((self.bits >> 12) & 1) != 0)
+    }
+    ///Bit 13 - CONT
+    #[inline(always)]
+    pub fn cont(&self) -> CONT_R {
+        CONT_R::new(((self.bits >> 13) & 1) != 0)
+    }
+    ///Bit 14 - WAIT
+    #[inline(always)]
+    pub fn wait(&self) -> WAIT_R {
+        WAIT_R::new(((self.bits >> 14) & 1) != 0)
+    }
+    ///Bit 16 - DISCEN
+    #[inline(always)]
+    pub fn discen(&self) -> DISCEN_R {
+        DISCEN_R::new(((self.bits >> 16) & 1) != 0)
+    }
+    ///Bit 21 - CHSELRMOD
+    #[inline(always)]
+    pub fn chselrmod(&self) -> CHSELRMOD_R {
+        CHSELRMOD_R::new(((self.bits >> 21) & 1) != 0)
+    }
+    ///Bit 22 - AWD1SGL
+    #[inline(always)]
+    pub fn awd1sgl(&self) -> AWD1SGL_R {
+        AWD1SGL_R::new(((self.bits >> 22) & 1) != 0)
+    }
+    ///Bit 23 - AWD1EN
+    #[inline(always)]
+    pub fn awd1en(&self) -> AWD1EN_R {
+        AWD1EN_R::new(((self.bits >> 23) & 1) != 0)
+    }
+    ///Bits 26:30 - AWD1CH
+    #[inline(always)]
+    pub fn awd1ch(&self) -> AWD1CH_R {
+        AWD1CH_R::new(((self.bits >> 26) & 0x1f) as u8)
+    }
+}
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CFGR1")
+            .field("awd1ch", &self.awd1ch())
+            .field("awd1en", &self.awd1en())
+            .field("awd1sgl", &self.awd1sgl())
+            .field("chselrmod", &self.chselrmod())
+            .field("discen", &self.discen())
+            .field("wait", &self.wait())
+            .field("cont", &self.cont())
+            .field("ovrmod", &self.ovrmod())
+            .field("exten", &self.exten())
+            .field("extsel", &self.extsel())
+            .field("align", &self.align())
+            .field("scandir", &self.scandir())
+            .field("res", &self.res())
+            .field("dmacfg", &self.dmacfg())
+            .field("dmaen", &self.dmaen())
+            .finish()
+    }
+}
+impl W {
+    ///Bit 0 - DMAEN
+    #[inline(always)]
+    pub fn dmaen(&mut self) -> DMAEN_W<CFGR1rs> {
+        DMAEN_W::new(self, 0)
+    }
+    ///Bit 1 - DMACFG
+    #[inline(always)]
+    pub fn dmacfg(&mut self) -> DMACFG_W<CFGR1rs> {
+        DMACFG_W::new(self, 1)
+    }
+    ///Bits 2:3 - RES
+    #[inline(always)]
+    pub fn res(&mut self) -> RES_W<CFGR1rs> {
+        RES_W::new(self, 2)
+    }
+    ///Bit 4 - SCANDIR
+    #[inline(always)]
+    pub fn scandir(&mut self) -> SCANDIR_W<CFGR1rs> {
+        SCANDIR_W::new(self, 4)
+    }
+    ///Bit 5 - ALIGN
+    #[inline(always)]
+    pub fn align(&mut self) -> ALIGN_W<CFGR1rs> {
+        ALIGN_W::new(self, 5)
+    }
+    ///Bits 6:8 - EXTSEL
+    #[inline(always)]
+    pub fn extsel(&mut self) -> EXTSEL_W<CFGR1rs> {
+        EXTSEL_W::new(self, 6)
+    }
+    ///Bits 10:11 - EXTEN
+    #[inline(always)]
+    pub fn exten(&mut self) -> EXTEN_W<CFGR1rs> {
+        EXTEN_W::new(self, 10)
+    }
+    ///Bit 12 - OVRMOD
+    #[inline(always)]
+    pub fn ovrmod(&mut self) -> OVRMOD_W<CFGR1rs> {
+        OVRMOD_W::new(self, 12)
+    }
+    ///Bit 13 - CONT
+    #[inline(always)]
+    pub fn cont(&mut self) -> CONT_W<CFGR1rs> {
+        CONT_W::new(self, 13)
+    }
+    ///Bit 14 - WAIT
+    #[inline(always)]
+    pub fn wait(&mut self) -> WAIT_W<CFGR1rs> {
+        WAIT_W::new(self, 14)
+    }
+    ///Bit 16 - DISCEN
+    #[inline(always)]
+    pub fn discen(&mut self) -> DISCEN_W<CFGR1rs> {
+        DISCEN_W::new(self, 16)
+    }
+    ///Bit 21 - CHSELRMOD
+    #[inline(always)]
+    pub fn chselrmod(&mut self) -> CHSELRMOD_W<CFGR1rs> {
+        CHSELRMOD_W::new(self, 21)
+    }
+    ///Bit 22 - AWD1SGL
+    #[inline(always)]
+    pub fn awd1sgl(&mut self) -> AWD1SGL_W<CFGR1rs> {
+        AWD1SGL_W::new(self, 22)
+    }
+    ///Bit 23 - AWD1EN
+    #[inline(always)]
+    pub fn awd1en(&mut self) -> AWD1EN_W<CFGR1rs> {
+        AWD1EN_W::new(self, 23)
+    }
+    ///Bits 26:30 - AWD1CH
+    #[inline(always)]
+    pub fn awd1ch(&mut self) -> AWD1CH_W<CFGR1rs> {
+        AWD1CH_W::new(self, 26)
+    }
+}
+/**ADC configuration register
+
+You can [`read`](crate::Reg::read) this register and get [`cfgr1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfgr1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
+
+See register [structure](https://stm32-rs.github.io/stm32-rs/STM32U535.html#ADC4:CFGR1)*/
+pub struct CFGR1rs;
+impl crate::RegisterSpec for CFGR1rs {
+    type Ux = u32;
+}
+///`read()` method returns [`cfgr1::R`](R) reader structure
+impl crate::Readable for CFGR1rs {}
+///`write(|w| ..)` method takes [`cfgr1::W`](W) writer structure
+impl crate::Writable for CFGR1rs {
+    type Safety = crate::Unsafe;
+}
+///`reset()` method sets CFGR1 to value 0
+impl crate::Resettable for CFGR1rs {}

### external/vendor/stm32u5/src/stm32u535/adc4/cfgr2.rs
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### external/vendor/stm32u5/src/stm32u535/adc4/chselr0.rs
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### external/vendor/stm32u5/src/stm32u535/adc4/chselr1.rs
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### external/vendor/stm32u5/src/stm32u535/adc4/cr.rs
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### external/vendor/stm32u5/src/stm32u535/adc4/dr.rs
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### external/vendor/stm32u5/src/stm32u535/adc4/ier.rs
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### external/vendor/stm32u5/src/stm32u535/adc4/isr.rs
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### external/vendor/stm32u5/src/stm32u535/adc4/or.rs
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### external/vendor/stm32u5/src/stm32u535/adc4/pwrr.rs
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### external/vendor/stm32u5/src/stm32u535/adc4/smpr.rs
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### external/vendor/stm32u5/src/stm32u535/adf1.rs
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### external/vendor/stm32u5/src/stm32u535/adf1/bsmx0cr.rs
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### external/vendor/stm32u5/src/stm32u535/adf1/ckgcr.rs
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### external/vendor/stm32u5/src/stm32u535/dlybos/cfgr.rs
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### external/vendor/stm32u5/src/stm32u535/exti/rpr1.rs
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### external/vendor/stm32u5/src/stm32u535/exti/seccfgr1.rs
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### external/vendor/stm32u5/src/stm32u535/fdcan1_ram.rs
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### external/vendor/stm32u5/src/stm32u535/fdcan1_ram/cccr.rs
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### external/vendor/stm32u5/src/stm32u535/fdcan1_ram/ckdiv.rs
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### external/vendor/stm32u5/src/stm32u535/fdcan1_ram/crel.rs
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### external/vendor/stm32u5/src/stm32u535/fdcan1_ram/dbtp.rs
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### external/vendor/stm32u5/src/stm32u535/fdcan1_ram/hpms.rs
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### external/vendor/stm32u5/src/stm32u535/fdcan1_ram/psr.rs
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### external/vendor/stm32u5/src/stm32u535/fdcan1_ram/rwd.rs
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### external/vendor/stm32u5/src/stm32u535/fdcan1_ram/rxf0s.rs
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### external/vendor/stm32u5/src/stm32u535/fdcan1_ram/rxf1s.rs
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### external/vendor/stm32u5/src/stm32u535/fdcan1_ram/tdcr.rs
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### external/vendor/stm32u5/src/stm32u535/fdcan1_ram/test.rs
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### external/vendor/stm32u5/src/stm32u535/fdcan1_ram/tocc.rs
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### external/vendor/stm32u5/src/stm32u535/fdcan1_ram/tscc.rs
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### external/vendor/stm32u5/src/stm32u535/fdcan1_ram/tscv.rs
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### external/vendor/stm32u5/src/stm32u535/fdcan1_ram/txbar.rs
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### external/vendor/stm32u5/src/stm32u535/fdcan1_ram/txbcf.rs
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### external/vendor/stm32u5/src/stm32u535/fdcan1_ram/txbcr.rs
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### external/vendor/stm32u5/src/stm32u535/fdcan1_ram/txbrp.rs
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### external/vendor/stm32u5/src/stm32u535/fdcan1_ram/txbtie.rs
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### external/vendor/stm32u5/src/stm32u535/fdcan1_ram/txbto.rs
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### external/vendor/stm32u5/src/stm32u535/fdcan1_ram/txfqs.rs
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### external/vendor/stm32u5/src/stm32u535/fdcan1_ram/xidam.rs
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### external/vendor/stm32u5/src/stm32u535/flash.rs
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